TWI232565B - Semiconductor chip-carrying substrate and its manufacturing method - Google Patents

Semiconductor chip-carrying substrate and its manufacturing method Download PDF

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TWI232565B
TWI232565B TW092133464A TW92133464A TWI232565B TW I232565 B TWI232565 B TW I232565B TW 092133464 A TW092133464 A TW 092133464A TW 92133464 A TW92133464 A TW 92133464A TW I232565 B TWI232565 B TW I232565B
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manufacturing
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TW092133464A
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TW200518292A (en
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Rung-Gan Lin
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Topson Opto Semiconductor Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

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Abstract

The present invention provides a semiconductor chip-carrying substrate and its manufacturing method. Plural first through holes are opened at the metal substrate that is provided with the upper and the lower conduction layers; and these through holes are stuffed to form plural plug pillars. Then, the second drilling process is conducted onto these plug pillars to form a protection layer on each hole wall of the first through holes. After that, a through hole conduction layer is formed on the protection layer so as to make both the upper and the lower parts of each through hole conduction layer contact with the upper and the lower conduction layers, respectively. Thus, the present invention provides a kind of dual-face connection-type metal substrate on which chips can be mounted directly to reach the effects of high heat dissipation, elongating lifetime of chip and increasing LED brightness.

Description

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【發明所屬之技術領域】 插且ίίΓ係有關一種半導體晶粒之基板,特別是關於一 、间政熱性且可雙面連接之金屬基板結構及 方 【先前技術】 隨著積體電路之電路接點的高度集積化及半導體晶粒 的廣泛應用,半導體元件之散熱結構更顯得重要。以發光 二,體(light-emitting diode,LED)為例,由於其具備 多彩、省電、壽命長且安全性高等優點,目前已被廣泛使 用在照明方面;然而LED元件卻普遍具有散熱不佳之問 題。 習知具散熱結構之發光二極體裝置如第一圖所示,係 將一封裝完成之發光二極體元件1〇利用表面黏著技術 (surface mount technology,SMT)黏著在銘板12 上,以 藉由鋁板12作為加強散熱之用;然而,此種方式必須先將 LED 晶粒 14與印刷電路板(printed circuit board PCB)16 打線連接而製作成一完整之發光二極體元件IQ之後,再將 發光二極體元件10以錫膏18黏著於鋁板12的單面線路20 上。此方式不僅增加製作成本及材料成本,同時LED晶粒 1 4之散熱路徑必須透過塑膠或陶瓷材質之印刷電路板丨6後 才能經由鋁板12散熱,而仍具有散熱效果不佳之缺失;再 者,由於LED晶粒14自身散熱不良,因此其發光強度及使 用壽命便會受到影響。又,此鋁板12僅適用於單面連接, 亦即鋁板12僅能做為發光二極體元件10的散熱板,而無法[Technical field to which the invention belongs] Insertion is related to a semiconductor die substrate, especially a metal substrate structure and method that can be connected on both sides and can be connected on both sides [prior art] With the circuit connection of integrated circuits The high degree of integration of dots and the widespread use of semiconductor grains make the heat dissipation structure of semiconductor elements even more important. Take light-emitting diode (LED) as an example. Because of its colorful, energy saving, long life and high safety, it has been widely used in lighting; however, LED components generally have poor heat dissipation. problem. As shown in the first figure, a conventional light emitting diode device with a heat dissipation structure is a packaged light emitting diode element 10 that is adhered to a nameplate 12 using surface mount technology (SMT) so that The aluminum plate 12 is used to enhance heat dissipation; however, this method must first connect the LED die 14 and printed circuit board PCB 16 to form a complete light-emitting diode element IQ, and then emit light. The diode element 10 is adhered to the single-sided circuit 20 of the aluminum plate 12 with a solder paste 18. This method not only increases the production cost and material cost, but also the heat dissipation path of the LED die 14 must pass through the printed circuit board made of plastic or ceramics, and then the heat can be dissipated through the aluminum plate 12, and still has the lack of poor heat dissipation effect; Due to the poor heat dissipation of the LED die 14, its luminous intensity and service life will be affected. In addition, the aluminum plate 12 is only suitable for single-sided connection, that is, the aluminum plate 12 can only be used as a heat sink of the light emitting diode element 10, and cannot be used.

五 發明說明 ⑵ 直接做為SMD型LED的基板。 之問題,提出 一種半導體晶 因此,本發明即針對上述 粒之承載基板及其製造方法。 【發明内容】 本發明 基板,利用 孔材料及鑽 型金屬基板 僅能提供單 本發明 體晶粒直接 直接散熱, 外部之金屬 力0 之主要目的,係在提供 在金屬基板上二次鑽孔 孔製程之控制,以製作 ’進而克服習知於塞孔 面連接型金屬基板之缺 之另一目的,係在提供 植入在此金屬材質之承 而毋需如習知般必須經 板散熱,進而有效提昇 一種半導 之做法, 出具導通 油墨上鑽 失。 一種金屬 載基板上 由印刷電 散熱半導 體晶粒之承載 配合適當之塞 孔之雙面連接 孔的困難點及 基板,使半導 ’俾使晶粒可 路板才能透過 體晶粒之能 本發明之再一目,係在提供一雙面連接型之金屬基 板,俾達成延長LED壽命及增加亮度之功效。 為達到上述之目的’本發明係先提供一金屬基板,該 金屬基板之^一相對表面各設有一上、下導電層,接著於該 金屬基板上形成複數導通孔,其中每一導通孔貫穿金屬基 板,且每一導通孔之孔壁上係先覆設有一保護層,再形成 一通孔導電層於保護層上。 底下藉由具體實施例配合所附的圖式詳加說明,當更 容易瞭解本發明之目的、技術内容、特點及其所達成之功 效0 1232565 五、發明說明(3) 【實施方式】 使用金屬基板的目的在於增強散熱性,金屬的導熱性 較陶瓷及塑膠為佳,當使用金屬基板做為半導體晶片如 LED晶片的載板時’可順利地將LED發光時所產生的熱能散 逸到空氣中。第二圖至第九圖為本發明於製作半導體晶粒 承載基板的各步驟構造剖視圖,請先參閱第七圖所示,為 本發明之結構示意圖,一半導體晶粒之承載基板3〇包括一 金屬基板32,常用者為紹板,在其二相對表面上各設有一 上、下結合穋層34、34’ ,以透過二結合膠層34、34,將二 上、下導電層36、36’分別結合於金屬基板32之二表面 上’該一導電層36、36通常係為銅層;另,金屬基板32 設有複數貫穿之導通孔38,在每一導通孔38之孔壁上依序 覆設有一保護層40及一通孔導電層42,保護層40係由環氧 樹脂系之樹脂所組成,而通孔導電層42通常為鍵銅層,且 其上、下部係分別與上、下導電層36、36,相接觸。 此半導體晶粒承載基板30在製作上必須克服導通孔38 於塞孔後,再於塞孔油墨上鑽孔且保持塞孔油墨不產生裂 隙(crack)及脫落的困難點,而本發明之製造方法即可克 服此問題。 在了解本發明之整體結構後,接續將詳細說明本發明 之各層結構及其製作方法,請參閱第二圖至第九圖所示。 首先,如第二圖所示,提供一金屬基板32,常用者為鋁 板’此金屬基板32之二相對表面上已透過二結合膠層34、 34’覆設有二上、下導電層36、36,,其通常為銅層;接著 tail 第7頁 1232565V. Description of the invention ⑵ As the substrate of SMD LED directly. In order to solve the problem, a semiconductor crystal is proposed. Therefore, the present invention is directed to the above-mentioned carrier substrate and a manufacturing method thereof. [Summary of the invention] The substrate of the present invention can only provide a single body crystal of the present invention to directly and directly dissipate heat using a hole material and a drilled metal substrate. The main purpose of the external metal force is to provide a secondary drilling hole in the metal substrate. The control of the process in order to make 'thereby overcoming the shortcomings of the metal substrate known in the plug hole surface connection type is to provide the implantation of this metal material without the need to heat through the board as is conventional, and Effectively improve a semiconducting method, and issue a continuum on the ink. Difficulties and substrates for supporting double-sided connection holes of printed electrical heat-dissipating semiconductor crystal grains with appropriate plug holes on a metal substrate, so that semiconducting semiconductors can be used to make the circuit board pass through the bulk crystal grains. Another goal is to provide a double-sided connection type metal substrate to achieve the effect of extending LED life and increasing brightness. In order to achieve the above-mentioned object, the present invention first provides a metal substrate, each of which is provided with an upper and a lower conductive layer on opposite surfaces thereof, and then a plurality of via holes are formed on the metal substrate, wherein each via hole penetrates the metal The substrate is provided with a protective layer on the hole wall of each via, and then a via conductive layer is formed on the protective layer. The detailed descriptions are provided below with specific examples and accompanying drawings to make it easier to understand the purpose, technical content, features and effects of the present invention. 0 1232565 V. Description of the invention (3) [Embodiment] Use of metal The purpose of the substrate is to enhance heat dissipation. The thermal conductivity of metal is better than that of ceramics and plastic. When a metal substrate is used as a carrier plate for a semiconductor wafer such as an LED wafer, it can smoothly dissipate the heat generated when the LED emits light into the air. . The second to ninth figures are cross-sectional views of the steps of the present invention in the process of manufacturing a semiconductor die carrier substrate. Please refer to FIG. 7 for a schematic diagram of the present invention. A semiconductor die carrier substrate 30 includes a The metal substrate 32, which is commonly used as a shao board, is provided with an upper and a lower bonding pad layer 34, 34 'on each of the two opposite surfaces, so that the two upper and lower conductive layers 36, 36 pass through the two bonding adhesive layers 34, 34. 'Respectively bonded to the two surfaces of the metal substrate 32' The one conductive layer 36, 36 is usually a copper layer; in addition, the metal substrate 32 is provided with a plurality of through-holes 38 penetrating therethrough. A protective layer 40 and a through-hole conductive layer 42 are sequentially formed. The protective layer 40 is composed of an epoxy resin, and the through-hole conductive layer 42 is usually a bond copper layer. The lower conductive layers 36, 36 are in contact. In the fabrication of the semiconductor die carrier substrate 30, it is necessary to overcome the difficulty of drilling the via hole ink after the via hole 38 is inserted in the via hole and keeping the via hole ink from cracking and falling off. Methods can overcome this problem. After understanding the overall structure of the present invention, the layers of the present invention and their manufacturing methods will be described in detail. Please refer to the second to ninth figures. First, as shown in the second figure, a metal substrate 32 is provided. An aluminum plate is commonly used. The two opposite surfaces of the metal substrate 32 have been covered with two upper and lower conductive layers 36, 34 through two bonding adhesive layers 34, 34 '. 36, which is usually a copper layer; then tail page 7 1232565

如第三圓所示進行第一次鑽孔作業,此步驟係對金屬基板 32鑽孔以形成複數個第一通孔38及定位孔39 ;接續如第四 圖所不進行塞孔作業,此步驟係以油墨將該等第一通孔38 填滿’填塞之油墨經烘烤固化及刷磨作業後,即形成複數 塞柱44 ’其中該油墨係為與金屬基板32附著性極佳之環氧 樹脂系材料者;接下來便如第五圖所示進行第二次鑽孔作 業’係對該等塞柱44鑽孔以形成複數第二通孔46,此第二 通孔46之孔徑係較第一通孔38小,藉以在第二次鑽孔後, 使每一第一通孔38之孔壁上各形成有一樹脂材質之保護層 40 〇 ,中’在第二次鑽孔之步驟中,由於上述塞孔油墨在 固化後的硬度高達9H以上,為避免鑽孔時油墨產生裂隙 (crack),所以鑽孔墊板必須使用硬度較高的材質,不能 使用一般鑽孔用的尿素板4FR4(FR4係指呈C-Stage的含膠 玻,布統稱),此鑽孔墊板通常為酚醛樹脂板;此外,第 一-人鑽孔之進刀速較佳者係控制在丨· 4至丨· 6 m/s,轉速較 佳者係控制在35至45 krpm,退刀速較佳者為24至26 m/S藉由此鑽孔條件配合適當之油墨,使塞孔柱44於鑽 孔時不會產生裂縫或脫落。 在第一通孔38上製作完成保護層40之後,接續如第六 圖所不旋即進行電鍍銅作業,進而在該等第二通孔46之 孔壁即保護層4〇)上形成通孔導電層42,且在上、下導電 36之表面亦一併形成鍍銅層47,使每一通孔導電 層之上、下部分別與該上、下導電層36、36,相接觸。The first drilling operation is performed as shown in the third circle. This step is to drill the metal substrate 32 to form a plurality of first through holes 38 and positioning holes 39. The plugging operation is not performed as shown in the fourth figure. The steps are to fill the first through holes 38 with ink to fill the stuffed ink. After baking and curing and brushing, a plurality of plugs 44 ′ are formed, wherein the ink is a ring with excellent adhesion to the metal substrate 32. For oxygen-based resin materials, the second drilling operation is performed as shown in the fifth figure. The holes 44 are drilled to form a plurality of second through-holes 46. The diameter of the second through-holes 46 is It is smaller than the first through hole 38, so that after the second drilling, a protective layer 40 made of resin material is formed on the hole wall of each first through hole 38. Since the hardness of the above-mentioned plugging ink after curing is as high as 9H or more, in order to avoid cracks in the ink during drilling, the drilling pad must be made of a higher hardness material, and the urea board for general drilling cannot be used. 4FR4 (FR4 refers to C-Stage with plastic glass, collectively referred to as cloth). It is a phenolic resin board. In addition, the best one-person drilling speed is controlled at 丨 · 4 to 丨 · 6 m / s, and the better speed is controlled at 35 to 45 krpm. It is better that it is 24 to 26 m / S. With this drilling condition and appropriate ink, the plug hole column 44 will not crack or fall off when drilling. After the protective layer 40 is completed on the first through holes 38, the copper plating operation is continued as shown in the sixth figure, and then the through holes are formed on the walls of the second through holes 46 (the protective layer 40). Layer 42 and copper plating layers 47 are also formed on the surfaces of the upper and lower conductive layers 36 so that the upper and lower conductive layers of each through hole are in contact with the upper and lower conductive layers 36 and 36 respectively.

12325651232565

由於將鋁質之金屬基板32直接鍍銅會因鋁、銅產生化學交 互反應而使金屬基板32氧化變黑,因此在金屬基板μ之第 一通孔38與通孔導電層42之間必須先設有該保護層4〇,而 後才能於金屬基板3 2上進行電鍍銅之作業。在形成該等銅 質之通孔導電層42之後’即如第七圖所示,進行線路成型 的製作作業,以便在金屬基板32之鍍銅層47上製作出電路 佈局48。至此,已初步完成承載基板3〇之各主要結構製 作0 其中線路成型係使用一般的印刷電路板製作方式,亦 即使用壓膜機將乾膜貼覆在板面上,再利用底片蓋在乾膜 上透過曝光方式使乾膜進行光聚合作用,而順利地將^ 路移轉;之後再利用顯影製程將未聚合的乾膜溶去,以留 下保護所需線路的乾膜層,再透過蝕刻製程去除不需要的 銅面部份,最後再利用去膜製程,去除板面上所有的乾 膜’以留下所需的線路。 在完成線路製作之後,本發明更可如第八圖所示,接 續再進行表面處理之步驟,其利用電鍍鎳金或化鎳浸金之 ^面處理方法形成一表面處理膜50。進行電鍍鎳金或化鎳 汉金之表面處理之目的除了藉由表面處理膜5〇保護銅面不 氧化之外,最主要的功能係提供打線〔wire bonding〕之 第二銲點連接用。 #最後,如第九圖所示進行蓋孔作業,將複數乾膜52分 別蓋住該等第二通孔46,其中乾膜52係為感光性聚合物, 如此即元成一半導體晶片承載基板3〇之製作。在此步驟Since copper plating of the aluminum metal substrate 32 directly causes the metal substrate 32 to oxidize and black due to the chemical interaction between aluminum and copper, the first through hole 38 of the metal substrate μ and the conductive layer 42 of the through hole must be first The protective layer 40 is provided, and then the copper plating operation can be performed on the metal substrate 32. After the formation of the copper through-hole conductive layers 42 ', as shown in the seventh figure, a circuit forming manufacturing operation is performed so as to produce a circuit layout 48 on the copper plating layer 47 of the metal substrate 32. At this point, the production of the main structures of the carrier substrate 30 has been completed. Among them, the circuit molding system uses a general printed circuit board manufacturing method, that is, a dry film is applied to the surface of the board using a laminator, and the dry film is used to cover the dry surface. Through the exposure method on the film, the dry film is subjected to photopolymerization, and the ^ path is smoothly transferred; then, the unpolymerized dry film is dissolved by the development process to leave a dry film layer for protecting the required circuit, and then transmitted The etching process removes unnecessary copper surface parts, and finally the film removal process is used to remove all the dry films on the board surface to leave the required wiring. After the circuit fabrication is completed, the present invention can further perform a surface treatment step as shown in FIG. 8. The surface treatment film 50 is formed by a surface treatment method of electroplated nickel gold or nickel immersion gold. The purpose of the surface treatment of electroplated nickel gold or nickelized hankin is to protect the copper surface from oxidation by a surface treatment film 50. The most important function is to provide a second solder joint for wire bonding. #Finally, cover the holes as shown in the ninth figure, and cover the second through holes 46 with a plurality of dry films 52, wherein the dry film 52 is a photosensitive polymer, so that a semiconductor wafer carrying substrate 3 is formed. 〇 的 制造。 Production. At this step

1232565 五、發明說明(6) 中’蓋孔之目的在於防止後續LED晶粒封裝時的樹脂透過 第二通孔46流到另一面的銲墊(pad)上而形成絕緣層,以 避免喪失焊接導通的功能。在此,僅需在金屬基板32的單 面蓋孔即可。 上述承載基板3 0取代習知印刷電路板作為半導體晶粒 之基板時,由於金屬的導熱性較陶瓷及塑膠為佳,故可有 效增強半導體晶粒之散熱性。第十圖為本發明之承載基板 使用做為一LED晶粒的載板之結構示意圖,如圖所示,在 該承載基板3 0上依設計需求設有一凹槽6〇,接著將LEI)晶 粒54直接以銀膠5 6植入在金屬材質之承載基板3〇上,而後 銲線且封裝樹脂,完成一LED封裝元件58,即可藉由基板 30自身的鋁金屬進行散熱,進而延長LE])的壽命及增加亮 度。 因此’本發明利用在金屬基板上二次鑽孔之做法,配 合適當之塞孔材料及鑽孔條件之控制,以製作出具導通孔 之雙面連接基板,提供安裝半導體晶粒。故本發明不僅在 製作方法上克服習知於塞孔油墨上鑽孔的困難點及僅能提 供單面連接金屬板之缺失,進而提供一雙面連接型之基 板,同時更可使安裝於其上之半導體晶粒達成有效散熱之 功效。 以上所述係藉由實施例說明本發明之特點,其目的在 ,熟習該技術者能暸解本發明之内容並據以實施,'而非限 疋本發明之專利範圍,故,凡其他未脫離本發明所揭示之 精神所完成之等效修飾或修改,仍應包含在以下所述之申1232565 V. Description of the invention (6) The purpose of the 'cover hole' is to prevent the resin during subsequent LED die packaging from flowing through the second through hole 46 to the pad on the other side to form an insulating layer to avoid loss of soldering. Continuity function. Here, it is only necessary to cover the hole on one side of the metal substrate 32. When the above-mentioned carrier substrate 30 replaces the conventional printed circuit board as the substrate of the semiconductor die, since the thermal conductivity of metal is better than that of ceramic and plastic, it can effectively enhance the heat dissipation of the semiconductor die. The tenth figure is a structural schematic diagram of a carrier substrate using the LED substrate as an LED die according to the present invention. As shown in the figure, a groove 60 is provided on the carrier substrate 30 according to design requirements, and then a LEI) crystal is provided. The granules 54 are directly implanted on the carrier substrate 30 made of metal with silver glue 56, and then the wires are encapsulated and the resin is encapsulated to complete an LED package component 58. The heat can be dissipated by the aluminum metal of the substrate 30, thereby extending LE ]) Life and increase brightness. Therefore, the present invention utilizes the method of secondary drilling on a metal substrate, and combines appropriate plugging materials and control of drilling conditions to produce a double-sided connection substrate with a via hole to provide mounting semiconductor die. Therefore, the present invention not only overcomes the difficulty of drilling holes known in the plugging ink and can only provide a single-sided connection metal plate in the manufacturing method, thereby providing a double-sided connection type substrate, but also can be mounted on it. The semiconductor chip above achieves effective heat dissipation. The above is the description of the characteristics of the present invention through the examples. The purpose is that those skilled in the art can understand the content of the present invention and implement it based on it, rather than limiting the scope of the patent of the present invention. Equivalent modifications or modifications made by the spirit disclosed in the present invention should still be included in the application described below.

1232565 五、發明說明(7) 請專利範圍中。 圖號說明: 1 0發光二極體元件 14 LED晶粒 18錫膏 30承載基板 34上結合膠層 36上導電層 38 導通孔/第一通孔 40保護層 44塞柱 47鍍銅層 50 表面處理膜 54 LED晶粒 58 LED封裝元件 12鋁板 1 6 印刷電路板 20 單面線路 32金屬基板 34’下結合膠層 36’ 下導電層 3 9 定位孔 42通孔導電層 46 第二通孔 48 電路佈局 52乾膜 56銀膠 60凹槽1232565 V. Description of the invention (7) In the scope of patent. Description of drawing number: 10 light emitting diode element 14 LED die 18 solder paste 30 bonding layer 36 on the substrate 34 conductive layer 38 via / first through hole 40 protective layer 44 plug 47 copper plating 50 surface Processing film 54 LED die 58 LED package element 12 aluminum plate 1 6 printed circuit board 20 single-sided circuit 32 metal substrate 34 'lower bonding layer 36' lower conductive layer 3 9 positioning hole 42 through hole conductive layer 46 second through hole 48 Circuit layout 52 dry film 56 silver glue 60 groove

第11頁 1232565 圖式簡單說明 第一圖為習知具散熱結構之發光二極體裝置示意圖。 第二圖至第九圖為本發明於製作半導體晶粒承載基板的各 步驟構造剖視圖。 第十圖為本發明之承載基板使用做為LED晶粒的載板之結 構示意圖。Page 11 1232565 Brief description of the diagram The first diagram is a schematic diagram of a conventional light emitting diode device with a heat dissipation structure. The second to ninth figures are cross-sectional views of the steps of the present invention in the fabrication of a semiconductor die carrier substrate. The tenth figure is a schematic diagram of the structure of the carrier substrate of the present invention which is used as the carrier plate of the LED die.

第12頁Page 12

Claims (1)

1232565 六、申請專利範圍 1· 一種半導體晶粒承載基板,包括: 一金屬基板’其係句把一令 依序覆設有-上貼人在該金屬板之上表面 —下貼合膠層及-下導電層;以及 該= :該導通孔係貫穿該金屬基板,在每-ϊίί ;= 序覆設有一保護層及-通孔導電層, 觸。 下邰係刀別與該上、下導電層相接 2·如申請專利範圍第i項所述之半 中,該金屬板係為銘板。+導艘日日粒承載基板,其 3中如::=!第1項所述之半導體晶粒承載基板,其 中該保濩層係由環氧樹脂系之樹脂所組成。 4中如::專=第1項所述之半導體晶粒承載基板,其 中該上、下導電層係各設有電路佈局。 5.如申請專利範圍第丨項所述之半導體 中,該上、下導電層之材料為銅。 承载基板,其 6中如Πίϊϊ圍第1項所述之半導體晶粒承載基板,其 中’該通孔導電層之材料為銅。 、 7·如申請專利範圍第丨項所述之半導體晶粒之承 其中’該等通孔導電層係以電鍍方式形成。 土 ’ 利範圍第1項所述之半導體晶粒承載基板,其 係作為發先二極體晶粒之承載基板。 丹 9· 一種半導體晶粒承載基板之製造方法,包括 提供-金屬基板,該金屬基板包括一金屬板,在屬1232565 6. Scope of patent application 1. A semiconductor die-bearing substrate, including: a metal substrate 'which is sequentially covered by a repertoire-the upper surface is attached to the upper surface of the metal plate-the lower surface is bonded with an adhesive layer and -The lower conductive layer; and the =: the via hole penetrates the metal substrate, and a protective layer and a through-hole conductive layer are arranged on each of the-=; The lower jaw blade is connected to the upper and lower conductive layers. 2. As described in the first half of item i of the patent application scope, the metal plate is a nameplate. + Guide board for Rilipin carrier, 3 of them are as follows: =! The semiconductor die carrier board described in item 1, wherein the protective layer is composed of epoxy resin. For example in 4: special = the semiconductor die carrier substrate described in item 1, wherein the upper and lower conductive layers are each provided with a circuit layout. 5. In the semiconductor described in item 丨 of the patent application scope, the material of the upper and lower conductive layers is copper. In the carrier substrate, the semiconductor die carrier substrate described in the first item in the first item, wherein the material of the through-hole conductive layer is copper. 7. The bearing of the semiconductor die as described in item 丨 of the scope of the patent application, wherein the conductive layers are formed by electroplating. The semiconductor die carrier substrate described in the first item of the invention is used as a carrier substrate for the development of the first diode die. Dan 9. A method for manufacturing a semiconductor die carrier substrate, including providing a metal substrate, the metal substrate including a metal plate, 1232565 六、申請專利範圍 板之上表面依序覆設有一上 該金屬板之下表面依序覆,:合膠層及一上導電層,且在 層; 又有一下貼合膠層及一下導電 進行第一次鑽孔作業,#料#入b 數第一通孔; 係對該金屬基板鑽孔,以形成複 將該等第一通孔填滿而形成複數塞柱; 第作業,係對該等塞柱鑽孔,以形成複數 —二ί孔該第—通孔之孔㈣較該第—通孔小,使每 -該第-通孔之孔壁上各形成有—保護層;以及 形成複數通孔導電層於該等第二通孔之孔壁上,以使每 一該通孔導電層之上、下部分別與該上、下 接 觸。 10·如申請專利範圍第9項所述之製造方法,其中 板係為板。 11·如申请專利範圍第9項所述之製造方法,其中 等第一通孔所使用之材料係為環氧樹脂系之油墨 12·如申請專利範圍第9項所述之製造方法,其中 第二次鑽孔之步驟中,係使用高硬度之鑽孔墊板。 13·如申請專利範圍第12項所述之製造方法,其中,該鑽 孔墊板為酚醛樹脂材質者。 14·如申請專利範圍第9項所述之製造方法,其中,在進行 第二次鑽孔之步驟中,進刀速為1·4至1·6 m/s,轉速為35 至45 krpm,退刀速為24至26 m/s。 15·如申請專利範圍第9項所述之製造方法,其中,形成該1232565 6. The scope of patent application The upper surface of the board is sequentially covered with an upper surface and the lower surface of the metal plate are sequentially covered: a glue layer and an upper conductive layer, and a layer; a glue layer and a conductive layer Perform the first drilling operation, # 料 # 入 b number of first through holes; drilling the metal substrate to form a plurality of first through holes to form a plurality of plugs; The plugs are drilled to form a plurality of holes, the holes of the first through holes are smaller than the holes of the first through holes, so that a protective layer is formed on each of the walls of the holes. A plurality of through-hole conductive layers are formed on the hole walls of the second through-holes, so that the upper and lower portions of each of the through-hole conductive layers are in contact with the upper and lower portions, respectively. 10. The manufacturing method according to item 9 of the scope of patent application, wherein the board is a board. 11. The manufacturing method described in item 9 of the scope of patent application, wherein the material used for the first through hole is an epoxy resin ink. 12. The manufacturing method described in item 9 of the scope of patent application, wherein In the second drilling step, a high hardness drilling pad is used. 13. The manufacturing method according to item 12 of the scope of patent application, wherein the drilling pad is made of phenolic resin. 14. The manufacturing method according to item 9 of the scope of patent application, wherein in the step of performing the second drilling, the feed speed is 1.4 to 1.6 m / s, and the rotation speed is 35 to 45 krpm. The retracting speed is 24 to 26 m / s. 15. The manufacturing method according to item 9 of the scope of patent application, wherein ^32565 六 申請專利範圍 二m電層之步驟係使用電鍍方'。 其中,該上 .申凊專利範園第9項所述/ 下導電層之材料為納 之製造方法 其中,該通孔 雷如展申請專利範圍第9項所述之製造方法 導電層之材料為鋼。 表&万法 在形成 下導電 在形成 如/請專利範圍第9項所述之製造方法,其中 =通孔導電層之後,更包括一步驟4將= 19 ^由線路成型的作業,以製作出電路佈局。 哕笙、申請專利範圍第9項所述之製造方法,其中 通孔導電層之後,更包括一表面處理之步驟。 •如申請專利範圍第19項所述之製造方法,其中,該表 =處理之步驟所使用之處理方式係選自電鍍鎳金及化鎳浸 金0^ 32565 6 Application scope of the patent The steps of the 2m electric layer use the electroplating method. Among them, the material of the conductive layer described in item 9 of the upper and lower patent fan garden is the manufacturing method of nano, wherein the material of the conductive layer of the manufacturing method described in item 9 of the patent application scope of the through hole is steel. Table & Wanfa is conductive under formation. After forming the manufacturing method as described in item 9 of the patent scope, after = conductive layer of the through hole, it also includes a step 4 which will be = 19 ^ from the circuit forming operation to make Out the circuit layout. Yun Sheng, the manufacturing method described in item 9 of the scope of patent application, wherein the conductive layer of the through hole further includes a surface treatment step. • The manufacturing method as described in item 19 of the scope of patent application, wherein the processing method used in the table = processing step is selected from the group consisting of electroplated nickel gold and nickel immersion gold.
TW092133464A 2003-11-28 2003-11-28 Semiconductor chip-carrying substrate and its manufacturing method TWI232565B (en)

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