TWI232497B - Mask - Google Patents
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- TWI232497B TWI232497B TW92132229A TW92132229A TWI232497B TW I232497 B TWI232497 B TW I232497B TW 92132229 A TW92132229 A TW 92132229A TW 92132229 A TW92132229 A TW 92132229A TW I232497 B TWI232497 B TW I232497B
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Description
1232497 五、發明說明(1) 1明所_屬之技術 问本ΓΓ是ΐ關於一種遮罩,且特別是有關於-種調整 晶圓之參數设定所使用之遮罩。 正 先前技術 半導體工業是近年來發展速度最快之高科技工業之 一,而微影(photolithography)製程在目前半 制 t ’ 士是無可取代的製程之一。在半導體之前段製=, 包括疋義主動7L件之源極以及汲極之離子植 金屬内連線層(Interc_ection iayer)之線路圖案或或疋 均是由微影製程來定義,其通常是經過幾十道/、 之步驟才能完成。此外,在半導體之後段製程中,勺= 塊(bump)製程或是球底金屬層(UBM)之製作,也必% 曝光機台將圖案轉移至光阻上,以定義出凸塊長成之位 或球底金屬層之位置。不論是前段製程或是後段製程, 影製程所使用的曝光機台或相關設備,深深影響整 體製程的製程能力。 整個微影製程大致上分為光阻覆蓋(resist coating)、曝光(exp〇sure)以及顯影(devel〇pment)等三 大步驟,而在進行微影製程時,所需具備的要件除了光 源、光罩(photo mask)、光阻之外,還需要用來顯影的顯 影液(deVel〇per)。其中,光阻覆蓋於晶圓的厚度與光阻 ^身的黏性有關,且光阻是否均勻分佈於晶圓上將影響後 績曝光之品質。一旦光阻的厚度不一致或差異太大時,將 使光罩的圖案在轉移時產生曝光不完全或曝光過量等缺 1 第5頁 ^l]896twf .ptd 1232497 五、發明說明(2) '~~~' 陷。此外,在曝光的步驟中,曝光機台所使用的紫外 ( ltra-V1〇let Light)光源或深紫外光光源,對於 也必須調整適當的縮小比例,才能將光罩上= 與光阻的厚度相吻☆,如此才能在光阻上i; 析度良好的圖.案。 行y解 而展f而,要控制上述之曝光條件並不是一件容易的事, 二制理想的曝光光源的強度以及理想的曝光時間 曝而;J…料,才能得到接近理想狀態的 晶圓J: 疋 的曝光參數設定均使用不同的 t測試用基# ’這樣消耗在測試上所使㈣晶圓數 非吊的高,使得測試的成本居高不下。 晶圓因此、’本發明的目的就是在提供一種遮罩,適用於一 定。,用以暴露出晶圓之部分表s ’並進行不同的參數設 於在ϋ?的目的就是在提供-種半導體製程設備,適用 本。问-Β曰圓上進行不同的參數設定,以減低測試的成 覆蓋發明之上述目的,本發明提出-種遮罩,適於 之遮軍,右ί作為—製程設備在調整製程參數時 中_ Α % μ遮罩,、有一開口 ,暴露出晶圓的部分表面,其 τ稭由改變開口盥晶圓之 77 _ 出晶圓之其他表面。 對位£,以使遮罩之開口暴露1232497 V. Description of the invention (1) 1 The technology of the _ belongs to the question ΓΓ is about a kind of mask, and especially about a kind of mask used to adjust the parameter setting of the wafer. Just prior technology The semiconductor industry is one of the fastest growing high-tech industries in recent years, and the photolithography process is currently one of the irreplaceable processes. Before the semiconductor ==, including the source of the active 7L element and the drain electrode's ion implanted metal interconnect layer (Interc_ection iayer), the circuit pattern or 疋 is defined by the lithography process, which is usually Dozens of steps can be completed. In addition, in the subsequent semiconductor manufacturing process, the scoop = bump process or the production of the ball-bottom metal layer (UBM) must also transfer the pattern to the photoresist to define the bumps. The position of the bit or bottom metal layer. Regardless of the front-end process or the rear-end process, the exposure machine or related equipment used in the film production process deeply affects the process capability of the entire system. The entire lithography process is roughly divided into three major steps, namely resist coating, exposure and development. When performing the lithography process, the necessary elements in addition to the light source, In addition to a photo mask and a photoresist, a developing solution (deVeloper) for development is required. Among them, the thickness of the photoresist covering the wafer is related to the viscosity of the photoresist, and whether the photoresist is evenly distributed on the wafer will affect the quality of the subsequent exposure. Once the thickness of the photoresist is inconsistent or too large, the pattern of the photomask will be incomplete or overexposed when it is transferred. 1 Page 5 ^ l] 896twf .ptd 1232497 V. Description of the invention (2) '~ ~~ 'trap. In addition, in the exposure step, the ultraviolet (ltra-V10let Light) light source or deep ultraviolet light source used by the exposure machine must also adjust the appropriate reduction ratio in order to match the photomask = the thickness of the photoresist Kiss ☆, so as to be able to i on the photoresist; It is not easy to control the above-mentioned exposure conditions by performing y solution. It is difficult to control the intensity of the ideal exposure light source and the ideal exposure time of the second system. J: The exposure parameter settings of 疋 use different test bases. This consumes a lot of ㈣ wafers for testing, which makes the cost of testing high. The wafer therefore, 'the object of the present invention is to provide a mask that is suitable for certain applications. The purpose of exposing a part of the wafer s ′ and setting different parameters is to provide a kind of semiconductor process equipment, which is applicable. Q-B said that different parameter settings are performed on the circle to reduce the above-mentioned purpose of the covered invention of the test. The present invention proposes a kind of mask suitable for covering the army. Right as the process equipment is in the process of adjusting process parameters. Α% μ mask, there is an opening to expose part of the surface of the wafer, and its τ is changed from the opening of the wafer to the other surface of the wafer. Align £ to expose the opening of the mask
1232497 五、發明說明(3)1232497 V. Description of the invention (3)
為達本發明之土述目& ,本發明*出 :備,適用於-晶;,此半導體製程設備具有知 備、-遮罩以及’遮罩旋轉架,《中製程設備可調整製程 參數,以進行多道參數設定。此外,遮罩係覆蓋於晶2之In order to achieve the objective of the present invention &, the present invention * exports: prepared, suitable for-crystal; this semiconductor processing equipment has known equipment, -mask and 'mask revolving frame, "process equipment can be adjusted process parameters To set multiple parameters. In addition, the mask is covering the crystal 2
上,而遮罩設置於製程設備與晶圓之間’且遮罩具有一開 口,其暴露出晶圓之部分表面。另外’遮罩旋轉架用以承 載遮罩,並使遮罩之開口環繞於晶圓之上’其中藉由改變 開口與晶圓之相對位置,以使遮罩之開口暴路出晶圓之其 他表面。 為達本發明之上述目的,本發明提出一種利用晶圓之 部分表面以進行參數設定的方法,適於在一晶圓上進行不 同的參數設定。首先提供/遮罩,此遮罩具有一開口,並 暴路出晶圓之部分表面於開口中。接者’改變遮罩之開口 與晶圓之相對位置,以使開口依序暴露出晶圓之其他表 面〇 本發明因採用可將晶圓劃分為多個區域的遮罩、’而晶 圓上各個區域可針對不^的曝光參數,以進行不同的曝光 設定。因此,在同一晶圓上,即可進行多道曝光設定,以 減少測試所使用的晶3圓3數目,並降低測試成本。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,下文特舉一較佳^施例,並配合所附圖式,作詳 細說明如下: 請參考第1以及2圖,其分別繪示本發明一較佳實施例The mask is disposed between the process equipment and the wafer 'and the mask has an opening that exposes a part of the surface of the wafer. In addition, the "mask rotation rack is used to carry the mask and surround the mask opening on the wafer", where the relative position of the opening and the wafer is changed, so that the mask opening is blown out of the wafer. surface. In order to achieve the above-mentioned object of the present invention, the present invention proposes a method for parameter setting using a part of a surface of a wafer, which is suitable for setting different parameters on a wafer. First, a mask is provided. The mask has an opening, and a part of the surface of the wafer is exposed in the opening. The receiver 'changes the relative position of the opening of the mask and the wafer so that the opening sequentially exposes other surfaces of the wafer. The present invention uses a mask which can divide the wafer into a plurality of regions. Each area can be set for different exposure parameters for different exposure parameters. Therefore, multiple exposure settings can be made on the same wafer to reduce the number of crystals, circles and 3 used in the test, and reduce the test cost. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: Please refer to FIGS. 1 and 2, It respectively illustrates a preferred embodiment of the present invention.
1232497 五、發明說明(4) 之一種利用晶圓之部分表面以進行參數設定的流程示意 圖。首先提供一遮罩110,而遮罩110具有一開口 112,其 中開口 1 1 2例如為一扇形開口 ,其半徑略小於或等於晶圓 1 〇 0之半徑,而開口 11 2的面積例如約佔晶圓1 〇 〇總面積之 1 / 8或1 / 6或其他比例。接著,暴露晶圓1 〇 〇之部分表面丨〇 2 於開口 1 1 2中·,以進行參數設定,之後改變遮罩1 1 〇之開口 1 1 2與晶圓1 〇 〇之相對位置,例如順時鐘旋轉遮罩丨丨〇或逆 時鐘旋轉遮罩11 〇,以使遮罩11 〇的開口丨丨2暴露出晶圓1 0 〇 之其他表面104。其中,遮罩11〇可配置於一遮罩旋轉架 (未繪示)上,以使遮罩110之開口丨12可以360度環繞於晶 圓1 0 0之上,並將晶圓1 〇 〇劃分為多個區域(例如圖中所標 5己之102、104) ’以進行不同的參數設定。此外,遮罩 亦可採用固定式,而晶圓1 〇 〇藉由一晶圓旋轉座(未繪示) 而旋轉’此種方式同樣可暴露晶圓丨〇〇之其他表面於開口 112 中。 明參考第3以及4圖,其分別緣示本發明另一較佳實施 例之一種遮罩的示意圖。遮罩2 1 〇具有一開口 2丨2 ,其中開 口 2^ 2例如為一扇形開口,而遮罩2丨〇的下方還可配置一遮 罩定位片220。此遮罩定位片220大致上區分為多個開口區 域222 (例如6個),當遮罩21〇順時鐘或逆時鐘旋轉時, 其開口212逐-通過每一開口區域m。在第3圖中,當遮 罩210之開口 212位於其中之一開口區域m時,則暴露晶 圓(未繪示)之部分表面,以進行參數設定。在第4圖 中田遮罩2 1 0之開口 2 1 2轉移至另一開口區域2 2 2時,則1232497 V. Description of the invention (4) A schematic diagram of the process of using a part of the surface of a wafer to set parameters. First, a mask 110 is provided, and the mask 110 has an opening 112. The opening 1 12 is, for example, a fan-shaped opening with a radius slightly smaller than or equal to the radius of the wafer 1000, and the area of the opening 11 2 is approximately Wafer 1/8 of the total area of 1/6 or 1/6 or other proportions. Next, a part of the surface of the wafer 1000 is exposed in the opening 1 12 for parameter setting, and then the relative position of the opening 1 12 of the mask 1 1 2 and the wafer 1 100 is changed, for example, Rotate the mask clockwise or counterclockwise to rotate the mask 11 clockwise so that the opening of the mask film 11 exposes the other surface 104 of the wafer 100. The mask 11 can be arranged on a mask rotating frame (not shown), so that the opening 110 of the mask 110 can be 360 degrees around the wafer 1000, and the wafer 1 00 Divided into multiple areas (for example, 102, 104 marked in the figure) to set different parameters. In addition, the mask can also be fixed, and the wafer 1000 can be rotated by a wafer rotation base (not shown). This method can also expose the other surfaces of the wafer in the opening 112. Reference is made to Figures 3 and 4 which are schematic diagrams of a mask according to another preferred embodiment of the present invention, respectively. The mask 2 10 has an opening 2 丨 2, where the opening 2 ^ 2 is, for example, a fan-shaped opening, and a mask positioning sheet 220 can be disposed below the mask 2 丨 0. The mask positioning sheet 220 is roughly divided into a plurality of opening regions 222 (for example, six). When the mask 21 rotates clockwise or counterclockwise, its opening 212 passes through each opening region m one by one. In FIG. 3, when the opening 212 of the mask 210 is located in one of the opening areas m, a part of the surface of the wafer (not shown) is exposed for parameter setting. In Figure 4, when the opening 2 1 2 of Nakada mask 2 1 2 is transferred to another opening area 2 2 2, then
1232497 五、發明說明(5) 暴露晶圓之其他表面,以進行另一參數設定,依此類推。 利用上述之遮罩,可用以調整多種半導體製程設備之 參數設定。舉例而言,在半導體之後段製程中,定義凸塊 長成之位置或球底金屬層之位置,可透過微影製程之曝光 設備來完成,以作為後續電鍍或印刷凸塊之位置。首先, 將光阻(未繪示)塗佈在一晶圓1 〇 〇的表面上,例如利用旋 塗(spin coating)的方式將光阻塗佈在晶圓1〇〇上,以使 光阻的表面平坦化,且光阻的厚度要均勻,以避免後續圖 案轉移時產生曝光不完全或曝光過量等缺陷。接著,將晶 圓100放置於一曝光設備(未綠示)中,而曝光機提供足夠 亮度的光源,例如為紫外光光源或深紫外光光源,並控制 適當的曝光時間,以使光罩上的圖案精確地轉移到光阻 上。在本實施例中,所使用的曝光機例如為投影式 (projection)曝光機,其將光罩上的圖案以適當的比例投 射在光阻上。此外,曝光機所能提供之聚焦深度,必須^ 光阻的厚度相吻合,如此才能在光阻上得到解析度良好 圖案。 β月參考第1圖’在進行曝光參數設定之前,先覆蓋一 遮罩110於晶圓100上,晶圓的尺寸可以是6吋、8吋或12时 等,而遮罩110之開口112,其暴露出光阻之部分區域。由 於遮罩11 0可阻擋曝光光源投射在光阻其他區域上,而僅 允許曝光光源通過開口丨丨2,並投射在由開口丨丨2所定義的 區域102上。接著,請參考第2圖,改變遮罩11〇之開口 與晶圓1 0 0之相對位置,以使遮罩丨丨〇之開口丨丨2暴露出光1232497 V. Description of the invention (5) Exposing the other surface of the wafer to set another parameter, and so on. The above mask can be used to adjust the parameter settings of various semiconductor process equipment. For example, in the later stage of the semiconductor process, the position where the bumps are grown or the position of the metal layer under the ball can be defined by the exposure equipment of the lithography process as the position of subsequent plating or printing bumps. First, a photoresist (not shown) is coated on the surface of a wafer 100, for example, the photoresist is coated on the wafer 100 by a spin coating method to make the photoresist The surface is flat and the thickness of the photoresist is uniform to avoid defects such as incomplete or overexposure during subsequent pattern transfer. Next, the wafer 100 is placed in an exposure device (not shown in green), and the exposure machine provides a light source with sufficient brightness, such as an ultraviolet light source or a deep ultraviolet light source, and controls an appropriate exposure time to place the photomask on The pattern is accurately transferred to the photoresist. In this embodiment, the exposure machine used is, for example, a projection exposure machine, which projects the pattern on the photomask onto the photoresist at an appropriate ratio. In addition, the depth of focus provided by the exposure machine must match the thickness of the photoresist so that a good resolution pattern can be obtained on the photoresist. β month refer to Figure 1 'Before setting the exposure parameters, first cover a mask 110 on the wafer 100, the size of the wafer can be 6 inches, 8 inches, or 12 hours, etc., and the opening 112 of the mask 110, It exposes a part of the photoresist. Since the mask 110 can block the exposure light source from being projected on other areas of the photoresist, only the exposure light source is allowed to pass through the opening 丨 2 and be projected on the area 102 defined by the opening 丨 丨 2. Next, referring to Figure 2, change the relative position of the opening of the mask 11 and the wafer 100 so that the opening of the mask 丨 丨 〇 2 exposes light.
1232497 五、發明說明(6) 阻之其他表面。因此,在同一晶圓1 0 0上,藉由環繞開口 112於晶圓1〇〇之不同區域上,可將晶圓1〇〇劃分成多個區 域102 ’以進行不同的曝光參數設定,而原本需要不同的 晶圓作為測試基材之曝光測試,只需要一片晶圓即可完 成’故消耗在測試上所使用的晶圓數目可大大減少,進而 降低測試成本。 在本實施例中,遮罩110所使用的開口112例如為扇形 開口 ’而扇形開口 1丨2係以晶圓之圓心為中心點旋轉,並 將晶圓100劃分為多個區域1〇2。其中,每一區域1〇2例如 呈葉片狀分佈於晶圓100上,而區域1〇2的側邊彼此區隔不 相連。此外,每一區域丨02之側邊亦可彼此相連接,或僅 有一側邊相連接,而另一側邊不相連。另外,開口丨丨2的 形狀不限定為扇形開口,亦可為圓形開口、矩形開口或梯 =開口,而開口 1 1 2係以晶圓1 〇〇之圓心為中心點旋轉,以 定義出不同的區域102於晶圓1〇〇上。再者,開口112的面 ,不限定如第1、2圖所繪示,亦可依實際曝光測試的多 來增大或縮小開口的面積。 效二,疋適當大小開口之遮軍110之後,接下來即是調 ς = 士參數,例如控制曝光的強度以及曝光時間的長短, ,選疋晶圓100之某一區域102暴露於開口112之中,而不 條件所呈現出來的圖案將成為重要的曝光參數設 ίΐίί。如* ’經過一而再 '再而三的改變曝光參數, ίίΐΐ露這些區域102之一於開0112中,以使晶圓1〇〇 之各個區域1〇2上呈現出不同的曝光效果,藉以得到接近1232497 V. Description of the invention (6) Other surfaces of resistance. Therefore, on the same wafer 100, by surrounding the opening 112 on different regions of the wafer 100, the wafer 100 can be divided into a plurality of regions 102 'for different exposure parameter settings, and The exposure test that originally required different wafers as the test substrate can be completed with only one wafer, so the number of wafers used in the test can be greatly reduced, thereby reducing test costs. In this embodiment, the opening 112 used in the mask 110 is, for example, a fan-shaped opening, and the fan-shaped opening 1 2 is rotated around the center of the wafer as the center point, and the wafer 100 is divided into a plurality of regions 102. Wherein, each region 102 is distributed in a leaf shape on the wafer 100, and the sides of the region 102 are not separated from each other. In addition, the sides of each area 02 may be connected to each other, or only one side may be connected, and the other side may not be connected. In addition, the shape of the opening 丨 2 is not limited to a fan-shaped opening, but may also be a circular opening, a rectangular opening, or a ladder = opening, and the opening 1 12 is rotated around the center of the circle of the wafer 1000 to define Different regions 102 are on the wafer 100. In addition, the surface of the opening 112 is not limited to that shown in Figures 1 and 2, and the area of the opening may be increased or decreased according to the actual exposure test. Effect 2: After covering the army 110 with an appropriate size opening, the next step is to adjust the parameters, such as controlling the intensity of the exposure and the length of the exposure time. Select an area 102 of the wafer 100 to be exposed to the opening 112. The patterns presented in the unconditional conditions will become important exposure parameter settings. For example, * 'after and again' and repeatedly change the exposure parameters, revealing one of these areas 102 in the opening 0112, so that each area 102 of the wafer 100 presents different exposure effects, thereby Get close
1232497 五、發明說明(7) 理想狀態的曝光條件。 在產業利用上’本發明所揭露 前段製程或半導體後段製裎之曝光 遮罩亦可適用於調整晶圓上主動元 子植入多募或深淺,而晶圓上不同 入的數量不同,藉以找出最佳的離 圓上常使用的姓刻技術,亦可_由 同區域來調整姓刻設備之參數,以 (over etch)或姓刻不完全等現象 製程設備例如離子植入設備、乾名虫 等,均可藉由遮罩來進行多道製程 佳的效果。 綜上所述,本發明因採用可將 遮罩’而晶圓上各個區域可針對不 不同的參數設定。因此,在同_曰 食、L 曰曰 參數設定,以減少測試所使用的晶 〇 雖然本發明已以一較佳實施例 以限定本發明,任何熟習此技藝者 神和範圍内,當可作些許之更&與 濩範圍當視後附之申請專利範圍所 之遮罩,適用於半導體 測試製程中。此外,此 件之源極以及汲極的離 區域上所得到的離子植 子植入狀況。另外,晶 此遮罩’針對晶圓上不 測試出是否有過度蝕刻 5因此,相關的半導體 刻設備以及曝光設備 參數的設定,以得到最 晶圓劃分為多個區域的 同的製程參數,以進行 圓上,即可進行多次的 圓數目,並降低測試成 揭露如上,然其並非用 ,在不脫離本發明之精 潤飾,因此本發明之保 界定者為準。1232497 V. Description of the invention (7) Ideal exposure conditions. In terms of industrial use, the exposure mask disclosed in the present invention for the front-end process or the semiconductor back-end system can also be used to adjust the number or depth of active element implants on the wafer, and the number of different implants on the wafer is different. The best surname engraving technology often used on the off-circle is also available. You can also adjust the parameters of the surname engraving equipment from the same area. Process equipment such as (over etch) or incomplete surname engraving. Insects, etc., can use masks to perform multiple processes. In summary, since the present invention adopts a mask that can be used, various regions on the wafer can be set for different parameters. Therefore, the same parameters are set to reduce the number of crystals used in the test. Although the present invention has been described with a preferred embodiment to limit the present invention, anyone skilled in the art can work within the scope and spirit of the art. A little more & and the scope of the mask as the scope of the attached patent application, suitable for semiconductor testing process. In addition, the ion implantation status obtained on the source and drain regions of this case. In addition, the mask 'is not tested for excessive etching on the wafer5. Therefore, the relevant semiconductor engraving equipment and exposure equipment parameters are set to obtain the same process parameters for the most wafer divided into multiple regions. By performing the circle, the number of circles can be performed multiple times, and the test result can be reduced as above. However, it is not useful, and it does not depart from the refined decoration of the present invention. Therefore, the guarantee of the present invention shall prevail.
1232497 圖式簡單說明 第1以及2圖分別繪示本發明一較佳實施例之一種利用 晶圓之部分表面進行參數設定之方法的流程示意圖。 第3以及4圖分別繪示本發明另一較佳實施例之一種遮 罩的示意圖。 【圖式標示說明】 100 晶 102 晶 圓 部 分 表面 104 晶 圓 其 他 表面 110 遮 罩 112 開 口 210 遮 罩 212 開 α 220 遮 罩 定 位 片 222 開 口 區 域1232497 Brief Description of Drawings Figures 1 and 2 respectively show a schematic flow chart of a method for setting parameters using a part of a surface of a wafer according to a preferred embodiment of the present invention. 3 and 4 are schematic diagrams of a mask according to another preferred embodiment of the present invention, respectively. [Illustration of Graphical Symbols] 100 crystal 102 crystal circle part surface 104 crystal circle other surface 110 mask 112 opening 210 mask 212 opening α 220 mask positioning piece 222 opening area
^ -;lr-J896twf .ptd 第12頁^-; lr-J896twf .ptd p. 12
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CN118380352A (en) * | 2024-06-24 | 2024-07-23 | 上海陛通半导体能源科技股份有限公司 | Wafer processing method capable of adjusting wafer warpage in different areas |
CN118380352B (en) * | 2024-06-24 | 2024-10-22 | 上海陛通半导体能源科技股份有限公司 | Wafer processing method capable of adjusting wafer warpage in different areas |
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CN118380352A (en) * | 2024-06-24 | 2024-07-23 | 上海陛通半导体能源科技股份有限公司 | Wafer processing method capable of adjusting wafer warpage in different areas |
CN118380352B (en) * | 2024-06-24 | 2024-10-22 | 上海陛通半导体能源科技股份有限公司 | Wafer processing method capable of adjusting wafer warpage in different areas |
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