TWI230976B - Method for forming a semiconductor device and structure thereof and method for forming a semiconductor device having a reduced pitch - Google Patents

Abstract

A method for forming a semiconductor device having a reduced pitch is provided. The method includes providing a substrate, forming a material layer over the substrate, forming a photoresist layer over the material layer, exposing a top surface of the photoresist layer to radiation, and forming a silylated layer over the photoresist layer. The method further includes removing a portion of the silylated layer to expose the photoresist layer, removing the photoresist layer, removing portions of the material layer using the silylated layer as a mask, and removing another portion of the silylated layer.

Description

1230976 __Case No. 92131481_Amended in January of the year __ 5. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a semiconductor element, and more particularly to a method for manufacturing a semiconductor element. Method for reducing the cell pitch (C e 1 1 P itch). [Previous Technology] The fabrication of semiconductor devices is a complex process. Generally speaking, this process includes several lithographic processes. In a typical lithography process, a photoresist layer is deposited on the film layer to be patterned and exposed to a light source. Among them, the radiation light source is, for example, ultraviolet radiation, and the radiation light source penetrates a mask for projection, and in order to form a pattern in the photoresist, a pattern is first defined on the mask. In addition, since the photomask only passes through the selected area of the film layer to be patterned, only the photoresist layer located on the selected area will be exposed. Then, the photoresist layer is developed to form a patterned photoresist layer on the film layer to be patterned which is located below. The lower part of the film layer will be exposed through the photoresist layer and removed by etching > to define, for example, the gate conductor of the transistor element to be formed later. Therefore, the pattern in the photoresist can be reproduced in the underlying film layer. Of course, the size of the semiconductor element is reduced as much as possible, and for the semiconductor element, it can have more important advantages. However, when a general lithography process is used to fabricate a semiconductor device, the lithography process may limit the size and density of the semiconductor device. For example, the minimum resolution of a particular lithography process (R es ο 1 uti ο n C apabi 1 ity) will determine the minimum pitch (P itch), that is, for a film layer to be patterned , This spacing

9905 twf1.ptc Page 6 1230976 Case No. 92131481 _η Name Amendment 5. The features of invention description (2) will be limited by the semiconductor components known by lithography. Therefore, when the body's electrical conductivity is not easily reduced. Due to the small lithographic process, the semiconductor element distance! The term is printed here (P r i n t). In this way, for lithography, the lithography process will result in the smallest width that can be achieved. When using the lithography process to define, for example, the width of conductive gates or the distance between each other, it is in the same structure, such as the distance between pieces. It is not effective for smaller-sized conductor elements (E ff is in. In addition, the lithographic separation and width are not required [invention requirements of the present invention, this Si 1 yati ο η) Pitch) 〇 Example of its cell pitch On one point, the other two neighbors are easy to shrink, and it is faster to say 'Nanmi's known technique icient 1 y, which requires more middle-term and lesser encounters.' Knowing the restrictions that define this kind of electricity, so in the half degree system, if the half is a crystal element, the conductor can be turned, yes) reducing the distance to develop a neighboring conductor element with a shadow process will not be easy to shrink Conductive gate. "The distance between two junctions of the same type and adjacent ones. Among them, the conductive gates of the same type. Because the density of semiconductor elements is not easy to increase to meet the demand for components. In addition, for materials that are semi-formed to a lower level Cost. The demand for how reliable (re 1 iab 1 y) and the distance between conductor elements is the manufacturing method of the semiconductor device, the structure of the same type is limited by the distance between them. A simple and feasible method to meet The above-mentioned photoresist is used to reduce the cell pitch of semiconductor elements (C e 1 1 current lithography process, which makes half of the formed element elements. Because of the semiconductor element cells

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9905twf1.ptc Page 7 1230976 __Case No. 92131481_Year_Month_Revision _ V. Description of the invention (3) The pitch can be reduced, so the component density can be increased, which in turn reduces the size and speed of the integrated circuit. In one embodiment, and this is only one example, a method for forming a semiconductor device with a reduced pitch is proposed. The method includes first providing a substrate. Then, a material layer is formed on the substrate. Next, a photoresist layer is formed on the material layer. After that, the photoresist layer is exposed to radiation. Then, a siliconized layer is formed on the surface of the photoresist layer. In addition, the method further includes removing a portion of the silicide layer to expose the photoresist layer. Then, the photoresist layer is removed. Then, using the silicide layer as a mask, a part of the material layer is removed. After that, the other parts of the Shixi Formation were removed. In another embodiment, the method includes first providing a substrate, and a first film layer is formed on the substrate. Then, a second film ® layer is formed on the first film layer. Then, a full exposure is performed on the second film layer within a preset time (Flood Exposure). After that, Shi Xihua forms a second film layer to form a Shi Xihua layer on the second film layer. In addition, the method further includes removing the first portion of the petrified layer to expose the second film layer. Then, the second film layer is removed. Then, using the silicide layer as a mask, the exposed portion of the first film layer is removed. After that, the second part of the silicide layer is removed. In still another embodiment, a method for forming a semiconductor device having a reduced pitch (P i t c h) includes forming a material layer before a substrate. Then, a patterned photoresist layer is formed on the material layer. Next, the patterned photoresist layer is exposed to ultraviolet radiation to change at least one property of the patterned photoresist layer, so that part of the patterned photoresist layer becomes depolymerized (D e ρ ο 1 ymerized) layer. Afterwards, this depolymerization is silicified in the gas or liquid phase

9905twf1.ptc Page 8 1230976 Case No. 92131481 Amendment V. Description of the Invention (4) Combined layers, so that the figure also includes the less than the brightest of the plasma etching using the chemical layer. The specified one is easy to elaborate. [The actual and similar are two lithographs of the gas mask. In this scope, it will not explain the easy-to-see points. Implementation. Please make it clear. One, come, copy, process, and each other and 〇 are the advantages of the invention. The example of the invention is published below: Formula] Just to describe the etched parts for the sake of convenience, to remove the materials in order to remove The permissible and specific contradictions formed. It is familiar with the description and novelty. It does not include a photoresistance or exposure layer on top of the other ones. It has the best description and the best layer between the special features of the invention or the invention. The distance between the light exposure intervals on the chemical plot is ^ -X *, and the 14 is the sign of the Ming. Point and point. Other implementations form a shredded layer. In addition, a mechanical planarization process and a patterned photoresist layer. RANDOM LAYER. Next, take the silicon part. After that, move most of the structures, and inch. The combination of these features, or each of these features, can be used for the purpose of understanding the background knowledge. Of course, the views, advantages and perspectives of the present invention will be described below. After removing the method, using the chemical layer as a silicide layer, the distance is included in the description of the features of the present invention to better describe any special features of the present invention, including the purpose, characteristics, and advantages. It can be more clearly illustrated, and in accordance with the accompanying drawings, it will be described in detail. In addition, the embodiments with clear drawings are used to illustrate the present invention. In this embodiment, the same or similar reference numerals refer to the same or similar phases. The illustrations are schematic diagrams, not actual dimensions. In terms related to location direction, such as

9905twf1.ptc Page 9 1230976 Case No. 92131481 Amendment V. Description of the Invention (5) Top, bottom, left, right, up, down, above, below, bottom, front and back, etc., are only used for The illustrated structure is described instead of limiting the present invention. Although specific illustrations are used in this embodiment to describe it in detail, it is not intended to limit the present invention. The following detailed description, although it is a preferred embodiment, can be modified and retouched without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be regarded as the scope of the attached patent application. Defined shall prevail. In addition, the method and structure of forming a semiconductor device with a reduced pitch (P i t c h) mentioned below cannot cover a complete process of manufacturing a semiconductor device with a reduced pitch. The present invention can be combined with many conventional integrated circuit manufacturing techniques, but only a limited number of process steps are mentioned here, which are needed to explain the present invention. The present invention is applicable to general semiconductor devices and processes. However, for the purpose of explaining the present invention, the following description is only related to a method for reducing the cell pitch by using silicidation technology in semiconductor devices. Please refer to the drawings in particular. Figure 1 is a cross-sectional view showing the substrate 10. A material layer 12 is formed on the substrate 10, and a photoresist layer 14 is formed on the material layer 12. The photoresist layer 14 is, for example, a patterned photoresist layer. Therefore, the material layer 12 and the photoresist layer 14 are sequentially formed on the substrate 10. In a preferred embodiment, the substrate 10 is made of a single crystal silicon material. In addition, the substrate 10 may be made of, for example, gallium nitride (G a N), gallium arsenide (G a A s), or a material generally suitable for semiconductors. The preferred material for the material layer 12 can be selected according to the requirements of a specific semiconductor application or structure. For example, material layers 1 2 can

9905twfl.ptc Page 10 1230976 — _Case No. 92131481_ Rev. J: _ 5. Description of the invention (6) includes semiconductor compounds, which can be selected from any group IIIA and VA elements (melon-v semiconductor compounds), Mixed III-V compounds, IIIA or IIIB elements and Group A elements (III-VI semiconductor compounds), mixed III-VI compounds, and combinations thereof. It is, for example, silicon (Si), silicon dioxide (Si02), doped silicon dioxide, silicon nitride (SiN), polycrystalline silicon (Si2), aluminum (A1), titanium (Si T i), titanium nitride (T i N), button (T a), tantalum nitride (T a N), copper, aluminum copper (A 1 Cu) alloy, polymer resin, dielectric anti-reflective coating Fabric (Dielectric Anti-Reflective Coating, DARC), bottom f5 Anti-Reflective Coating (BARC), Development Bottom Anti-Reflective Coating (DeBARC), and these different materials Any combination. However, in a preferred embodiment, the material layer 12 may include other semi-conductive materials, metallic or non-metallic materials, as long as these materials can be used to form semiconductor components, structures and / or integrated circuits. In one embodiment, the method of 'forming the material layer 12 on the substrate 10 can be achieved by a thermal process', which is, for example, thermal oxidation. In one embodiment, during the thermal oxidation process f 'substrate 10 is exposed to thermal radiation, and the surrounding environment is filled with oxygen' to form a material layer 12 on the substrate 10. In addition, the material layer 12 can be deposited on a substrate by a conventional thin film deposition method, which is, for example, chemical vapor deposition or chemical vapor deposition (CVD). The material layer 1 f may have a uniform thickness in the range of approximately 40 angstroms (A) to 8000 angstroms, and preferably has a uniform thickness of approximately 12,000 angstroms. In the present embodiment, the material layer 12 includes a thickness of about 8 0/1 2 0 0 oxidized stone / polycrystalline stone, and the patterned photoresist layer 14 has about 4 2 0 0 angstrom.

9905twf1.ptc Page 11 1230976 Correction

__ Case No. 92131481_ ± 5. Thickness of the description of the invention (7). The photoresist layer 14 is formed on the material layer 12 using, for example, a photolithography process. The resist layer 14 may be a negative photoresist, a positive photoresist, a negative electron beam resist, or an electro-optic beam resist. In this embodiment, the photoresist layer 14 includes a positive photoresist. It is also called f-radiation-positive photoresistance of Radiation-Softening photoresist, which is exposed to radiation and depolymerized, where f is radiated by radiation such as U V. With the use of a positive photoresist, the areas exposed to radiation ^ will be dissolved in the developer solution, while the uncovered areas covered with photoresist = will not be affected. In order to form the photoresist layer 14, a photoresist layer is spun on the material layer 12 (Spi n), and after the photoresist baking process, the substrate 10 is placed in a generally known stepper ( Stepper) or scanning device (Scanner), and the reticle in the stepper or scanning device will be aligned and exposed to ultraviolet (UV) radiation. The size of the reticle can be a size that can cover only a small portion of the substrate 10. In this case, the stepper or the scanning device divides the substrate 10 into multiple quadrants for scanning, so that These areas are sequentially exposed until the entire substrate 10 or a portion of the substrate to be exposed has been exposed to UV radiation. Then, after Post Exposured Bake, the substrate 10 is placed in a developing solution to dissolve the depolymerized portion of the photoresist layer that has been exposed to UV radiation to produce a patterned light.阻 层 14。 Resistance layer 14. In this embodiment, the patterned photoresist layer 14 is characterized by a height H1 of approximately 4200 angstroms and a width CD1 of approximately 1600 angstroms. Moreover, in this embodiment, the minimum pitch dimension d 1 of the patterned photoresist layer 14 is as small as the size allowed by the lithography process. For example, the minimum pitch dimension d 1 may be

9905twf1.ptc Page 12 1230976 __Case No. 92131481_ Year Month Amendment_ V. Description of the invention (8) 3 0 0 0 Angstrom. In other embodiments, the width, height, and / or distance d 1 may be other sizes. FIG. 2 is a cross-sectional view following FIG. 1 and showing exposure on the patterned photoresist layer 14. This exposure process can change or change at least one property of the patterned photoresist layer 14. For example, a portion of the patterned photoresist layer 14 can be changed from a polymer state of cross-linking (Cr s s-Lin k d) to a polymer state of less cross-linking. Therefore, in accordance with the viewpoint of the present invention, a comprehensive exposure treatment is performed to change at least the degree of crosslinking of the photoresist layer 14. Such a fragmenting agent will more easily diffuse into this polymer which reduces the degree of crosslinking. In Figure 2, in order to change the degree of crosslinking of the polymer, a comprehensive exposure to ultraviolet radiation is performed to depolymerize the patterned photoresist layer. This process of comprehensively exposing the patterned photoresist layer 14 is achieved, for example, by deep ultraviolet radiation (less than 2 480 angstroms), and then a heat treatment step is performed. This exposure process is performed at a predetermined time and dose with a substantially vertical patterned photoresist layer 14, so the top surface of the patterned photoresist layer 14 can be fully exposed, for example. In one embodiment, the dose of ultraviolet radiation is, for example, about 30 to 200 in J / cm2, and the exposure energy is about 50 mJ / cm2. The heat treatment step may be performed at a temperature of about 90 to 150 degrees Celsius and a time of about 1 to 5 minutes. In this implementation, the process includes silicidating the patterned photoresist layer 14, and the silicidation includes a diffusion process, such as diffusing the silicide into the outside of the Lu patterned photoresist layer 14. In the case where silicon is used as an example, the silicide agent includes, for example, fluorinated silylamine (difluorinylsilyldifluorinylamine).

9905twf1.ptc Page 13 1230976 _Case No. 92131481_Year_Month_Fifth, the description of the invention (9) (dimethysi lydimethyamine), dimethylaminopentamethyldisi lane, dimethylaminopentamethyldisi lane Dimethylsilydiethylamine or bis (dimethylamin〇) diinethylsilane

Wait). This silicidation reagent is implemented in the form of a vapor or liquid containing silicon, and the silicidation reagent can provide a large #etch resistance (Etch Resistance) by providing a lithography to the patterned photoresist layer structure. . In a preferred embodiment, for the silicide in the gas phase, the silicidation process can be performed at a temperature of about 90 to 150 degrees Celsius and a time of about 1 to 20 minutes. For the silicidation reagent in the liquid phase, the silicidation process can be performed at a temperature of about 15 to 30 degrees Celsius and a time of about 1 to 20 minutes. The silicidation diffusion process can preferably be adjusted so that the vertical depth of the silicided layer 18 (for example, the thickness of the silicided layer is t) is smaller than the thickness of the patterned photoresist layer 14 and, as shown in the figure, The vertical depth is smaller than the height H2, and the remaining and unsilicided patterned photoresist layer 16 has a height of H3. ^ μ As a result of the silicidation process, the surface portion of the unsilicided patterned photoresist layer 16 will be silicified, and an unriched patterned photoresist layer 16 will form an enriched stone evening light. The resist layer or the petrified layer 18 forms a structure as shown in FIG. 3. According to the viewpoint of the present invention, the silicide layer 18 can reduce the cell pitch obtained by using a general lithography process. The silicide layer 18 has a thickness t of about 600 angstroms. In this implementation, the thickness of the patterned photoresist layer 14 remaining under the silicide layer 18 is approximately 3800 angstroms, and the non-silicided patterned photoresist layer 16 is formed with a width CD3 of approximately 90. 0 Angstroms. In accordance with this

9905twf1.ptc Page 14 1230976 __Case No. 92131481__Year Month Day Amendment __ V. Description of the Invention (10) In the embodiment of the invention, the height H1 is greater than the height H3, and the width CD1 is greater than the width CD3. In this embodiment, the obtained structure covered with the silicide layer 18 has a height H2 of about 4 400 angstroms and a width CD2 of about 2100 angstroms. In addition, in the embodiment according to the present invention, the height Η 2 is greater than the height Η 1, and the width CD2 is greater than the width CD1, the width CD2 is approximately equal to the width CD3 plus a thickness t, and the height Η2 is approximately equal to the height Η3 plus Upper thickness t. Next, the top silicidation layer 18 is removed (for example, planarized) to expose the surface of the unsilicided patterned photoresist layer 16. This removal method is, for example, using a cash back engraving technique or a conventional polishing Technology to form a structure as shown in FIG. 4, wherein a conventional polishing technology is, for example, a chemical mechanical polishing (CMP) process. For example, ′ is a chemical mechanical polishing process to remove the top of the silicided layer 8 and expose the top surface of the unsilicided patterned photoresist layer 16. The polishing time of the silicide layer 18 ^ is based on the ability to completely remove the top of the silicide layer 丨 8, that is, the chemical mechanical polishing process will end before the unpatterned patterned light beam and the substantial part is removed. Point in time. In a preferred embodiment, additional polishing of the lithography layer 18 and part of the non-silicided patterned photoresist layer 6 is possible. However, in the process of the CMP process, in order to obtain better control of the material to be removed, it is possible to control the depth of the planarization so that the material is only removed to the top surface. Other methods for moving the top of the coating layer 18 may include dry etching and wet etching = other etching processes. Those who are familiar with this art know a variety of techniques: techniques can also be implemented here. Technology Then, as shown in Figure 5, remove the unsiliconized photoresist layer

9905twf1.ptc Page 15 1230976 _Case No. 92131481_Year Month Amendment_ V. Description of the Invention (11) 1 6 The removal method is, for example, plasma etching. Since plasma etching is performed by anisotropic etching, the edges of the retained structure can be sharpened. Therefore, plasma etching is a better removal method. the way. In this embodiment, plasma etching is performed using an etching gas containing oxygen. The composition of the plasma source gas can be changed, for example, it can contain oxygen (02). The steps of this process include, for example, the first step using a C2F6 plasma, the main etching step using a 02-S02 plasma, and an over-etching step. Such etching will cause the unsiliconized photoresist layer 16 to degrade, and the stone evening layer 18 will become a polymer rich in silicon dioxide, which further increases its power to electricity. Resistivity of slurry etching. When an oxygen plasma is used in the etching process described here, silicidation has a unique advantage for the etch resistance of the patterned photoresist layer 14. For example, a photoresist layer that has been silicified according to the method described herein according to the present invention, under an oxygen plasma, exhibits an etch rate less than about 50% of the unsilicided patterned photoresist layer 14. Therefore, the silicide layer 18 can be formed in a thinner film layer and produce a sharper image (Image) than conventionally known. The etching time of the unsilicided patterned photoresist layer 16 is based on the ability to completely remove the unsilicided patterned photoresist layer 16, that is, the removal technology will end at the essence of the material layer 12 At the point in time before it was removed. In this embodiment, the removal of the non-silicided patterned photoresist layer 16 can expose a part of the material layer 12. _ Then, use the silicide layer 18 as the etching mask layer, and etch by using an etchant that has a greater selectivity to the material layer than the processing (eg, silicide) layer 18

9905twf1.ptc Page 16 1230976 Case No. 92131481 Amendment V. Description of the Invention (12) The material layer 12 is etched to form the structure as shown in FIG. In particular, in this embodiment, the conditions for the engraving of the material layer 12 are that the etching rate of the material layer 12 is greater than the etching rate of the silicide layer 18, and when the upper surface of the substrate 10 is exposed, This etching will stop. This process is similar to that when the material layer 12 is etched, the substrate 10 is used as an etching stop layer. After that, the oxidized layer 1 8 ′ is removed. The removal method is, for example, using a wet I insect engraving technique, which sequentially uses, for example, dilute hydrofluoric acid (2 0 0: 1), a mixed solution of sulfuric acid and hydrogen peroxide, and ammonia water. / Hydrogen peroxide / deionized water to form a plurality of structures having a pitch as shown in FIG. 7. In particular, in this embodiment, the etching on the silicide layer 18 is performed under the condition that the etch rate of the silicide layer 18 is greater than the #etch rate of the substrate 10 (and, in one embodiment, also Will be greater than the etch rate of the material layer 12), and when the upper surface of the material layer 12 is exposed (and, in one embodiment, the upper surface of the substrate 10 that was not exposed before the etching is exposed) ), This etching will stop. This process is similar to that when the silicide layer 18 is etched, the material layer 12 and the substrate 10 are used as #etch stop layers. After removing the layer, a transistor element can be formed. The method for forming the transistor element is, for example, implanting a dopant into the source / drain junction of the substrate 10, and the junction is located between these structures 20. In a preferred embodiment, the distance between two adjacent structures 20 is relatively fixed. The distance reference d 2 represents the pitch of the structure 20 and is therefore also the pitch of the transistor elements formed subsequently according to the method of the present invention. It can be seen from the comparison between the pitch d 1 in FIG. 1 and the pitch d 2 in FIG. 7 that the pitch d 2 is half of the pitch d 1. In addition, it can also be seen from Figures 1 and 7 that the width of the section (Lateral) of each structure is substantially small.

9905twf1.ptc Page 17 1230976 _Case No. 92131481_ Years and months Amendment_ V. Description of the invention (13) The minimum section width allowed in the lithography process. Therefore, the present invention can provide a method for forming a transistor element, and the distance between the elements obtained by this method is smaller than the distance between the conventional transistor elements obtained by using the current lithographic conditions. Since the pitch of the components can be reduced, the density of the components can be increased. In the above description, those skilled in the art can easily infer that a semiconductor device can be formed by using the method of the present invention, and in particular, a method of reducing the cell pitch in a semiconductor device by using a silicidation technology. Although in the above description, the present invention has been described with reference to several embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. In addition, those skilled in the art can integrate, delete, replace, and retouch the ideas disclosed here to make them more visible. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

9905twf1.ptc Page 18 1230976 Case No. 92131481_ ± Month Modified Drawing Brief Description Figure 1 is a cross-sectional view of a substrate according to a preferred embodiment of the present invention, in which a material layer has been sequentially formed on the substrate and Patterned photoresist layer. Fig. 2 is a continuation of Fig. 1 and shows the steps of performing a comprehensive exposure on a patterned photoresist. Fig. 3 is a continuation of Fig. 2 and shows the steps of silicidation and depolymerization to form a silicidation layer on the patterned photoresist layer. Fig. 4 is a continuation of Fig. 3 and shows the steps of removing the top of the silicide layer by using an etch-back technique or a conventional polishing technique to expose the top surface of the unsilicided patterned photoresist layer. A known polishing technique is, for example, chemical mechanical planarization.

Fig. 5 is a continuation of Fig. 4 and shows a step of removing a non-silicided patterned photoresist layer using a dry stripping technique. Fig. 6 is a continuation of Fig. 5 and shows the steps of using a silicide layer as an etching mask and etching the material layer. Fig. 7 is a continuation of Fig. 6 and shows the steps of removing the silicide layer by using a wet stripping technique to form a plurality of structures having a reduced pitch.

Description of type mark] 10 substrate 12 material layer 14 photoresist layer 16 unsilicided patterned photoresist layer 18 silicide layer 20 structure

9905twf1.ptc Page 19 1230976 Case No. 92131481 Λ_η Correction Brief description of drawings HI, Η2, Η3: Height CD1, CD2, CD3: Width d 1, d 2 ·· Pitch t: Thickness

9905twf1.ptc Page 20

Claims (1)

1230976 Case No. 92131481 _η said Amendment VI. Patent Application Scope 1. A semiconductor device is proposed to make Radiat in the photoresist layer by 2. method, which should be 3. method, its thing, the first group 4. Method, its silicon, and the group for one base, the material, the light ion), the light removal department, except the guarantee as stated in the processing · protection method as claimed in the IV group 〇 as claimed in the nitrided into A substrate; a top layer formed on the bottom to form a resist layer; a method for forming the resist layer; the method includes: a material layer; a photoresist layer; exposure to a treatment radiation (Treatment photoresist layer protection) The layer is a patented radiation cladding including a patented material layer including a patented material layer and a patented material layer of silicon and a plurality of groups. A protective layer is formed; the protective layer is to expose the lower portion of the layer; and a cover is to remove the portion The material layer of the semiconductor device described in the first item includes a light beam, a siliconized layer (Silylated Layer), and an additional step in addition to the protective layer. The formation method of the semiconductor device described in the second item of the range is selected from the formation method of the semiconductor device described in the second item of the range composed of a group π compound, a group m compound, a group V compound, and a group VI compound. Selected from the group consisting of silicon, silicon dioxide, doped silicon dioxide, aluminum, copper, titanium, titanium nitride, tantalum and nitride 9905 twfl.ptc Page 21 1230976 MM 92131481 Revision 6. Application for patent scope 5. The method for forming a semiconductor element as described in item 2 of the patent application scope ', wherein the material layer is made of a polymer resin. 6. The method for forming a semiconductor device according to item 2 of the scope of the patent application, wherein the material layer is selected from the group consisting of a Dielectric Anti-Reflective Coating and a Bottom Anti -Reflective Coating) and a developable bottom anti-reflective coating (DeBARC). 7. The method for forming a semiconductor device according to item 2 of the scope of patent application, wherein the photoresist layer is a patterned photoresist layer. _ 8 · The method for forming a semiconductor device according to item 2 of the scope of patent application, wherein the photoresist layer is a positive photoresist. 9. The method for forming a semiconductor device according to item 2 of the scope of the patent application, wherein the photoresist layer is a positron beam (E_Beam) resist. 1 〇 The method for forming a semiconductor device according to item 2 of the scope of patent application, wherein exposing the photoresist layer to radiation includes performing a comprehensive exposure process (Flood Exposure Process) to change at least the photoresist layer一 性。 One nature. 1 1 · The method for forming a semiconductor device according to item 2 of the scope of the patent application, wherein a petrified layer formed on the photoresist layer includes silanizing a surface of the photoresist layer. 1 2 · The method for forming a semiconductor device as described in item 11 of the scope of patent application ', wherein one surface of the photoresist layer of Shi Xihua includes performing a silicidation process in a gas phase. 9905twfl.ptc Page 22 1230976 _ Case No. 92131481_Year_Amendment_ VI. Patent Application Range 1 3. The method for forming a semiconductor device as described in Item 12 of the patent application range, wherein the photoresist layer is silicided. A surface includes a silicidation process in a liquid phase. 1 4. A structure of a semiconductor element, which is formed by using the method of forming a semiconductor element described in item 1 of the patent scope. 1 5. A structure of a semiconductor device, which is formed using the method of forming a semiconductor device described in item 2 of the patent scope. 16. A structure of a semiconductor device, which is formed by using the method of forming a semiconductor device described in item 9 of the patent scope. 17. A method for forming a semiconductor device, comprising: providing a substrate on which a first film layer is formed; forming a second film layer on the first film layer; and performing a second film layer on the second film layer A comprehensive exposure process to form a protective layer on the second film layer; removing a first portion of the protective layer to expose the second film layer; removing the second film layer; and Using the protective layer as a # engraved mask, remove an exposed portion of one of the first film layers. [18] The method for forming a semiconductor device according to item 17 of the scope of patent application, wherein: the protective layer includes a silicide layer; and the method includes an additional step of removing a second part of the protective layer. 19. Formation of a semiconductor device as described in item 17 of the scope of patent application 9905twf1.pt c Page 23 1230976 Case No. 92131481 Date_Amendment of Liu Qingyan Shen Di Bao's advancement of the surface and top row and the film with, two, the middle layer shoots the radiation to the outside of the light • ， 紫 ， The stratification in the shot case exposed the radioactive material maps all outside the package is included. Department of light and straight middle layer exposure perpendicular to the film • film-like upper radiating E in the first and second surface outside the I's the first full solid purple special, this layer of this method and the film formed in Fang Erlu element body Item No. 7 of the Guideline IX. Fan Li specially invited the Chinese side to form a combination of the compound of the family, the compound of the family, the compound of the family, the compound of the family, and the family of the family. The family is selected by V Bai. The fourth layer of the family of laminated films is the fourth layer of the first group of materials and the first layer of light blocking is the second layer, the first group of the group's qualitative nature-as little as the second layer of the film. In addition to the change, the change was changed to the process of layer-forming film, and the second part of the surface was exposed. The part is guided by the shape of the element. 8 11 French package •, the middle membrane and the phase two are liquid; the process or the production phase is exposed, the gas storm is flat, the balance is equal, the Department of Mechanical Engineering, the Department of Chemical Engineering, the first silicon, or the In the process of layering and layering, silicon etching, the second one, the first one, the second layer, the second layer, the second layer, the first layer, the second layer, the first layer, and the first, the first layer. In addition to cutting the previous part of the division, the division of the removed part is 0, and the formed part is described in the guide of the element 8 1-X. Fan Li specially requested to apply as the middle phase liquid-or the phase gas 1 on Marching the layer: the second in the film, the method 9905twf1.ptc Page 24 1230976 Case No. 92131481 Amendment of the first exposure of the violent part KΓ v. 1 The first layered silicon encirclement should be removed from Li Qin and transferred to the sixth or process; Dry-wet, one-use, or encapsulation, layer-etching, film-etching, two, dry, one, remove, use, move, include, divide, β, stand-up, solid-layer film, • In the description of the part of the body before the removal process, the part of the body guide is described in item 8 li. Fan Li specifically invites δ- as in the French removal process, there are many more layers of this structure.士士 口 ά * '' There should be a forming system βτ Ji mouth between the Λ system distance and the process filming micro-level 丨 the 1st layer of the dagger fan M 亥 专 Special I. ", A division", please CK inch 卩 shift rule α mid-range 纟 in the meantime! 4, the division before Xu Fafang is divided into β-Likou quality practice item 7 IX item 8 I do the law of the element The base of the item described in the half of the base is equal to 0. It is tied to the knot βτ it. The perimeter Fanli special profit system constructs the structure of the structure. ::: the shape method, the method f, the ancient tr, and the squares are formed into the t of the configuration ^ MH ^ "element body 7L body fMf guide, guide-guide-half, half of half 14" / j 有 有 具 There are il-shaped parts of the element guide, including the method of blocking light in this layer; layering material maps-forming the upper layer of the bottom material-forming the top layer The case change plan should be changed to 'one in the middle of the shot; the radiation is low and the purple is reduced and the degree is exposed in parallel, k) the intensive in-layer fiL blocks the two light and the ro The photoresist layer of this photoresist i 9905twf1.ptc Page 25 1230976 _ Case No. 92131481_Year_Day__ Sixth, the scope of the patent application is to diffuse the silyl amine (Si lyl amine) into the patterned photoresist layer to form a surface covering the surface A siliconized layer to silicify the patterned photoresist layer in a gas phase or a liquid phase; use a etch-back process or a chemical mechanical planarization process to remove a first portion of the silicided layer to The patterned photoresist layer is exposed; a plasma gas is used to remove the patterned photoresist layer; the silicide layer is used as an etching mask to remove an exposed portion of the material layer; and A second portion of the silicide layer is removed to form a plurality of structures having a pitch, and the pitch is smaller than a gap size allowed by a lithography process. 2 8. The method for forming a semi-conducting element with a reduced pitch as described in item 27 of the scope of the patent application, wherein: the plasma gas includes ozone; and removing the second part of the silicide layer ends the material Before a substantial part of the layer was removed. 9905twf1.ptc Page 26