1229839 一轉換器’用以接收該第三顯示資料以及該些第二伽 侷電壓’依該第三顯示資料選擇對應的該些第二伽僞電壓 之一並輸出爲該影像驅動訊號。 5·如申請專利範圍第4項所述之顯示器的驅動電路，其 中該轉換器係爲數位至類比轉換器(D/A converter)。 6. 如申請專利範圍第4項所述之顯示器的驅動電路，其 中該弟—緩衝器係爲線緩衝器(line buffer)。 7. 如申請專利範圍第4項所述之顯示器的驅動電路，其 中該弟二顯TpC貪料係並列形式（in parallel)之資料。 8. —種顯示器的驅動電路，用以依一水平同步訊號之時 序將一第一顯示資料轉換爲一影像驅動訊號以提供該顯示 器顯像，該顯示器的驅動電路包括： 一伽侷（Gamma)電壓產生器，用以提供多數個第一伽僞 電壓； 一控制裝置，用以檢測該第一顯示資料，並依該水平 同步訊號之時序輸出與該第一顯示資料對應之多數個伽侷 電壓控制訊號，而該控制裝置包括： 一解多工電路(demultiplexer)，用以接收該第一顯 示資料並對該第一顯示資料中之一灰階解碼，對於解碼得 到之該灰階則對應輸出一觸發訊號；以及 一伽侷電壓控制電路，用以接收該觸發訊號以及 該水平同步訊號，栓鎖該觸發訊號並依該水平同步訊號之 時序輸出爲該些伽侷電壓控制訊號之一，其中該伽侷電壓 控制電路之個數，與該些伽僞電壓控制訊號之總個數相 同，而該伽侷電壓控制電路包括： 1229839 泛年^月曰修(更〉正本 98-3-19 一或閘，具有一第一或閘輸入端、一第二或 閘輸入端以及一或閘輸出端，該第一或閘輸入端用以接收 該觸發訊號； 一第一栓鎖器，具有一第一輸入端、一第一 輸出端以及一第一重置端，該第一栓鎖器之該第一輸入端 耦接至該或閘輸出端，該第一栓鎖器之該第一輸出端耦接 至該第二或閘輸入端，該第一栓鎖器之該第一重置端耦接 至該水平同步訊號；以及 一第二栓鎖器，具有一第二輸入端、一第二 輸出端以及一時脈觸發端，該第二栓鎖器之該第二輸入端 耦接至該第一栓鎖器之該第一輸出端，該第二栓鎖器之該 時脈觸發端耦接至該水平同步訊號，該第二栓鎖器之該第 二輸出端耦接輸出爲該些伽侷電壓控制訊號之一； 多數個第一緩衝器(buffer)，任一該些第一緩衝器用以 接收該些第一伽侷電壓之一以及該些伽僞電壓控制訊號之 一，任一該些第一緩衝器依該伽侷電壓控制訊號決定是否 輸出一第二伽侷電壓；以及 一驅動器，用以接收該些第二伽侷電壓、該水平同步 訊號及該第一顯示資料，以該水平同步訊號之時序依該第 一顯示資料選擇對應的該些第二伽侷電壓之一並輸出爲該 影像驅動訊號。 9. 如申請專利範圍第8項所述之顯示器的驅動電路，其 中該伽僞電壓產生器更接收多數個伽僞調整電壓，並依該 些伽侷調整電壓產生對應之該些第一伽僞電壓。 10. 如申請專利範圍第8項所述之顯示器的驅動電路， 25 1229839 f 98-3-19 *---j 年月日修(I正替雜g - --一... — i 其中該第一顯不資料係串列形式（in serial)之資料。 11.如申請專利範圍第8項所述之顯示器的驅動電路， 其中該驅動器包括： 一位移暫存器（shift register)，用以接收該第一顯示資 料並產生一第二顯示資料； 一第二緩衝器，用以接收該第二顯示資料及該水平同 步訊號，依該水平同步訊號之時序栓鎖該第二顯示資料並 輸出一第三顯示資料；以及 一轉換器，用以接收該第三顯示資料以及該些第二伽 侷電壓，依該第三顯示資料選擇對應的該些第二伽侷電壓 之一並輸出爲該影像驅動訊號。 I2·如申請專利範圍第11項所述之顯示器的驅動電 路，其中該轉換器係爲數位至類比轉換器(D/A converter)。 13. 如申請專利範圍第U項所述之顯示器的驅動電 路’其中該桌一緩衝器係爲線緩衝器(line buffer)。 14. 如申請專利範圍第U項所述之顯示器的驅動電 路’其中該第三顯示資料係並列形式(in parallel)之資料。 15. —種平面顯示器，包括： 一顯示面板，具有多數個像素； 一時序控制器’用以輸出一掃瞄訊號與一水平同步訊 號； 一組閘極驅動電路，具有多數個閘極驅動器，用以接 收該掃瞄訊號； 一組源極驅動電路，具有多數個源極驅動器，其中每 一該些源極驅動器用以依一水平同步訊號之時序將一第一 26 1229839 顯示資料轉換爲一影像驅動訊號以提供該顯示器顯像，該 些源極驅動器包括： 一伽僞(Gamma)電壓產生器，用以提供多數個第 一伽僞電壓；以及 一控制裝置，用以檢測該第一顯示資料，並依該 水平同步訊號之時序輸出與該第一顯示資料對應之多數個 伽僞電壓控制訊號，而該控制裝置包括： 一灰階訊號比較電路，內具一灰階資料，用 以接收該第一顯示資料並與該灰階資料比較，若比較結果 爲相同則輸出一觸發訊號；以及 一伽僞電壓控制電路，用以接收該觸發訊號 以及該水平同步訊號，栓鎖該觸發訊號並依該水平同步訊 號之時序輸出爲該些伽侷電壓控制訊號之一，其中該灰階 訊號比較電路與該伽侷電壓控制電路各別之個數，與該些 伽侷電壓控制訊號之總個數相同，而該伽侷電壓控制電路 包括： 一或閘，具有一第一或閘輸入端、一第 二或閘輸入端以及一或閘輸出端，該第一或閘輸入端用以 接收該觸發訊號； 一第一栓鎖器，具有一第一輸入端、一 第一輸出端以及一第一重置端，該第一栓鎖器之該第一輸 入端耦接至該或閘輸出端，該第一栓鎖器之該第一輸出端 耦接至該第二或閘輸入端，該第一栓鎖器之該第一重置端 親fer至該水平问步訊號；以及 一弟一栓鎖器，具有一第二輸入端、一 1229839 第二輸出端以及一時脈觸發端，該第二栓鎖器之該第二輸 入端耦接至該第一栓鎖器之該第一輸出端，該第二栓鎖器 之該時脈觸發端耦接至該水平同步訊號，該第二栓鎖器之 該第二輸出端耦接輸出爲該些伽侷電壓控制訊號之一； 多數個第一緩衝器(buffer)，任一該些第一緩衝器用以 接收該些第一伽侷電壓之一以及該些伽僞電壓控制訊號之 一任一該些第一緩衝器依該伽僞電壓控制訊號決定是否 輸出一第二伽僞電壓；以及 一驅動器，用以接收該些第二伽侷電壓、該水平同步 訊號及該第一顯示資料，以該水平同步訊號之時序依該第 一顯示資料選擇對應的該些第二伽侷電壓之一並輸出爲該 影像驅動訊號。 16. 如申請專利範圍第15項所述之平面顯示器，其中該 伽侷電壓產生器更接收多數個伽僞調整電壓，並依該些伽 侷調整電壓產生對應之該些第一伽僞電壓。 17. 如申請專利範圍第15項所述之平面顯示器，其中該 第一顯示資料係串列形式(in serial)之資料。 18. 如申請專利範圍第15項所述之平面顯示器，其中該 驅動器包括： —位移暫存器（shift register)，用以接收該第一顯示資 料並產生一第二顯示資料； 一第二緩衝器，用以接收該第二顯示資料及該水平同 步訊號，依該水平同步訊號之時序栓鎖該第二顯示資料並 輸出一第三顯示資料；以及 一轉換器，用以接收該第三顯示資料以及該些第二伽 28 1229839 侷電壓’依該第三顯示資料選擇對應的該些第二伽僞電壓 之一並輸出爲該影像驅動訊號。 19.如申請專利範圍第18項所述之平面顯示器，其中該 轉換窃係爲數位至類比轉換器(D/A converter)。 2〇.如申請專利範圍第18項所述之平面顯示器，其中該 弟一緩衝益係爲線緩衝器(line buffer)。 21.如申請專利範圍第18項所述之平面顯示器，其中該 第三顯示資料係並列形式(in parallel)之資料。 22·如申請專利範圍第15項所述之平面顯示器，其中該 平面顯不器包括一液晶顯示器（liquid crystal display, LCD)。 23. 如申請專利範圍第15項所述之平面顯示器，其中該 平面顯不器包括一非晶砂液晶顯示器（amorphous silicon LCD)。 24. 如申請專利範圍第15項所述之平面顯示器，其中該 平面顯示器包括一低溫多晶砂液晶顯示器（low temperature poiy-silicon LCD)。 25·如申請專利範圍第15項所述之平面顯示器，其中該 平面顯示器包括一有機發光二極體顯示器（organic light emitting diode display)。 26. 如申請專利範圍第15項所述之平面顯示器，其中該 平面顯示器包括一反射式液晶顯示器。 27. 如申請專利範圍第26項所述之平面顯示器，其中該 反射式液晶顯示器包括一 liquid crystal on silicon (LCOS)。 29 1229839 28種平面顯示器，包括： 一顯示面板，具有多數個像素； 一時序控制器，用以輸出一掃瞄訊號與一水平同步訊 號； 一組閘極驅動電路，具有多數個閘極驅動器，用以接 收該掃瞄訊號， 一組源極驅動電路，具有多數個源極驅動器，其中每 /該些源極驅動器用以依一水平同步訊號之時序將一第一 顔禾資料轉換爲一影像驅動訊號以提供該顯示器顯像，該 些源極驅動器包括： 一伽侷（Gamma)電壓產生器，用以提供多數個第 —伽僞電壓；以及 一控制裝置’用以檢測該第一顯示資料，並依該 水平同步訊號之時序輸出與該第一顯示資料對應之多數個 伽僞電壓控制訊號，而該控制裝置包括： —解多工電路(demultiplexer)，用以接收該第 一顯示資料並對該第一顯示資料中之一灰階解碼，對於解 碼得到之該灰階則對應輸出一觸發訊號；以及 一伽僞電壓控制電路’用以接收該觸發訊號 以及該水平同步訊號，栓鎖該觸發訊號並依該水平同步訊 號之時序輸出爲該些伽侷電壓控制訊號之一，其中該伽僞 電壓控制電路之個數，與該些伽僞電壓控制訊號之總個數 相同’而該伽侷電壓控制電路包括： 一或閘’具有一第一或閘輸入端、 一第二或閘輸入端以及一或閘輸出端，該第一或閘輸入端 30 1229839 用以接收該觸發訊號； 一第一栓鎖器，具有一第一輸入 端、一第一輸出端以及一第一重置端，該第一栓鎖器之該 第一輸入端耦接至該或閘輸出端，該第一栓鎖器之該第一 輸出端耦接至該第二或閘輸入端，該第一栓鎖器之該第一 重置端耦接至該水平同步訊號；以及 一第二栓鎖器，具有一第二輸入 端、一第二輸出端以及一時脈觸發端，該第二栓鎖器之該 第二輸入端耦接至該第一栓鎖器之該第一輸出端，該第二 栓鎖器之該時脈觸發端耦接至該水平同步訊號’該第二栓 鎖器之該第二輸出端耦接輸出爲該些伽侷電壓控制訊號之 多數個第一緩衝器(buffer) ’任一該些第一緩衝器用以 接收該些第一伽僞電壓之一以及該些伽侷電壓控制訊號之 一，任一該些第一緩衝器依該伽僞電壓控制訊號決定是否 輸出一第二伽僞電壓；以及 一驅動器，用以接收該些第二伽僞電壓、該水平同步 訊號及該第一顯示資料，以該水平同步訊號之時序依該第 一顯示資料選擇對應的該些第二伽傳電壓之一並輸出爲該 影像驅動訊號。 29.如申請專利範圍第28項所述之平面顯币器’其中該 伽僞電壓產生器更接收多數個伽僞調整電壓’並依該些伽 僞調整電壓產生對應之該些第一伽彳馬電Μ ° 3〇·如申請專利範圍第28項所述之平面顯不器，其中該 第一顯示資料係串列形式(in serial)之資料。 1229839 31·如申請專利範圍第28項所述之平面顯示器，宜中該 驅動器包括： ^ —位移暫存器(shift register)’用以接收該第一顯示資 料並產生一第二顯示資料； 一第二緩衝器，用以接收該第二顯示資料及該水平同 步訊號’依該水平同步訊號之時序栓鎖該第二顯示資料並 輸出一第三顯示資料；以及 一轉換器，用以接收該第三顯示資料以及該些第二伽 僞電壓，依該第三顯示資料選擇對應的該些第二伽侷電壓 之一並輸出爲該影像驅動訊號。 32. 如申請專利範圍第31項所述之平面顯示器，其中該 轉換器係爲數位至類比轉換器（D/A converter)。 33. 如申請專利範圍第31項所述之平面顯示器，其中該 第二緩衝器係爲線緩衝器（line buffer)。 34. 如申請專利範圍第31項所述之平面顯示器，其中該 第三顯示資料係並列形式（in parallel)之資料。 35. 如申請專利範圍第28項所述之平面顯示器，其中該 平面顯不器包括一液晶顯不器（liquid crystal display， LCD)。 36. 如申請專利範圍第28項所述之平面顯示器，其中該 平面顯τκ器包括一非晶砂液晶顯不器（amorphous silicon LCD)。 37. 如申請專利範圍第28項所述之平面顯示器，其中該 平面顯不器包括一低溫多晶砂液晶顯示器（low temperature poly-silicon LCD)。 32 1229839 38. 如申請專利範圍第28項所述之平面顯示器，其中該 平面顯示器包括一有機發光二極體顯示器（organic light emitting diode display)。 39. 如申請專利範圍第28項所述之平面顯示器，其中該 平面顯示器包括一反射式液晶顯示器。 40. 如申請專利範圍第39項所述之平面顯示器，其中該 反射式液晶顯示器包括一liquid crystal on silicon (LC0S)。 331229839 A converter is used to receive the third display data and the second gamma voltages according to the third display data, and select one of the corresponding second gamma pseudo voltages and output it as the image driving signal. 5. The driving circuit for a display as described in item 4 of the patent application, wherein the converter is a digital-to-analog converter (D / A converter). 6. The driving circuit for a display as described in item 4 of the scope of the patent application, wherein the brother-buffer is a line buffer. 7. The driver circuit for a display as described in item 4 of the scope of patent application, wherein the second display TpC is in parallel. 8. A display drive circuit for converting a first display data into an image drive signal to provide the display of the display according to the timing of a horizontal synchronization signal, the drive circuit of the display includes: a gamma A voltage generator for providing a plurality of first gamma pseudo voltages; a control device for detecting the first display data and outputting a plurality of gamma bureau voltages corresponding to the first display data in accordance with the timing of the horizontal synchronization signal A control signal, and the control device includes: a demultiplexer circuit for receiving the first display data and decoding one of the first display data, and outputting the gray level corresponding to the decoded output A trigger signal; and a gamma voltage control circuit for receiving the trigger signal and the horizontal synchronization signal, latching the trigger signal, and outputting one of the gamma voltage control signals according to the timing of the horizontal synchronization signal, wherein The number of the gamma voltage control circuits is the same as the total number of these gamma pseudo voltage control signals. The gamma voltage control circuit includes: 1229839 Pan year ^ month Yue Xiu (more> original 98-3-19 one OR gate, has a first OR gate input terminal, a second OR gate input terminal and an OR gate output terminal, the first OR gate input terminal For receiving the trigger signal; a first latch having a first input terminal, a first output terminal and a first reset terminal, the first input terminal of the first latch is coupled to the first latch terminal; OR output terminal, the first output terminal of the first latch is coupled to the second OR input terminal, and the first reset terminal of the first latch is coupled to the horizontal synchronization signal; and A second latch has a second input end, a second output end, and a clock triggering end. The second input end of the second latch is coupled to the first of the first latch. The output terminal, the clock trigger terminal of the second latch is coupled to the horizontal synchronization signal, and the second output terminal of the second latch is coupled to output one of the gamma voltage control signals; most First buffers, any one of the first buffers is used to receive one of the first Gamma voltages and the Gamma pseudo-electricity One of the control signals, any one of the first buffers determines whether to output a second gamma voltage according to the gamma voltage control signal; and a driver for receiving the second gamma voltages, the horizontal synchronization signal, and For the first display data, one of the second gamma voltages corresponding to the first display data is selected according to the timing of the horizontal synchronization signal and output as the image driving signal. 9. As described in item 8 of the scope of patent application The display driving circuit of the display, wherein the gamma pseudo voltage generator further receives a plurality of gamma adjustment voltages, and generates the first gamma pseudo voltages corresponding to the gamma adjustment voltages. The driving circuit of the display is 25 1229839 f 98-3-19 * --- year, month and day repair (I is replacing the miscellaneous g----...-i, where the first display data is in series Form (in serial) information. 11. The driving circuit for a display according to item 8 of the scope of patent application, wherein the driver comprises: a shift register for receiving the first display data and generating a second display data; a first Two buffers for receiving the second display data and the horizontal synchronization signal, latching the second display data and outputting a third display data according to the timing of the horizontal synchronization signal; and a converter for receiving the first display data The three display data and the second gamma voltages are selected according to the third display data and output as the image driving signal. I2. The driving circuit for a display device according to item 11 of the scope of patent application, wherein the converter is a digital-to-analog converter (D / A converter). 13. The driving circuit of a display device as described in item U of the scope of patent application, wherein the table-buffer is a line buffer. 14. The driving circuit of a display as described in item U of the scope of the patent application, wherein the third display data is data in a parallel form. 15. A flat display including: a display panel with a plurality of pixels; a timing controller 'for outputting a scanning signal and a horizontal synchronization signal; a set of gate driving circuits having a plurality of gate drivers for To receive the scanning signal; a set of source driving circuits having a plurality of source drivers, each of which is for converting a first 26 1229839 display data into an image at the timing of a horizontal synchronization signal A driving signal is provided to provide the display of the display. The source drivers include: a Gamma voltage generator for providing a plurality of first Gamma voltages; and a control device for detecting the first display data. And outputting a plurality of gamma voltage control signals corresponding to the first display data according to the timing of the horizontal synchronization signal, and the control device includes: a gray-scale signal comparison circuit having a gray-scale data therein for receiving the The first display data is compared with the grayscale data, and if the comparison result is the same, a trigger signal is output; and a gamma pseudo voltage control circuit, To receive the trigger signal and the horizontal synchronization signal, latch the trigger signal and output one of the gamma voltage control signals according to the timing of the horizontal synchronization signal, wherein the grayscale signal comparison circuit and the gamma voltage control circuit The respective numbers are the same as the total number of the gamma voltage control signals, and the gamma voltage control circuit includes: an OR gate having a first OR gate input terminal, a second OR gate input terminal, and An OR gate output terminal, the first OR gate input terminal is used to receive the trigger signal; a first latch, having a first input terminal, a first output terminal and a first reset terminal, the first The first input terminal of the latch is coupled to the OR gate output. The first output terminal of the first latch is coupled to the second OR gate input. The first input of the first latch is A reset terminal profers to the horizontal interrogation signal; and a latch and a latch having a second input end, a 1229839 second output end, and a clock trigger end, the second latch of the second latch The input terminal is coupled to the first output of the first latch. , The clock trigger terminal of the second latch is coupled to the horizontal synchronization signal, and the second output terminal of the second latch is coupled to output one of the gamma voltage control signals; most of the first A buffer, any one of the first buffers for receiving one of the first gamma voltages and one of the gamma pseudo voltage control signals, and any one of the first buffers controlling signals according to the gamma pseudo voltage Determining whether to output a second gamma pseudo voltage; and a driver for receiving the second gamma voltages, the horizontal synchronization signal and the first display data, and selecting the timing of the horizontal synchronization signal according to the first display data The corresponding one of the second gamma voltages is output as the image driving signal. 16. The flat-panel display as described in item 15 of the scope of patent application, wherein the gamma voltage generator further receives a plurality of gamma pseudo-adjusted voltages, and generates the first gamma pseudo voltages corresponding to the gamma adjusted voltages. 17. The flat display according to item 15 of the scope of patent application, wherein the first display data is data in serial form. 18. The flat display according to item 15 of the scope of patent application, wherein the driver comprises:-a shift register for receiving the first display data and generating a second display data; a second buffer A device for receiving the second display data and the horizontal synchronization signal, latching the second display data and outputting a third display data according to the timing of the horizontal synchronization signal; and a converter for receiving the third display The data and the second gamma 28 1229839 station voltages' select one of the second gamma pseudo voltages corresponding to the third display data and output it as the image driving signal. 19. The flat panel display of claim 18, wherein the conversion is a digital-to-analog converter (D / A converter). 20. The flat panel display according to item 18 of the scope of patent application, wherein the first buffer is a line buffer. 21. The flat display according to item 18 of the scope of patent application, wherein the third display data is data in a parallel form. 22. The flat-panel display according to item 15 of the scope of patent application, wherein the flat-panel display includes a liquid crystal display (LCD). 23. The flat-panel display according to item 15 of the patent application, wherein the flat-panel display comprises an amorphous silicon LCD. 24. The flat-panel display according to item 15 of the scope of patent application, wherein the flat-panel display includes a low temperature poiy-silicon LCD. 25. The flat display according to item 15 of the patent application scope, wherein the flat display includes an organic light emitting diode display. 26. The flat-panel display according to item 15 of the patent application scope, wherein the flat-panel display comprises a reflective liquid crystal display. 27. The flat-panel display as described in claim 26, wherein the reflective liquid crystal display includes a liquid crystal on silicon (LCOS). 29 1229839 28 kinds of flat displays, including: a display panel with a plurality of pixels; a timing controller for outputting a scanning signal and a horizontal synchronization signal; a set of gate driving circuits having a plurality of gate drivers for In order to receive the scanning signal, a set of source driver circuits has a plurality of source drivers, wherein each / these source drivers are used to convert a first image data into an image driver according to the timing of a horizontal synchronization signal The signals provide the display of the display. The source drivers include: a Gamma voltage generator for providing a plurality of pseudo-gamma voltages; and a control device 'for detecting the first display data, And outputting a plurality of gamma voltage control signals corresponding to the first display data according to the timing of the horizontal synchronization signal, and the control device includes: a demultiplexer circuit for receiving the first display data and A gray level decoding in the first display data, and a trigger signal is output corresponding to the gray level obtained by the decoding; and a gamma pseudo voltage control The channel is used to receive the trigger signal and the horizontal synchronization signal, latch the trigger signal, and output one of the gamma voltage control signals according to the timing of the horizontal synchronization signal, among which the number of gamma pseudo voltage control circuits, The number of the gamma voltage control signals is the same as the total number of gamma voltage control signals. The gamma voltage control circuit includes: an OR gate having a first OR gate input terminal, a second OR gate input terminal, and an OR gate output terminal. The first OR gate input terminal 30 1229839 is used to receive the trigger signal. A first latch has a first input terminal, a first output terminal, and a first reset terminal. The first input terminal is coupled to the OR gate output terminal, the first output terminal of the first latch is coupled to the second OR gate input terminal, and the first reset terminal of the first latch Coupled to the horizontal synchronization signal; and a second latch having a second input terminal, a second output terminal and a clock trigger terminal, the second input terminal of the second latch is coupled to the horizontal latch signal; The first output end of the first latch, and the second latch The clock trigger terminal is coupled to the horizontal synchronization signal, and the second output terminal of the second latch is coupled to output a plurality of first buffers of the gamma voltage control signals. The first buffers are used to receive one of the first gamma pseudo voltages and one of the gamma local voltage control signals. Any one of the first buffers determines whether to output a second gamma according to the gamma pseudo voltage control signals. A pseudo voltage; and a driver for receiving the second gamma pseudo voltages, the horizontal synchronization signal, and the first display data, and selecting the corresponding second gammas according to the timing of the horizontal synchronization signal according to the first display data One of the voltages is transmitted and output as the image driving signal. 29. The flat coin display device described in item 28 of the scope of patent application, wherein the gamma pseudo voltage generator further receives a plurality of gamma pseudo adjustment voltages and generates the corresponding first gammas according to the gamma pseudo adjustment voltages. Ma Dian M ° 30. The flat display as described in item 28 of the scope of patent application, wherein the first display data is data in serial form. 1229839 31. The flat display as described in item 28 of the scope of patent application, preferably the driver includes: ^ —shift register 'for receiving the first display data and generating a second display data; a A second buffer for receiving the second display data and the horizontal synchronization signal 'latching the second display data and outputting a third display data according to the timing of the horizontal synchronization signal; and a converter for receiving the second display data The third display data and the second gamma pseudo voltages are selected according to the third display data and corresponding to one of the second gamma voltages and output as the image driving signal. 32. The flat-panel display according to item 31 of the patent application scope, wherein the converter is a digital-to-analog converter (D / A converter). 33. The flat display as described in item 31 of the application, wherein the second buffer is a line buffer. 34. The flat display as described in item 31 of the scope of patent application, wherein the third display data is data in a parallel form. 35. The flat panel display as described in item 28 of the patent application, wherein the flat panel display includes a liquid crystal display (LCD). 36. The flat-panel display according to item 28 of the patent application, wherein the flat-display τκ device comprises an amorphous silicon liquid crystal display (amorphous silicon LCD). 37. The flat-panel display according to item 28 of the patent application, wherein the flat-panel display comprises a low temperature poly-silicon LCD. 32 1229839 38. The flat panel display as described in item 28 of the scope of patent application, wherein the flat panel display includes an organic light emitting diode display. 39. The flat panel display as described in claim 28, wherein the flat panel display includes a reflective liquid crystal display. 40. The flat-panel display as described in claim 39, wherein the reflective liquid crystal display includes a liquid crystal on silicon (LC0S). 33