JP2011221327A - Pixel circuit, electro-optical device and drive method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of times of writing data into the same pixel circuit in one frame period by digital drive.SOLUTION: A pixel circuit 400A includes a holding capacitor 410 which holds a data signal Xj; a switching element SW1 by which, when a scanning signal Yi becomes active, the data signal Xj is taken in the holding capacitor 410; a comparator 420 by which a lamp signal S having a horizontal scanning period cycle is compared with the data signal Xj held in the holding capacitor 410; and a selection circuit 440 by which, based on an output signal of the comparator 420, the pulse width modulated signal is generated to be supplied to an liquid crystal element 450.

Description

  The present invention relates to a pixel circuit, an electro-optical device, and a driving method thereof.

In a conventional liquid crystal device (see Patent Document 1) and a light emitting device using an organic EL element, one frame is divided into a plurality of subfields, and a sub-unit that controls binary lighting / extinction of each pixel in subfield units. Field drive is known.
In the sub-field driving, a signal designating lighting / extinguishing is written to the pixel in each sub-field, and lighting / extinguishing is controlled accordingly.

No. 00/070594

  However, in a conventional liquid crystal device using subfield driving, it is necessary to write data to the same pixel circuit a plurality of times within one frame period in order to apply a pulse train corresponding to the gradation to be displayed on the liquid crystal. Therefore, it was necessary to increase the data transfer speed as compared with analog driving. For this reason, there has been a problem that it is difficult to achieve a high frame required for a large screen, a high gradation, a stereoscopic display, and the like.

  Therefore, an object of the present invention is to significantly reduce the number of times data is written to the same pixel circuit within one frame period while being digitally driven.

  In order to solve the above problems, the pixel circuit of the present invention is supplied with a reference signal whose level changes in a predetermined cycle and a data signal having a pulse width corresponding to a gradation to be displayed in a predetermined writing period. A pixel circuit that converts a pulse width of the data signal into a potential using the reference signal and holds a display potential corresponding to a gradation to be displayed; and the display potential and the reference signal And a generation unit that generates a pulse width modulated drive signal based on the comparison result of the comparison unit. In this pixel circuit, an electro-optical element whose optical characteristics change according to electric energy may be provided, and a drive signal having a pulse width corresponding to the gradation to be displayed may be supplied to the electro-optical element. Further, the drive signal may be a pulse width modulation signal having a predetermined period. In this case, the predetermined period is arbitrary, and may be, for example, a period that is a natural number times the horizontal scanning period.

  According to the present invention, the conversion holding unit demodulates the pulse width modulated data signal and holds the potential. Once the data signal is taken into the pixel circuit, the comparison unit compares the display potential with a reference signal having a predetermined period, so that it is possible to generate a pulse width modulated drive signal having a predetermined period. That is, once the data signal is converted into the display potential and written once, the drive signal is generated by repeatedly comparing with the reference signal until writing again. Therefore, the number of times of writing a data signal to the pixel circuit in one frame can be greatly reduced while being digitally driven. Furthermore, pseudo contours and the like due to luminance changes in a frame due to a gradation code, which is a problem in digital driving using subfields, can be dispersed in a predetermined cycle, so that the image quality can be improved. The electro-optical element is a liquid crystal element that changes its transmittance as an optical characteristic according to the applied voltage when electric energy is applied as an applied voltage, and the luminance according to the current when the electric energy is applied as current. An organic EL element that emits light is included.

  Here, the conversion holding unit includes a capacitor that holds the display potential, and a sampling unit that supplies the reference signal to the holding capacitor only during a pulse width period of the data signal in the writing period. preferable. The sample and hold can be performed by the capacity and the sampling unit.

  More specifically, the reference signal is supplied via a signal line, and the sampling unit is provided between the signal line and the first node, and is turned on only for a period of the pulse width of the data signal. A selection transistor, and a first switching element provided between the first node and the second node and turned on only during the writing period, wherein one terminal of the capacitor is the second node The storage capacitor is preferably connected to the other terminal and supplied with a fixed potential to the other terminal.

  Alternatively, the reference signal is supplied via a signal line, and the sampling unit is provided between the signal line and the first node, and is a selection transistor that is turned on only during a period of a pulse width of the data signal; A first switching element provided between the first node and the second node and turned on only during the writing period; and provided between the signal line and the second node; A second switching element that is turned on only during a period other than the period, and the comparator includes an inverter having an input terminal connected to a third node and an output terminal connected to a fourth node; and the third node And a fourth switching node, and a third switching element that is turned on only during the writing period, and wherein the capacitor is a cup provided between the second node and the third node. Rin It may be a capacity. In this case, the configuration can be simplified because the comparison unit can be configured by an inverter.

In the pixel circuit described above, the generation unit does not reflect the comparison result of the comparison unit in the drive signal in the mask period including the writing period, and after the mask period ends, the comparison result of the comparison unit According to the above, it is preferable to generate the drive signal. In this case, the waveform disturbance can be masked.
Further, the comparison unit outputs a comparison signal indicating a comparison result to a fourth node, the generation unit includes a mask unit and a selection unit, and the mask unit is in an off state during the mask period, In a period other than the mask period, and is turned on in the mask period, with the fifth switching element having one terminal connected to the fourth node and the other terminal connected to the fifth node; A sixth switching element that is in an off state in a period other than the mask period, one terminal is connected to the fifth node, and the other terminal is supplied with a first potential, and the selection unit includes: It is preferable that either one of the first level and the second level is selected based on the output signal of the mask unit and is output as the drive signal. In this case, masking can be performed by two switching elements.

  In the pixel circuit described above, it is preferable that the reference signal has a ramp waveform or a waveform with a gamma characteristic. In the case of a ramp waveform, the gradation to be displayed and the pulse width can be made proportional. On the other hand, by using a waveform having gamma characteristics, gamma correction and pulse width modulation can be executed simultaneously.

  According to the electro-optical device of the invention, the plurality of data lines, the plurality of scanning lines, the plurality of signal lines, and the plurality of pixel circuits provided corresponding to the intersections of the scanning lines and the data lines, A scanning line driving circuit for supplying a scanning signal for sequentially selecting the scanning lines for each horizontal scanning period to the plurality of scanning lines, and a pulse width corresponding to the gradation to be displayed on the plurality of data lines. A data line driving circuit that supplies a data signal; and a reference signal generating unit that generates a reference signal whose level changes with a horizontal scanning period as one cycle and supplies the reference signal to the plurality of signal lines in common. Each of the pixel circuits converts a pulse width of the data signal into a potential using the reference signal, holds a display potential corresponding to a gradation to be displayed, the display potential and the reference signal The comparison part to compare with the previous Based on the comparison result of the comparing unit, characterized in that it comprises a generator for generating a pulse width modulated drive signal of the horizontal scanning period cycle.

  According to the present invention, the conversion holding unit demodulates the data signal subjected to the Halus width modulation and holds the potential. Once the data signal is taken into the pixel circuit, the comparison unit compares the display potential with a reference signal having a predetermined period, so that a pulse width-modulated drive signal having a horizontal scanning period can be generated. That is, once the data signal is converted into the display potential and written once, the drive signal is generated by repeatedly comparing with the reference signal until writing again. Therefore, the number of times of writing a data signal to the pixel circuit in one frame can be greatly reduced while being digitally driven. Furthermore, pseudo contours and the like due to luminance changes in a frame due to a gradation code, which is a problem in digital driving using subfields, can be dispersed in a predetermined cycle, so that the image quality can be improved.

  A plurality of data lines, a plurality of scanning lines, a plurality of signal lines, a plurality of pixel circuits provided corresponding to intersections of the scanning lines and the data lines, and the scanning lines are scanned. A scanning line driving circuit for supplying a scanning signal for sequentially selecting lines for each horizontal scanning period; a data line driving circuit for supplying a data signal having a pulse width corresponding to a gradation to be displayed on the plurality of data lines; A first reference signal whose waveform rises with a delay from the start of the horizontal scanning period and a second reference signal whose waveform rises from the start of the horizontal scanning period with a horizontal scanning period as one cycle. And a reference signal generating means for generating the first reference signal in a horizontal scanning period in which the corresponding scanning signal is active, and a second reference signal in the other horizontal scanning period. 1 reference signal A signal line driving circuit that generates a reference signal obtained by time-division-multiplexing the second reference signal and supplies the reference signal to each of the plurality of signal lines, and each of the plurality of pixel circuits uses the reference signal. A conversion holding unit that converts a pulse width of the data signal into a potential and holds a display potential corresponding to a gradation to be displayed; a comparison unit that compares the display potential with the reference signal; and And a generation unit configured to generate a pulse-width-modulated drive signal having the horizontal scanning period period based on the comparison result.

  Here, the generation unit does not reflect the comparison result of the comparison unit in the drive signal during the period in which the scanning signal is active, and after the period ends, the driving unit performs the driving according to the comparison result of the comparison unit. Preferably, a signal is generated. According to the present invention, it is possible to display an accurate gradation by masking the disturbance of the comparison result during the period in which the scanning signal is active.

  Next, an electronic apparatus according to the present invention includes the above-described electro-optical device. Such an electronic device corresponds to a personal computer, a mobile phone, an electronic camera, or the like.

  Further, the present invention can be understood as a driving method of a pixel circuit. As such an invention, a reference signal whose level changes in a predetermined cycle and a data signal having a pulse width corresponding to a gradation to be displayed in a predetermined writing period are supplied, and the reference signal is used to The pulse width of the data signal is converted into a potential, the display potential corresponding to the gradation to be displayed is held, the display potential is compared with the reference signal, and the pulse width is modulated based on the comparison result A drive signal is generated.

1 is a block diagram illustrating a configuration of a liquid crystal device according to a first embodiment of the present invention. It is a circuit diagram of pixel circuit 400A of i row j column. 4 is a timing chart showing the operation of the liquid crystal device 1A. 5 is a timing chart showing a relationship among a first power supply potential V1, a second power supply potential V2, a common potential com, and a potential VE supplied to the liquid crystal element 450. It is a circuit diagram of the pixel circuit 400B of the i row j column used for 2nd Embodiment of this invention. It is a block diagram which shows the structure of the liquid crystal device 1B which concerns on 3rd Embodiment. It is a timing chart of the embodiment. 2 is a circuit diagram of a pixel circuit 400C in an i-th row and a j-th column used in the embodiment. FIG. 4 is a timing chart showing the operation of the liquid crystal device 1B of the same embodiment. FIG. 44C is a circuit diagram of a pixel circuit 400D according to a modification of the embodiment. It is a circuit diagram which shows the structural example of the amplifier which concerns on a modification. It is a perspective view which shows the external appearance structure of the personal computer which is an example of an electric potential apparatus. It is a perspective view which shows the external appearance structure of the projection type display apparatus which is an example of an electric potential apparatus.

<1. First Embodiment>
FIG. 1 is a block diagram showing a schematic configuration of the liquid crystal device according to the first embodiment of the present invention. The liquid crystal device 1A includes a liquid crystal panel AA and an external circuit. The liquid crystal panel AA has an element substrate on which a thin film transistor (hereinafter referred to as TFT) and various wirings are formed, a transparent counter substrate on which a common electrode is formed on one surface, and an element substrate. And a liquid crystal sandwiched between the substrate and the substrate. In the liquid crystal panel AA, a display area W, a scanning line driving circuit 100A, and a data line driving circuit 200 are formed. Among these, m scanning lines 101 are formed in the display area W in parallel with the X direction. In addition, n data lines 103 are formed in parallel with the Y direction orthogonal to the X direction. In addition, m signal lines 102 are formed in parallel with the X direction. A pixel circuit 400 </ b> A is provided corresponding to each intersection of the scanning line 101 and the data line 103.

  The scanning line driving circuit 100A generates scanning signals Y1, Y2, Y3,..., Ym for sequentially selecting the plurality of scanning lines 101, and supplies them to each pixel circuit 400A. The scanning signal Y1 is a pulse having a width corresponding to one horizontal scanning period (1H) from the first timing of one vertical scanning period (1F), and is supplied to the scanning line 101 in the first row. Thereafter, the pulses are sequentially shifted and supplied as scanning signals Y2, Y3,..., Ym to the scanning lines 101 in the 2, 3,. In general, when the scanning signal Yi supplied to the scanning line 101 in the i-th row (i is an integer satisfying 1 ≦ i ≦ m) becomes high level, the scanning line 101 is selected.

  The data line driving circuit 200 supplies data signals X1, X2,..., Xn to the data lines 103 in the first, second,. Thereby, the data signals X1, X2,... Xn are supplied to each of the pixel circuits 400 positioned on the selected scanning line 101. In this example, the data signals X1 to Xn are signals having a pulse width corresponding to the gradation and having one of two levels of signal levels, high level and low level. In the following description, a data signal supplied to the data line 103 in the j-th column (j is an integer satisfying 1 ≦ j ≦ n) is referred to as a data signal Xj.

  The ramp signal generation circuit 500A supplies the ramp signal S to all the pixel circuits 400A via the signal line 102. The waveform of the ramp signal S is a ramp waveform with one horizontal scanning period as one cycle.

  The control circuit 300 generates various control signals and supplies them to the scanning line driving circuit 100A and the data line driving circuit 200. Further, the control circuit 300 outputs, for example, 10-bit gradation data Dout to the data line driving circuit 200. In this example, the control circuit 300 and the ramp signal generation circuit 500A are provided outside the liquid crystal panel AA, but some or all of these components may be taken into the liquid crystal panel AA. Furthermore, some of the components provided in the liquid crystal panel AA may be provided as an external circuit.

  Next, the pixel circuit 400A of the present embodiment will be described. FIG. 2 shows a circuit diagram of the pixel circuit 400A in the i-th row and j-th column. As shown in this figure, the pixel circuit 400A includes a selection transistor Tr, a switching element SW1, a holding capacitor 410, a comparator 420, and an inverter 421 that are turned on when the scanning signal Yi is active and turned off when the scanning signal Yi is inactive. .

  The selection transistor Tr is composed of, for example, an n-channel TFT, and one of the drain and the source is connected to the signal line 102, the other is connected to the node P, and the gate is connected to the data line 103. As described above, since the data signal Xj is a digital signal that is pulse-width modulated every horizontal scanning period, when the data signal Xj is at a high level, the selection transistor Tr is turned on and the ramp signal S is captured.

  The switching element SW1 is composed of, for example, an n-channel TFT, and one of the drain and the source is connected to the node P, the other is connected to the node A, and the gate is connected to the scanning line 101. The storage capacitor 410 is provided between the node A and a fixed potential (in this example, the ground potential GND). The comparator 420 compares the potential of the node A with the potential of the signal line 102. Since the ramp signal S is supplied to the signal line 102, the comparator 420 compares the potential of the node A with the level of the ramp signal S. When the potential VA of the node A exceeds the level of the ramp signal S, the comparator 420 compares the potential of the ramp A with the high level. When the potential VA of the node A falls below the level of the ramp signal S, a signal that goes low is output. The inverter 421 inverts the output signal of the comparator 420 and supplies it to the node D. The comparator 420 and the inverter 421 are configured by TFTs.

The pixel circuit 400A further includes an inverter 430, a selection circuit 440, and a liquid crystal element 450. These structures are constituted by TFTs.
In the selection circuit 440, the node E is connected to one terminal, the transfer terminal TG1 to which the second power supply potential V2 is supplied to the other terminal, the node E is connected to one terminal, and the first power supply is connected to the other terminal. And a transfer gate TG2 to which the potential V1 is supplied. Each of the transfer gates TG1 and TG2 is configured by connecting a p-channel TFT and an n-channel TFT in parallel. The transfer gates TG1 and TG2 are supplied with the potential VB of the node B as a control signal and the potential VC of the node C obtained by inverting it with the inverter 430. As a result, the potential VB is high level (potential VC is low level), the transfer gate TG1 is turned on, the transfer gate TG2 is turned off, and the potential VE of the node E becomes the second power supply potential V2. On the other hand, when the potential VB is at a low level (the potential VC is at a high level), the transfer gate TG2 is turned on, the transfer gate TG1 is turned off, and the potential VE of the node E becomes the first power supply potential V1.

The liquid crystal element 450 includes a pixel electrode 450a formed on the element substrate, a counter electrode 450b formed on the counter substrate, and liquid crystal sandwiched between the pixel electrode 450a and the counter electrode 450b.
A common potential com is supplied to the counter electrode 450b, the pixel electrode 450a is connected to the node E, and a potential VE is supplied.
A common potential com and a potential VE are applied to the liquid crystal, and the orientation and order of liquid crystal molecules change according to the applied voltage, so that gradation display by light modulation is possible. For example, in the normally white mode, the amount of light passing through the liquid crystal is limited as the applied potential increases. In the normally black mode, the amount of light that is transmitted is reduced as the applied potential is increased. Then, light having contrast according to the image signal is emitted for each pixel. For this reason, a predetermined display becomes possible.

  The potential VB of the node B has a level within the sampling value of the ramp signal S written in the storage capacitor 410 (the level of the ramp signal S when the selection transistor Tr switches from the on state to the off state) and within one horizontal scanning period. It is determined by the magnitude relationship with the changing ramp signal S. That is, when the sampling value exceeds the ramp signal S, the potential VB becomes low level, and the first power supply potential V1 is supplied to the liquid crystal element 450. On the other hand, when the sampling value falls below the ramp signal S, the potential VB. Becomes a high level, and the second power supply potential V 2 is supplied to the liquid crystal element 450.

  In other words, the liquid crystal element 450 is supplied with a pulse width modulation signal obtained by pulse width modulating the gradation to be displayed. If the sampling value of the ramp signal corresponding to the pulse width of the data signal Xj is written in one horizontal scanning period in one frame period (a period in which the m scanning lines 101 are scanned), the pixel circuit 400A has the inside. The comparison between the sampling value and the ramp signal S is repeatedly performed every horizontal scanning period. As a result, the period of the pulse width modulation signal supplied to the liquid crystal element 450 is one horizontal scanning period. Even if the transmittance of the liquid crystal is controlled in such a short cycle, a change in the transmittance can be sensed only on average by human vision. Therefore, it is possible to display an image with no flicker and no flicker.

  Next, the operation of the liquid crystal device 1A will be described with reference to FIG. In the following description, in the pixel circuit 400A in the i-th row and j-th column, the potentials VA, VD, and VE of each node are represented with “(i, j)”. In this example, the data signal Xj is a digital signal that becomes a high level or a low level, and represents a gradation with a pulse width every horizontal scanning period 1H.

  First, in the pixel circuit 400A in the i-th row and the j-th column, when the scanning signal Yi becomes active from the time t1a (high level) in the i-th horizontal scanning period starting from the time t1, and the i-th row is selected, the switching element SW1 is turned on. At this time, the data signal Xj is at the high level, and the data signal Xj changes from the high level to the low level at time t1b. When the data signal Xj becomes a high level, the ramp signal S is supplied to the holding capacitor 410 via the switching element SW1, so that the level of the ramp signal S at time t1b is sampled and held in the holding capacitor 410. As a result, the potential VA (i, j) of the node A falls from time t1a and coincides with the level of the ramp signal S at time t1b, and is then held at the level of the ramp signal S at time t1b.

The comparator 420 compares the potential VA of the node A with the level of the ramp signal S, and the inverter 421 inverts the comparison result to generate the potential VD. As a result, the potential VD (i, j) transitions from the low level to the high level at time t1b. Then, the comparison between the ramp signal S and the potential VA of the node A is repeatedly executed in each of the (i + 1) th and subsequent horizontal scanning periods started from the time t2.
By controlling the selection circuit 440 with the potential VD (i, j) obtained in this way, the potential VE (i, j) of the node E becomes the first power supply potential V1 and the second power supply potential as shown in FIG. Select V2.

  That is, the pulse-width-modulated data signal Xj is converted into a voltage indicating a gray scale using the ramp signal S, written and stored in the holding capacitor 410, and the written voltage is stored in the ramp signal S in the horizontal scanning period cycle. Thus, a pulse width modulation signal having a pulse width corresponding to the gradation to be displayed is repeatedly generated every horizontal scanning period.

  Next, in the pixel circuit 400A in the (i + 1) th row and jth column, the scanning signal Yi + 1 becomes active (high level) from the time t2a in the i + 1th horizontal scanning period starting from the time t2, and i + 1. When a row is selected, the switching element SW1 is turned on. At this time, the data signal Xj is at the high level, and the data signal Xj changes from the high level to the low level at time t2b. When the data signal Xj becomes a high level, the ramp signal S is supplied to the holding capacitor 410 via the switching element SW1, so that the level of the ramp signal S at time t2b is sampled and held in the holding capacitor 410. As a result, the potential VA (i + 1, j) at the node A rises from time t2a along the waveform of the ramp signal S to time t2b, and is then held.

Since the comparator 420 compares the potential VA of the node A with the level of the ramp signal S, the potential VD (i + 1, j) changes from the low level to the high level at time t2b. Then, the comparison between the ramp signal S and the potential VA of the node A is repeatedly executed in each of the i + 2 and subsequent horizontal scanning periods started from the time t3.
By controlling the selection circuit 440 with the potential VD (i + 1, j) obtained in this way, the potential VE (i + 1, j) of the node E becomes equal to the first power supply potential V1 as shown in FIG. The second power supply potential V2 is selected.

  Next, FIG. 4 shows a relationship among the first power supply potential V1, the second power supply potential V2, the common potential com, and the potential VE supplied to the liquid crystal element 450. As shown in this figure, the first power supply potential V1 and the second power supply potential V2 are in a relationship in which the high level and the low level are reversed. Furthermore, in this example, the polarity of the common potential com is reversed and driven, and accordingly, the polarities of the first power supply potential V1 and the second power supply potential V2 are reversed. By adopting such driving, the amplitude of the data signals X1 to Xn can be reduced. Since the data line 103 is a capacitive load, by reducing the amplitude of the data signals X1 to Xn, the driving capability of the data line driving circuit 200n can be reduced and the power consumption can be reduced.

In subfield driving for binary digital driving of lighting and extinguishing of pixels, it is necessary to write data to the pixel circuit in each of the plurality of subfields. According to the first embodiment described above, 1 A data signal may be written into the pixel circuit 400A once in a frame. Therefore, compared with subfield driving, the data transfer rate can be reduced as in analog driving. On the other hand, the drive waveform for the actual liquid crystal is binary digital drive, and is less affected by changes in the VT curve of the liquid crystal than analog drive, and is superior in terms of reliability.
Furthermore, a pseudo contour due to a luminance change in a frame due to a gradation code, which is a problem in digital driving using a subfield, can be avoided because it is a completely distributed code of one horizontal scanning period.
In addition, since the data signal may be a digital signal, the accuracy of gradation display can be improved. In addition, the data line driving circuit can be simplified.

<2. Second Embodiment>
Next, a liquid crystal device 1A according to the second embodiment will be described. The liquid crystal device 1A of the second embodiment is configured in the same manner as the liquid crystal device 1A of the first embodiment shown in FIG. 1 except that the pixel circuit 400B is used instead of the pixel circuit 400A.
FIG. 5 shows a circuit diagram of the pixel circuit 400B in the i-th row and j-th column. The pixel circuit 400B includes an inverter 470, a switching element SW2, and a coupling capacitor 460 instead of the comparator 420 and the holding capacitor 410 that compare the data signal Xj and the ramp signal S, and a point that the switching element SW3 is used. Thus, the configuration is the same as that of the pixel circuit 400A. Note that the pixel circuit 400B is formed of a TFT as in the pixel circuit 400A.

  The switching element SW1 is provided between the node F and the node P. The switching element SW2 is provided between the signal line 102 and the node F. In this example, the switching element SW1 is composed of an n-channel TFT, while the switching element SW2 is composed of a p-channel TFT. Therefore, the switching elements SW1 and SW2 are exclusively turned on. Specifically, when the scanning signal Yi is active, the switching element SW1 is turned on, the switching element SW2 is turned off, and the scanning signal Yi is not turned on. When active, the switching element SW1 is turned off and the switching element SW2 is turned on.

  Next, the coupling capacitor 460 is provided between the node F and the node G. Further, an inverter 470 and a switching element SW3 are provided in parallel between the node G and the node D. The switching element SW3 is composed of, for example, an n-channel TFT and is turned on when the scanning signal Yi becomes active. Therefore, when the scanning signal Yi is active and the i-row pixel circuit 400B is selected, the output terminal and the input terminal of the inverter 470 are connected, and the inverter 470 functions as an inverting amplifier. At this time, the node G connected to the input terminal of the inverter 470 is biased to the threshold potential V_th (intermediate potential between the high level and the low level) of the inverter 470, so the potential VG of the node G becomes the threshold potential V_th. . At the same time, the switching element SW1 is turned on. The selection transistor Tr supplies the ramp signal S to the node P while the data signal Xj is at a high level. Since the data signal Xj is pulse width modulated, the potential of the ramp signal S at the timing when the selection transistor Tr transitions from the on state to the off state is in accordance with the gradation to be displayed. Here, if the potential of the ramp signal S at the timing is Vs, the coupling capacitor 460 accumulates electric charge according to the potential difference ΔV (= Vs−V_th) with the node G as a reference.

  Next, when the i-th horizontal scanning period ends and the scanning signal Yi becomes inactive, the switching elements SW1 and SW3 are turned off and the switching element SW2 is turned on. While the input of the inverter 470 is in a high impedance state, the ramp signal S is supplied to one terminal of the coupling capacitor 460 connected to the node F via the switching element SW2. Therefore, the potential VG of the node G is VG = VF−ΔV = S−ΔV.

The inverter 470 compares the potential VG with the threshold potential V_th. When the potential VG exceeds the threshold potential V_th, the potential VD of the node D is set to a low level, while when the potential VG falls below the threshold potential V_th, The potential VD of D is set to the high level.
That is, the potential VD is set to the high level with S−ΔV <V_th. Here, since ΔV = Vs−V_th, the potential VD of the node D is set to the high level when S <Vs. Accordingly, the switching element SW3 and the inverter 470 function as means for comparing the ramp signal S with the potential Vs corresponding to the gradation to be displayed.

When the ramp signal S is written to the coupling capacitor 460, the potential difference ΔV is held until the ramp signal S is written again in the next frame. Therefore, once the ramp signal S is written in the period in which the data signal Xj is active, the comparison is executed in the horizontal scanning cycle which is the cycle of the ramp signal S, and the pulse width corresponding to the gradation to be displayed is set from the inverter 470. The pulse width modulation signal which has is output.
Therefore, also in the second embodiment, it is possible to display the luminance corresponding to the gradation to be displayed as in the first embodiment.

  Since the pixel circuit 400B according to the second embodiment does not use the comparator 420, the configuration can be simplified. Also in the liquid crystal device 1A of the second embodiment, a data signal may be written into the pixel circuit 400B once per frame, as in the first embodiment. Therefore, compared with subfield driving, the data transfer rate can be reduced as in analog driving. On the other hand, the drive waveform for the actual liquid crystal is binary digital drive, and is less affected by changes in the VT curve of the liquid crystal than analog drive, and is superior in terms of reliability. Furthermore, a pseudo contour due to a luminance change in a frame due to a gradation code, which is a problem in digital driving using a subfield, is not a problem because it becomes a completely distributed code of one horizontal scanning period.

<3. Third Embodiment>
Next, a third embodiment of the present invention will be described. In the first and second embodiments, the writing ramp waveform and the display ramp waveform are combined. In contrast, in the third embodiment, a writing ramp waveform and a display ramp waveform are prepared separately.
FIG. 6 shows a block diagram of a liquid crystal device 1B according to the third embodiment. The liquid crystal device 1B is the same as that shown in FIG. 1 except that a signal line driver circuit 600 is added, a ramp signal generation circuit 500B is used instead of the ramp signal generation circuit 500A, and a pixel circuit 400C is used instead of the pixel circuit 400A. The liquid crystal device 1A of the first embodiment shown in FIG.

  The ramp signal generation circuit 500B generates a first ramp signal Sw for writing and a second ramp signal Sr for display. As shown in FIG. 7, the first ramp signal Sw and the second ramp signal Sr have one horizontal scanning period as one cycle. The first ramp signal Sw for writing maintains an initial value for the first period Ta from the start of the horizontal scanning period, and has a ramp waveform in the second period Tb following this. On the other hand, the second ramp signal Sr for display has no period for maintaining the initial value, and the entire horizontal scanning period has a ramp waveform.

The reason for providing the first period Ta for maintaining the initial value in the first ramp signal Sw for writing is to provide a margin between the adjacent scanning signals Yi and Yi + 1. The scanning signal is exclusively active and the two scanning signals must not be active at the same time. For this reason, the scanning signal becomes active with a slight delay from the start of the horizontal scanning period.
If the ramp signal rises from the start of the horizontal scanning period, the ramp signal is wasted and the dynamic range becomes narrow during the period from the start of the horizontal scanning period until the scanning signal becomes active. Therefore, in the first ramp signal Sw for writing, the dynamic range is effectively utilized by setting the rising edge of the waveform as the start of the second period Tb.

  The signal line driver circuit 600 selects the first ramp signal Sw for writing in the horizontal scanning period in which the scanning signal Yi is active, and selects the second ramp signal Sr for display in the other horizontal scanning periods. Thus, the ramp signal Si is generated. As a result, as shown in FIG. 7, the horizontal scanning period in which the first ramp signal Sw for writing is selected in the order of the ramp signals S1, S2, S3,.

  Next, a circuit diagram of the pixel circuit 400C in the i-th row and the j-th column is shown in FIG. The pixel circuit 400C is configured similarly to the pixel circuit 400A of the first embodiment shown in FIG. 2 except that the ramp signal Si is supplied to the signal line 102 and the switching elements SW5 and SW6 are provided. Yes.

With this configuration, when the scanning signal Yi becomes active, a potential corresponding to the pulse width of the data signal Xj can be written to the storage capacitor 410. However, a disturbed waveform may be output to the node D during the period when the scanning signal Yi is active.
Therefore, in the pixel circuit 400C, the comparison results of the period are masked using the switching elements SW5 and SW6.

  The switching element SW5 is composed of a p-channel TFT, and one of the drain and the source is connected to the node D, the other is connected to the node B, and the gate is connected to the scanning line 101. The switching element SW6 is composed of an n-channel TFT, and one of the drain and the source is connected to the node B, the other is grounded, and the gate is connected to the scanning line 101.

  For this reason, the switching elements SW5 and SW6 are exclusively turned on, and when the scanning signal Yi is active (high level), the switching element SW5 is turned off and the switching element SW6 is turned on. When the scanning signal Yi is inactive (low level), the switching element SW5 is turned on and the switching element SW6 is turned off. Therefore, the potential VB of the node B becomes the ground potential when the scanning signal Yi is active, and becomes the potential VD of the node D when the scanning signal Yi is inactive.

  Here, the ramp signal Si is a signal obtained by time-division multiplexing the first ramp signal Sw for writing and the second ramp signal Sr for display, and in the i-th horizontal scanning period in which the scanning signal Yi is active. Becomes the first ramp signal Sw for writing, and becomes the second ramp signal Sr for display in other horizontal scanning periods. Therefore, a potential having a magnitude corresponding to the pulse width of the data signal Xj can be written into the storage capacitor 410 using the first ramp signal Sw, and by comparing this potential with the second ramp signal Sr for display. The pulse width modulated signal is output to node D.

FIG. 9 shows waveforms of respective parts of the liquid crystal device 1B. First, in the pixel circuit 400C in the i-th row and j-th column, when the scanning signal Yi becomes active from the time t1a (high level) in the i-th horizontal scanning period starting from the time t1, and the i-th row is selected, the switching element SW1 is turned on. At this time, the data signal Xj is at the high level, and the data signal Xj changes from the high level to the low level at time t1b. When the data signal Xj becomes a high level, the ramp signal Si is supplied to the holding capacitor 410 via the switching element SW1, so that the level of the ramp signal Si at time t1b is sampled and held in the holding capacitor 410.
Here, the ramp signal Si in the i-th horizontal scanning period is the first ramp signal Sw for writing. Since the first ramp signal S1 rises with a delay from the start of the horizontal scanning period, even if the time t2 at the start of the i-th horizontal scanning period and the time t1a at which the scanning signal Yi becomes active do not match, the storage capacitor A sufficiently low potential can be written to 410.

  The comparator 420 compares the potential VA of the node A with the level of the ramp signal Si, and the inverter 421 inverts the comparison result to generate the potential VD. As a result, the potential VD (i, j) transitions from the low level to the high level at time t1b. However, a disturbed waveform may be output to the node D during the period when the scanning signal Yi is active.

At this time, the switching element SW6 is turned on and the switching element SW5 is turned off. Therefore, in the i-th horizontal scanning period, the comparison result of the comparator 420 is masked and is not reflected in the potential VB (i, j) of the node B. When the switching element SW4 is turned on in the (i + 1) th horizontal scanning period, the comparator 420 compares the potential held in the holding capacitor 410 with the ramp signal Si, and compares the comparison result with the potential VB (i, j). As a result, the potential VB (i, j) rises from the low level to the high level in the (i + 1) th horizontal scanning period.
Here, in the (i + 1) th horizontal scanning period, the second ramp signal Sr for display is selected as the ramp signal Si. Since the second ramp signal Sr rises from the start of the horizontal scanning period, the dynamic range of the pulse width can be expanded compared to the first ramp signal Sw. Thereby, a large contrast can be obtained.

  Next, in the pixel circuit 400C in the (i + 1) th row and jth column, the scanning signal Yi + 1 becomes active (high level) from the time t2a in the i + 1th horizontal scanning period starting from the time t2, and i + 1. When a row is selected, the switching element SW1 is turned on. At this time, the data signal Xj is at the high level, and the data signal Xj changes from the high level to the low level at time t2b. When the data signal Xj becomes a high level, the ramp signal Si is supplied to the holding capacitor 410 via the switching element SW1, so that the level of the ramp signal Si at time t2b is sampled and held in the holding capacitor 410. As a result, the potential VA (i + 1, j) at the node A rises from time t2a along the waveform of the ramp signal S to time t2b, and is then held.

Since the comparator 420 compares the potential VA of the node A with the level of the ramp signal Si, the potential VD (i + 1, j) changes from the low level to the high level at time t2b. However, since the switching element SW4 is in the OFF state during the period when the scanning signal Yi + 1 is active, the operation of the comparator 420 becomes unstable during the shaded period in the figure.
Therefore, the comparison result of the comparator 420 is masked using the switching element SW6 and the switching element SW5. When the switching element SW4 is turned on in the (i + 2) th horizontal scanning period, the comparator 420 compares the potential held in the storage capacitor 410 with the ramp signal Si, and compares the comparison result with the potential VB (i + 1, j). As a result, the potential VB (i + 1, j) rises from the low level to the high level in the (i + 2) th horizontal scanning period.

  By repeating the above operation, it is possible to display a more accurate gradation while masking the waveform disturbance in the writing period. Also in the present embodiment, the data transfer rate can be reduced as in analog driving, and a pseudo contour due to a luminance change in the frame due to the gradation code can be avoided.

  In the third embodiment, as in the second embodiment, the inverter 470 and the switching element SW2 are used to constitute a means for comparison, and the coupling capacitor 460 holds a potential difference corresponding to the pulse width of the data signal Xj. May be. In this case, the pixel circuit 400D is as shown in FIG.

<4. Modification>
The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible.
(1) In each embodiment described above, the reference signals to be compared with the potential corresponding to the pulse width of the data signal Xj are the ramp signals S and S1 to Sm. However, the present invention is not limited to the ramp waveform. Of course. That is, any signal with a certain period may be used. More specifically, it may be a signal that monotonously decreases after the waveform monotonously increases, or a signal that monotonously increases after monotonously decreasing.
Furthermore, the reference signal to be compared may have a gamma characteristic. That is, the signal waveform may be a curve with a gamma characteristic. In this case, gamma characteristics can be imparted simultaneously with the pulse width modulation. Also, one of the first ramp signal Sw for writing and the second ramp signal Sr for display may be a gamma characteristic waveform and the other may be a ramp waveform.
The period of the reference signal is arbitrary and is not limited to a natural number times the horizontal scanning period, but may be a natural number times the horizontal scanning period in consideration of synchronization with scanning line driving.

(2) In the above-described embodiment, the polarity of the common potential com is inverted at a predetermined period. However, the polarity of the common potential com may not be inverted.

(3) In the above-described embodiment, the display device using the liquid crystal element 450 has been described as an example. However, the present invention is not limited to this, and may be applied to a display device using a light emitting element. For example, you may apply to an apparatus using light emitting elements, such as an organic EL element, an inorganic EL element, and a light emitting diode. That is, the present invention can be applied to an electro-optical device using an electro-optical element whose optical characteristics are changed by electric energy, such as the liquid crystal element 450 and the light-emitting element.
In the case of using a light emitting element, it is not necessary to invert the polarity of the applied voltage, but gradation is displayed by modulating the pulse width of a signal applied to the light emitting element.

(4) In the third embodiment and the modification described above, the mask process is performed using the switching elements SW5 and SW6. However, the present invention is not limited to this, and the mask process may not be performed. Good. In this case, the accuracy of display gradation is lowered, but the configuration can be simplified.
For example, in the pixel circuit 400C illustrated in FIG. 8 and the pixel circuit 400D illustrated in FIG. 10, the switching elements SW5 and SW6 may be deleted and the node D may be connected to the node B.

(5) The pixel circuits 400B and 400D using the coupling capacitor 460 described above constitute an amplifier using the inverter 470 and the switching element SW3. If the gain is insufficient in one stage, for example, FIG. ), A plurality of stages of inverters and switching elements may be connected in series. Alternatively, as shown in FIG. 11B, inverters may be connected in series, and a switching element may be connected between the input at the first stage and the output at the final stage.

<5. Application example>
Next, an electronic apparatus using the liquid crystal device 1 according to the present invention will be described. FIG. 12 is a perspective view showing the configuration of a mobile personal computer that employs the liquid crystal device 1A (1B) according to any one of the embodiments described above as a display device. The personal computer 2000 includes a liquid crystal device 1A (1B) as a display device and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002.

  FIG. 13 is a schematic view illustrating a projection display device (projector) 90 as an electronic device. As shown in FIG. 13, the projection display device 90 includes an illumination device 92, a separation optical system 94, three liquid crystal devices 1 (1 r, 1 g, 1 b) and a projection optical system 96 according to the above embodiments. To do.

  The separation optical system 92 separates the illumination light emitted from the illumination device 92 into a plurality of monochromatic lights (red light, green light, blue light) and irradiates each liquid crystal device 1. Specifically, red light r of the illumination light enters the liquid crystal device 1 r after being reflected by the dichroic mirror 941 and the mirror 942. The green light g transmitted through the dichroic mirror 941 is reflected by the dichroic mirror 943 and enters the liquid crystal device 1g. The blue light b transmitted through the dichroic mirror 943 is incident on the liquid crystal device 1b after being reflected by the mirror 944 and the mirror 945.

  Each liquid crystal device 1 is used as a light modulator (light valve) that modulates incident light to form an image. The liquid crystal device 1r modulates the red light r coming from the mirror 942 to form a red image. Similarly, the liquid crystal device 1g forms a green image, and the liquid crystal device 1b forms a blue image. The projection optical system 96 projects the emitted light from each liquid crystal device 1 onto the display surface 98. The projection optical system 96 includes a dichroic prism 961 that synthesizes light emitted from each liquid crystal device 1 (red light, green light, and blue light), and a projection lens 962 that projects light emitted from the dichroic prism 961 onto the display surface 98. It is comprised including. Therefore, a color image is displayed on the display surface 98.

  The liquid crystal device 1 according to each of the above embodiments is used as a direct-view display device in addition to the projection display device 90 illustrated in FIG. Electronic devices to which the electro-optical device according to the present invention is applied include cellular phones, portable information terminals, digital still cameras, televisions, video cameras, car navigation devices, pagers, electronic notebooks, electronic paper, calculators, word processors, workstations. Video phones, POS terminals, printers, scanners, copiers, video players, devices equipped with touch panels, and the like.

400A, 400B, 400C ... Pixel circuit, 1A, 1B ... Liquid crystal device, 410 ... Holding capacitor, 420 ... Comparator, SW1 to SW6 ... Switching element, 440 ... Selection circuit, 470 ... Inverter, 460 ... Coupling capacitors 101... Scanning lines 102... Signal lines 103... Data lines 100... Scanning line driving circuits 200... Data line driving circuits 500 A and 500 B.

Claims (12)

A pixel circuit to which a reference signal whose level changes in a predetermined cycle and a data signal having a pulse width corresponding to a gradation to be displayed in a predetermined writing period are supplied.
A conversion holding unit for converting a pulse width of the data signal into a potential using the reference signal and holding a display potential corresponding to a gradation to be displayed;
A comparison unit for comparing the display potential with the reference signal;
Based on a comparison result of the comparison unit, a generation unit that generates a pulse width modulated drive signal;
A pixel circuit comprising: The conversion holding unit is
A capacitor for holding the display potential;
A sampling unit that supplies the reference signal to the storage capacitor only during a period of a pulse width of the data signal in the writing period;
The pixel circuit according to claim 1, further comprising: The reference signal is supplied via a signal line;
The sampling unit
A select transistor provided between the signal line and the first node and turned on only for a period of a pulse width of the data signal;
A first switching element provided between the first node and the second node and turned on only during the writing period;
The capacitor is a storage capacitor in which one terminal is connected to the second node and a fixed potential is supplied to the other terminal.
The pixel circuit according to claim 2. The reference signal is supplied via a signal line;
The sampling unit
A select transistor provided between the signal line and the first node and turned on only for a period of a pulse width of the data signal;
A first switching element which is provided between the first node and the second node and is turned on only during the writing period;
A second switching element provided between the signal line and the second node and turned on only during a period other than the writing period;
The comparison unit includes:
An inverter having an input terminal connected to the third node and an output terminal connected to the fourth node;
A third switching element provided between the third node and the fourth node and turned on only during the writing period;
The capacitor is a coupling capacitor provided between the second node and the third node.
The pixel circuit according to claim 2. In the mask period including the writing period, the generation unit does not reflect the comparison result of the comparison unit in the drive signal, and after the mask period ends, the generation signal is output according to the comparison result of the comparison unit. Generate,
5. The pixel circuit according to claim 1, wherein the pixel circuit is a pixel circuit. The comparison unit outputs a comparison signal indicating a comparison result to the fourth node,
The generation unit includes a mask unit and a selection unit,
The mask portion is
A fifth switching element which is turned off in the mask period, turned on in a period other than the mask period, one terminal is connected to the fourth node, and the other terminal is connected to the fifth node; ,
A sixth switching element that is turned on in the mask period, turned off in a period other than the mask period, one terminal is connected to the fifth node, and the other terminal is supplied with a first potential; With
The selection unit selects either the first level or the second level based on the output signal of the mask unit, and outputs the selected drive signal.
The pixel circuit according to claim 5.   6. The pixel circuit according to claim 1, wherein the reference signal has a ramp waveform or a waveform with a gamma characteristic. Multiple data lines,
A plurality of scan lines;
Multiple signal lines,
A plurality of pixel circuits provided corresponding to intersections of the scanning lines and the data lines;
A scanning line driving circuit for supplying a scanning signal for sequentially selecting each scanning line for each horizontal scanning period to the plurality of scanning lines;
A data line driving circuit for supplying a data signal having a pulse width corresponding to a gradation to be displayed on the plurality of data lines;
A reference signal generating unit that generates a reference signal whose level changes with a horizontal scanning period as one cycle and supplies the reference signal in common to the plurality of signal lines;
Each of the plurality of pixel circuits is
A conversion holding unit for converting a pulse width of the data signal into a potential using the reference signal and holding a display potential corresponding to a gradation to be displayed;
A comparison unit for comparing the display potential with the reference signal;
A generation unit that generates a pulse width modulated drive signal of the horizontal scanning period period based on the comparison result of the comparison unit;
An electro-optical device. Multiple data lines,
A plurality of scan lines;
Multiple signal lines,
A plurality of pixel circuits provided corresponding to intersections of the scanning lines and the data lines;
A scanning line driving circuit for supplying a scanning signal for sequentially selecting each scanning line for each horizontal scanning period to the plurality of scanning lines;
A data line driving circuit for supplying a data signal having a pulse width corresponding to a gradation to be displayed on the plurality of data lines;
A first reference signal whose waveform rises with a delay from the start of the horizontal scanning period and a second reference signal whose waveform rises from the start of the horizontal scanning period with a horizontal scanning period as one cycle. A reference signal generating means for generating
The first reference signal is selected in the horizontal scanning period in which the corresponding scanning signal is active, and the second reference signal is selected in the other horizontal scanning period, and the first reference signal and the second reference signal are selected. A signal line driving circuit that generates a reference signal that is time-division multiplexed signals and supplies the signal to each of the plurality of signal lines,
Each of the plurality of pixel circuits is
A conversion holding unit for converting a pulse width of the data signal into a potential using the reference signal and holding a display potential corresponding to a gradation to be displayed;
A comparison unit for comparing the display potential with the reference signal;
A generation unit that generates a pulse width modulated drive signal of the horizontal scanning period period based on the comparison result of the comparison unit;
An electro-optical device. The generation unit does not reflect the comparison result of the comparison unit in the drive signal during a period when the scanning signal is active, and generates the drive signal according to the comparison result of the comparison unit after the period ends. To
The electro-optical device according to claim 9.   An electronic apparatus comprising the electro-optical device according to claim 8. A reference signal whose level changes in a predetermined cycle and a data signal having a pulse width corresponding to a gradation to be displayed in a predetermined writing period are supplied.
Using the reference signal, the pulse width of the data signal is converted into a potential, and a display potential corresponding to the gradation to be displayed is held.
Comparing the display potential with the reference signal;
Based on the comparison result, a pulse width modulated drive signal is generated.
A driving method for an electro-optical device.

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