1229439 五、發明說明（1) 本發明係有關於一種半導體之製造方法，特別 一，半導體製程中之預清潔（pre-clean)方法，使預清潔 爐箱（pre-clean chamber)中内壁上附著物之剝落時^ = 以，估測’而可依所估測之時間定時清理爐箱内壁、，0 剝洛物掉洛而晶片上形成缺陷（d e f e c t)。 第1A〜IF圖顯示了傳統上在〇.15，之半導體製程 作孟屬層間插塞（P 1 u g )所進行之步驟。 上开閱第1a圖’提供一石夕基底1〇，在石夕基底b 上形成一金屬層11，如鋁或銅。 接著，請參閱第1B圖，在金屬層丨丨上再依序形成一 ，㈣及氮化層13。介電層12係—氧切層，而氮化層13 糸-鼠氧切層，帛以在爾後進行黃光㈣時增加光阻之 解析度。 再來，凊參閱第1C圖，在介電層12及氮化層13中形成 多個介層孔14(VIA)，介層孔14穿越介電層12及氮化層13 ί广止於金屬層11，使金屬層11之表面暴露。另外，金屬 因被暴露而與環境中之氧氣發生氧化作用，生成一金 屬氧化層1 4 1，如氧化銅或氧化鋁。 然後’請參閱第1D圖，開始藉由氬濺擊（Ar_sputter) 進行預ί潔之動作，而將金屬氧化層⑷去除。 接f ’ 4參閱第1Ε圖，在介層孔i 4去沈積一阻障層 1 5，如氮化鈦或鎢化鈦。 凊參閱第1F圖，在介層孔14中填入-導電層 1 6，如鎢而形成插塞。 0503-6149TWF;TSMC2000-0936;Vincent.ptd 1229439 五、發明說明（2) 此外在第1D圖中進行預清潔步驟時，一 清潔爐箱，並在爐箱中右今备 叙係使用預 面生成之么愿ί爐中 于濺擊，使金屬層11表 電阻值。回士氧！*匕層141被去除’以減低金屬層間插塞之 ⑷同樣遭受V子鼠轟化擊層:3由Λ在濺擊^ 後，其内壁會逐漸生成…：‘爐=使用-段時間 ::Γ 剝落而掉落至晶片表面，造成晶片 然而，在上=值者必需經常進行爐箱内壁之清理。 箱内壁產生之附著物=之插塞製程中，由於預清潔時在爐 化物，使得ΐ::Γ4=::、，,ι可能同時包含氮化物及氧 箱之時間，因此常在f : ::t法準確得知應清理爐 上產生缺陷。"以：：中！=剝落而導致晶片 良率降低。 丄驗中，迈種現象可造成5〜10%之 為了解決上述問韻 . 法，包括以下步驟。接徂“明提供-種半導體製造方 及一覆蓋該金屬層之絶绦二基底，該基底上具有一金屬層 化層。形成-穿越該;蔓甚：。在該絕緣層上形成-護蓋氧 露該金屬I，致使該：f乳化層及該絕緣層之介層孔而暴 擊而移除該金屬氧^層。&上生成一金屬氧化層。經由賤 其t ’更包括以下步驟。在該介層孔中之金屬展 層移除。 層孔中填入一導電層。將該護蓋氧化1229439 V. Description of the invention (1) The present invention relates to a method for manufacturing a semiconductor, in particular, a pre-clean method in a semiconductor process, which attaches an inner wall of a pre-clean chamber When the object is peeled off, ^ =, estimate, and the inner wall of the furnace can be cleaned regularly according to the estimated time. 0, the object is peeled off, and a defect is formed on the wafer. Figures 1A to IF show the steps traditionally performed by a semiconductor process at 0.15 to produce a Mons interlayer plug (P 1 u g). The first view of FIG. 1a is provided with a Shixi substrate 10, and a metal layer 11 such as aluminum or copper is formed on the Shixi substrate b. Next, referring to FIG. 1B, a metal layer, a silicon layer, and a nitride layer 13 are sequentially formed on the metal layer. The dielectric layer 12 is an oxygen-cutting layer, and the nitrided layer 13 鼠 -mouse oxygen-cutting layer, so as to increase the resolution of the photoresistance when yellow light is subsequently performed. Next, referring to FIG. 1C, a plurality of vias 14 (VIA) are formed in the dielectric layer 12 and the nitride layer 13. The vias 14 pass through the dielectric layer 12 and the nitride layer 13 and stop at the metal. Layer 11 to expose the surface of the metal layer 11. In addition, the metal is oxidized with oxygen in the environment due to exposure, forming a metal oxide layer 1 41, such as copper oxide or aluminum oxide. Then, please refer to FIG. 1D and start the pre-cleaning action by argon spattering to remove the metal oxide layer. Referring to FIG. 1E next to f'4, a barrier layer 15 such as titanium nitride or titanium tungsten is deposited on the via hole i4.凊 Referring to FIG. 1F, the via 14 is filled with a conductive layer 16 such as tungsten to form a plug. 0503-6149TWF; TSMC2000-0936; Vincent.ptd 1229439 V. Description of the invention (2) In addition, when performing the pre-cleaning step in Figure 1D, clean the oven and use the pre-surface generation in the oven. What would you like to do in the furnace, so that the metal layer 11 has a resistance value. Shi Shi oxygen! * Dagger layer 141 is removed 'to reduce the plug between metal layers. It also suffers from the bombardment layer of V rat: 3 After ^ is splashed by Λ, its inner wall will gradually generate ...:' furnace = use-period of time :: Γ peels off and falls to the surface of the wafer, causing the wafer. However, those who are above must always clean the inner wall of the oven. Attachment produced on the inner wall of the tank = In the plugging process, the pre-cleaning is performed on the furnace, so that ΐ :: Γ4 = :: ,,, ι may contain both nitride and oxygen tank time, so it is often at f:: The: t method accurately knows that defects should be removed from the furnace. " With :: Medium! = Degradation of wafers caused by chipping. In the test, the phenomenon of seeding can cause 5 ~ 10%. In order to solve the above problem, the method includes the following steps. Next to "provide a semiconductor manufacturer and a second substrate covering the metal layer, which has a metal layer on the substrate. Forming-crossing the; Mangan: forming a protective cover on the insulating layer The oxygen exposes the metal I, which causes the: f emulsified layer and the interlayer pores of the insulating layer to be violently removed to remove the metal oxygen layer. A metal oxide layer is formed on top of the metal layer. The method includes the following steps: The metal layer in the via hole is removed. A conductive layer is filled in the via hole. The cover is oxidized.
1229439 五、發明說明（3) 本务月藉由在進行濺擊清潔 / (Cap-Oxide)，使爐箱内壁之附著办成一護蓋氧化層 掌控其可能剝落時間而 物，氧化物，以利於 片上形成缺陷。 U相’避免意外掉落於晶 以下’就圖式說明本發明之一 例。 ^月 種半導體製造方法實施 圖式簡單說明 第1 A〜1F圖顯示傳統插塞之製造過程； 第2 A〜2F圖顯示本發明之半導體製方 之製造過程。 w方法中貫^例 符號說明 11、2卜金屬層； 13、23〜氮化層； 141、241〜金屬氧化層 1 6、2 6〜導電層； 1 〇、20〜基底； 12、22〜介電層； 1 4、2 4〜介層孔； 1 5、2 5〜阻障層； CapOxide〜護蓋氧化層 實施例 第2A〜2F圖顯示了傳統上在〇i5//m之半導體製程中製 作金屬層間插塞（p 1 u g )所進行之步驟。 首先，請參閱第2A圖，提供一矽基底2〇，在石夕基底2〇 上形成一金屬層21，如紹或銅。 一1229439 V. Description of the invention (3) This month, by performing splash cleaning / (Cap-Oxide), the inner wall of the furnace box is attached as a cover oxide layer to control its possible peeling time, oxide, and Facilitates the formation of defects on the chip. The U-phase 'prevents accidental dropping below the crystal' and illustrates an example of the present invention with reference to the drawings. ^ Month implementation of a semiconductor manufacturing method Brief description of the drawings Figures 1A to 1F show the manufacturing process of a conventional plug; Figures 2A to 2F show the manufacturing process of the semiconductor manufacturing method of the present invention. In the method, ^ example symbols are used to explain the metal layers 11 and 2; 13, 23 to the nitride layer; 141, 241 to the metal oxide layer 16, 26 to the conductive layer; 10, 20 to the substrate; 12, 22 to the Electrical layer; 14, 24 ~ via hole; 15, 2, 5 ~ barrier layer; CapOxide ~ cap oxide layer embodiment 2A ~ 2F shows traditionally in the semiconductor process of 5 // m Steps for making a metal interlayer plug (p 1 ug). First, referring to FIG. 2A, a silicon substrate 20 is provided, and a metal layer 21 such as Shao or copper is formed on the Shixi substrate 20. One
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五、發明說明（4) 接著，請參閱第26圖，在金屬層21上再依序形成一介 電層22、氮化層23及護蓋氧化層Cap〇xide。介電層“係一 乳化矽層，氮化層23係一氮氧化矽層，而護蓋氧化層 apOxide亦為一氧化矽層，用以在爾後進行黃光蝕刻時增 光阻之解析度。其中，遵盍氧化層CapQxide之厚度約為 ^ 再來，請參閱第2(：圖，在介電層22、氮化層23及護蓋 氧$層CapOxide中形成多個介層孔24(VIA)，介層孔24穿 越介電層22、氮化層23及護蓋氧化層Cap0xide而停止於金 ，層21，使金屬層21之表面暴露。另外，金屬層21因被暴 露而與環境中之氧氣發生氧化作用，生成一金屬氧化層 2 4 1 ’如氧化銅或氧化鋁。 八二後明參閱弟2D圖’開始藉由氬丨賤擊（Ar-sputter) 進行預清潔之動作，而將金屬氧化層24 1去除。 接著’請參閱第2E圖，在介層孔24中沈積一阻障層 2 5，如氮化鈦或鎢化鈦。 最後’請參閱第2F圖，在介層孔24中填入一導電層 2 6 ’如鶴。同時’可利用化學機械研磨法（CMP)將護蓋氧 化層CcpOxide去除，同時完成插塞之形成。 在第2D圖中進行預清潔步驟時，護蓋氧化層CapOxide 代替習知技術中之氮化層丨3 (第丨D圖）遭受離子轟擊，所以 使爐箱内壁之附著物均來自氧化層。如此，在進行預清潔 時’在爐箱内壁產生之附著物僅有氧化物，使得其剝落時 間較容易估測而可以較準碓地得知應清理爐箱之時間，而V. Description of the Invention (4) Next, referring to FIG. 26, a dielectric layer 22, a nitride layer 23, and a cap oxide layer Capoxide are sequentially formed on the metal layer 21. The dielectric layer is an emulsified silicon layer, the nitride layer 23 is a silicon oxynitride layer, and the cap oxide layer apOxide is also a silicon oxide layer, which is used to increase the resolution of the photoresist during yellow light etching. The thickness of the CapQxide oxide layer is about ^ Again, please refer to FIG. 2 (: figure, a plurality of vias 24 (VIA) are formed in the dielectric layer 22, the nitride layer 23, and the cap oxygen layer CapOxide. The interlayer hole 24 passes through the dielectric layer 22, the nitride layer 23, and the cap oxide layer Cap0xide and stops at gold, layer 21, and exposes the surface of the metal layer 21. In addition, the metal layer 21 is exposed to the environment due to exposure. Oxygen is oxidized to form a metal oxide layer 2 4 1 'such as copper oxide or aluminum oxide. Refer to the 2D picture after August 22' and start the pre-cleaning action by Ar-sputter. The metal oxide layer 24 1 is removed. Next, please refer to FIG. 2E, and deposit a barrier layer 25, such as titanium nitride or titanium tungsten, in the via hole 24. Finally, please refer to FIG. 2F, in the via hole. Fill 24 with a conductive layer 2 6 'like a crane. At the same time', the chemical oxide layer CcpOxide can be covered by chemical mechanical polishing (CMP). Remove and complete the formation of the plug at the same time. In the pre-cleaning step in Figure 2D, the cap oxide layer CapOxide replaces the nitride layer in the conventional technology 丨 3 (Figure 丨 D), which is subject to ion bombardment, so the furnace box The attachments on the inner wall are from the oxide layer. In this way, during the pre-cleaning, the attachments generated on the inner wall of the furnace box are only oxides, making the peeling time easier to estimate and knowing more accurately that the furnace box should be cleaned Time, and
0503-6149TWF;TSMC2000-0936;Vincent.ptd 第9頁 1229439 五、發明說明⑸ 附^ =時對爐箱進行清理，亦不會在製造過程中意外發生 明之剝落而導致晶片產生缺陷。在實際之經驗中，本發 提高=二體製造方法應用於2M之SRAM產品上時，可將良^ 以限明已以一較佳實施例揭露如1，然其並非用 :’和範圍卜當可作些許之更動：：不：離本發明之精 範圍當視後附之申請專利範圍；；定者：：本發明之保 0503-6149TWF;TSMC2000-0936;Vincent.ptd 第10頁0503-6149TWF; TSMC2000-0936; Vincent.ptd Page 9 1229439 V. Description of the invention ⑸ Attached ^ = When the furnace is cleaned, it will not accidentally peel off during the manufacturing process and cause defects in the wafer. In actual experience, when the improvement of the present invention is applied to a 2M SRAM product, the good method can be used to limit the exposure to 1 as a preferred embodiment, but it is not used: 'and scope When you can make some changes :: No: Depart from the scope of the present invention, the scope of patents attached to the application ;; Set :: the guarantee of the present invention 0503-6149TWF;