472319 五、發明說明（1) 5 - 1發明領域： 本發明係有關於移除蝕刻殘留物的方法，特別是一種 移除含氟殘留物的方法；此含氟殘留物會造成低介電常數 介質與金屬擴散阻絕層（metal diffusion barrier)的黏 著性差。 5-2發明背景： 及或摻與底或部 内接的矽的線在 件連中晶件連些 元層材多元層這 作一底一路一， 構第的在電第間 結與件接體在之 線線元連積接分 連連路内與連部 屬層電層是内他 金二體一線的其 重第積第屬般的。 多成在，金 一構的 用形可是與。結成 利在接種矽接或完 路。連一晶連件線 電作内外多相元連 體工層另而構路層 導接一。，結電二 半連第觸成或體第 合内，接形件積過 整的時相上元與透 高間接域線的接是 件連區屬上連上 元内質金材内分 隨著元件尺寸設計的縮小，為了克服RC延遲的問題， 發展成使用銅金屬與低介電常數介電層的新製程，例如雙 鑲嵌製程。雙鑲嵌製程可直接運用更小的設計法則，且大 部分的雙鑲嵌製程在内連線結構上可產生一平坦化的表面 。因此，運用雙鑲嵌製程可用較少的步驟達到後續製程所472319 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for removing etching residues, especially a method for removing fluorine-containing residues; this fluorine-containing residue will cause a low dielectric constant The adhesion between the dielectric and the metal diffusion barrier is poor. 5-2 Background of the Invention: And the wire connected to the bottom or the inner part of the silicon is connected in the piece, the crystal piece is connected to some element layers, and the multiple layers are made one by one, one way and one way. The line layer element continuous product is connected to the connection layer and the subordinate layer of the electrical layer is the inner product of the inner body and the second layer. More than in, the use of the shape of Jin Yi structure but. Formation is facilitated by inoculation or completion. Connected with a crystal connecting line Electrically operated internal and external multi-phase element connected working layer and road construction layer are connected one by one. The connection of the second half of the connection and the connection of the body, and the time when the connecting pieces are over-integrated, the connection between the upper element and the indirect domain line of the high-level is the inner region of the upper element. In order to reduce the component size design, in order to overcome the problem of RC delay, a new process using copper metal and a low dielectric constant dielectric layer has been developed, such as a dual damascene process. The dual damascene process can directly apply smaller design rules, and most of the dual damascene process can produce a flat surface on the interconnect structure. Therefore, the dual-damascene process can be used to reach subsequent processes in fewer steps.
第4頁 472319 五、發明說明（2) 需的表面，如第一圖所示，為一銅/低介電常數介電質雙 鑲嵌結構。一銅導體結構1 3 0與一第一低介電常數介電層 1 1 0相鄰，其上覆蓋一覆蓋層（c a p 1 a y e r ) 1 4 0，例如氮化 矽層；一已蝕刻出圖案的第二低介電常數介電層1 2 0於覆 蓋層1 4 0上。 接著*触刻暴露出氮化石夕覆蓋層1 4 0。然而刻氮 化矽是使用含氟的電漿，例如C H 2F 2-0 2-A r電漿進行，有些 氟化高分子物質便會在此蝕刻步驟中形成。接著進入洗淨 程序移除蝕刻殘留物；通常，以含氨類的有機溶劑移除蝕 刻殘留物，同時不會攻擊低介電常數層（1 〇 w - k f i 1 m )。然 而，氟化高分子物質很難以這類有機溶劑移除；這些殘留 的氟化高分子物質會導致低介電常數介電層與接下來要形 成的金屬擴散阻絕層間的黏著性差，進一步導致剝離的問 題，因此，殘留的含氟物質在蝕刻後洗淨程序中必須完全 移除才行。 5 - 3發明目的及概述： 鑒於上述之發明背景中，傳統蝕刻後的洗淨過程所產 生的諸多缺點，本發明提供一種移除殘留氟化高分子物質 的方法；在蝕刻後洗淨過程中加入濺鍍處理可以破壞氟化 高分子物質結構。Page 4 472319 V. Description of the invention (2) The required surface, as shown in the first figure, is a copper / low-k dielectric dual damascene structure. A copper conductor structure 130 is adjacent to a first low-k dielectric layer 1 110, and is covered with a cap 1 ayer 1 40, such as a silicon nitride layer; an etched pattern The second low-k dielectric layer 12 is on the cover layer 140. Then * contact lithography exposes the nitrided layer 1 4 0. However, silicon nitride is etched using a fluorine-containing plasma, such as a CH 2F 2-0 2-A r plasma. Some fluorinated polymer materials are formed during this etching step. Then proceed to the cleaning process to remove the etching residues; usually, the etching residues are removed with an organic solvent containing ammonia without attacking the low dielectric constant layer (10 w-k f i 1 m). However, fluorinated polymer materials are difficult to remove with this type of organic solvent; these residual fluorinated polymer materials can cause poor adhesion between the low-k dielectric layer and the metal diffusion barrier layer to be formed next, further leading to peeling Therefore, the remaining fluorine-containing substances must be completely removed during the post-etching cleaning process. 5-3 Purpose and Summary of the Invention: In view of the above-mentioned backgrounds of the invention, the conventional cleaning process after etching has many disadvantages, the present invention provides a method for removing residual fluorinated polymer materials; during the cleaning process after etching The addition of sputtering can destroy the structure of the fluorinated polymer material.
472319 五、發明說明（3) 本發明的另一目的在提供一防止介層或溝槽元件中 metal diffusioη阻絕層黏著性弱的方法；在钱刻後洗淨 過程中加入烘烤處理以移除（d e g a s )蝕刻殘留物。 根據以上所述之目的，揭露一種在雙鑲嵌（dua 1 damascene)製程中移除複數個含氟姓刻殘留物的方法，至 少包括提供一雙鑲嵌結構，其具有一銅導體結構於其中， 一覆蓋層（cap layer)於銅導體結構及雙鑲嵌結構上，及 一具有至少一位於銅導體結構上方之一開口的低介電常數 介電層，例如以旋塗高分子形成之介電層，於覆蓋層上β 以含有氟成分的電漿蝕刻覆蓋層以暴露出銅導體結構。接 著，以一溶劑清洗雙鑲嵌結構；及將雙鑲嵌結構置入一爐 管中或電漿（氬或氳氣）濺鍍處理，或是兩者皆有，以移除 含氟I虫刻殘留物。在清洗過程中加入供烤及滅鐘處理可移 除含氟蝕刻殘留物，進而防止低介電常數介電層與接著要 形成的金屬擴散阻絕層之間的黏著不足，進而防止其剝落 5 - 4發明詳細說明： 本發明的半導體設計可被廣泛地應用到許多半導體設 計中，並且可利用許多不同的半導體材料製作，當本發明472319 V. Description of the invention (3) Another object of the present invention is to provide a method for preventing the weak adhesion of the metal diffusioη barrier layer in the interposer or trench element; adding a baking treatment to remove it during the washing process after money carving (Degas) Etching residue. According to the above-mentioned purpose, a method for removing a plurality of fluorine-containing inscription residues in a dual damascene process is disclosed, including at least providing a dual damascene structure having a copper conductor structure therein. A cap layer on the copper conductor structure and the dual damascene structure, and a low dielectric constant dielectric layer having at least one opening above the copper conductor structure, such as a dielectric layer formed by spin coating a polymer, On the cover layer, the cover layer is etched with a plasma containing fluorine to expose the copper conductor structure. Next, the dual mosaic structure is cleaned with a solvent; and the dual mosaic structure is placed in a furnace tube or plasma (argon or krypton) sputtering treatment, or both, to remove the fluorine-containing I insect residue. Thing. Adding baking and bell-extinguishing treatments during the cleaning process can remove the fluorine-containing etching residues, thereby preventing insufficient adhesion between the low-k dielectric layer and the metal diffusion barrier layer to be formed next, thereby preventing its peeling 5- 4 Detailed description of the invention: The semiconductor design of the present invention can be widely applied to many semiconductor designs, and can be made using many different semiconductor materials.
472319 五、發明說明（4) 以一較佳實施例來說明本發明方法時，習知此領域的人士 應有的認知是許多的步驟可以改變，材料及雜質也可替換 ，這些一般的替換無疑地亦不脫離本發明的精神及範疇。 其次，本發明用示意圖詳細描述如下，在詳述本發明 實施例時，表示半導體結構的剖面圖在半導體製程中會不 依一般比例作局部放大以利說明，然不應以此作為有限定 的認知。此外，在實際的製作中，應包含長度、寬度及深 度的三維空間尺寸。 在此實施例中，揭露一種在雙鑲後（dual damascene) 製程中移除複數個含氟蝕刻殘留物的方法，至少包括提供 一雙鑲嵌結構，其具有一銅導體結構於其中，一覆蓋層（ c a p 1 a y e r )於銅導體結構及雙鑲嵌結構上，及一具有至少 一位於銅導體結構上方之一開口的低介電常數介電層，例 如以旋塗高分子形成之介電層，於覆蓋層上。以含有氟成 分的電漿蝕刻覆蓋層以暴露出銅導體結構。接著，以一溶 劑清洗雙鑲嵌結構；及將雙鑲嵌結構置入一爐管中或電漿 (氬或氫氣）滅鑛處理，或是兩者皆有，以移除含銳敍刻殘 留物。在清洗過程中加入烘烤及減:鐘處理可移除含H Ί虫刻 殘留物，進而防止低介電常數介電層與接著要形成的金屬 擴散阻絕層之間的黏著不足，進而防止其剝落。 在此實施例中，參照第二A圖，一半導體結構，例如472319 V. Description of the invention (4) When a preferred embodiment is used to describe the method of the present invention, those skilled in the art should recognize that many steps can be changed, and materials and impurities can be replaced. These general replacements are undoubtedly The land does not depart from the spirit and scope of the present invention. Secondly, the present invention is described in detail with a schematic diagram as follows. In the detailed description of the embodiments of the present invention, the cross-sectional view showing the semiconductor structure will not be partially enlarged according to the general scale in the semiconductor manufacturing process to facilitate the description, but it should not be used as a limited recognition. . In addition, the actual production should include three-dimensional space dimensions of length, width and depth. In this embodiment, a method for removing a plurality of fluorine-containing etching residues in a dual damascene process is disclosed, at least including providing a dual damascene structure having a copper conductor structure therein, and a cover layer. (Cap 1 ayer) on a copper conductor structure and a dual damascene structure, and a low dielectric constant dielectric layer having at least one opening above the copper conductor structure, such as a dielectric layer formed by spin-coating a polymer, on Overlay. The cover layer is etched with a plasma containing fluorine components to expose the copper conductor structure. Next, the dual mosaic structure is cleaned with a solvent; and the dual mosaic structure is placed in a furnace tube or plasma (argon or hydrogen) demineralization treatment, or both, to remove sharp residues. Adding baking and reducing during the cleaning process: the bell treatment can remove the H-containing tapeworm residue, thereby preventing insufficient adhesion between the low-dielectric constant dielectric layer and the metal diffusion barrier layer to be formed, thereby preventing its Flaking. In this embodiment, referring to the second A diagram, a semiconductor structure, such as
472319 五、發明說明（5) 一雙鑲嵌結構，包括銅導體結構1 3，一第一低介電常數介 電層10及一覆蓋層（cap layer)14先後在其上形成。此外 ，已蝕刻的第二低介電常數介電層12與第三低介電常數介 電層1 6中間亦有覆蓋層1 4，一遮罩層1 7則是用來定義出第 三低介電常數介電層1 6的蝕刻圖案。在此，所有的低介電 常數介電層有一小於2. 6的介電常數值，可以利用旋塗（ spin on)高分子形成。 本發明的關鍵步驟是移除覆蓋層1 4後洗淨的程序，為 的是移除在第二低介電常數介電層12與第三低介電常數介 電層1 6及銅導體結構1 3上的蝕刻殘留物。然而，蝕刻時使 用含氟的電漿，如二氟曱烷有許多的缺點。首先，以此電 漿蝕刻後會產生氟化高分子。這些氟化高分子會阻礙接下 來在第二低介電常數介電層12或第三低介電常數介電層16 側壁上形成的金屬擴散阻絕層（例如T a N ) ( b a r r i e r 1 a y e r ) (圖上未示）的黏著力，進而造成阻絕層的剝落。本發明中 ，雙鑲嵌結構的蝕刻後洗淨的程序在含胺有機洗劑後加上 烘烤及氬（Ar )或氫氣電漿濺鍍處理步驟。烘烤處理目的在 於蒸發殘留在結構較疏鬆的第二低介電常數介電層1 2或第 三低介電常數介電層1 6中的不純物質；烘烤處理將晶圓製 入充滿氮的爐管中，溫度約介於3 5 0°C至4 0 (TC之間。再 者，以Ar或氫氣電漿作濺鍍處理。氟化高分子亦可被Ar電 漿物理濺鍍轟撞出去，或利用氫氣與第二低介電常數介電 層1 2或第三低介電常數介電層1 6產生化學反應而移除含氟472319 V. Description of the invention (5) A double damascene structure including a copper conductor structure 13, a first low dielectric constant dielectric layer 10 and a cap layer 14 are formed thereon. In addition, the etched second low-k dielectric layer 12 and the third low-k dielectric layer 16 also have a cover layer 14 between them, and a mask layer 17 is used to define a third low-k layer. Etching pattern of the dielectric constant dielectric layer 16. Here, all the low dielectric constant dielectric layers have a dielectric constant value less than 2.6, and can be formed using spin-on polymers. The key step of the present invention is the cleaning process after removing the cover layer 14 in order to remove the second low-k dielectric layer 12 and the third low-k dielectric layer 16 and the copper conductor structure. 1 Etching residue on 3. However, the use of a fluorine-containing plasma, such as difluoromethane, for etching has many disadvantages. First, fluorinated polymers are produced after etching with this plasma. These fluorinated polymers will hinder a metal diffusion barrier layer (eg, T a N) (eg, barrier 1 ayer) formed on the side wall of the second low dielectric constant dielectric layer 12 or the third low dielectric constant dielectric layer 16. (Not shown in the figure) adhesion, which in turn causes the peeling of the barrier layer. In the present invention, the cleaning process of the double-mosaic structure after the etching is followed by the steps of baking and argon (Ar) or hydrogen plasma sputtering after the amine-containing organic detergent. The purpose of the baking process is to evaporate the impurities remaining in the second low-k dielectric layer 12 or the third low-k dielectric layer 16 with a relatively loose structure; the baking process will make the wafer filled with nitrogen. In the furnace tube, the temperature is between 350 ° C and 40 ° C. Furthermore, Ar or hydrogen plasma is used for sputtering treatment. Fluorinated polymers can also be bombarded by Ar plasma physical sputtering. Knock it out, or use hydrogen to chemically react with the second low-k dielectric layer 12 or the third low-k dielectric layer 16 to remove fluorine.
第8頁 472319 五、發明說明（6) 殘留物。 第三A圖為S i N覆蓋層蝕刻後，以含胺有機洗劑清洗雙 鑲嵌旋低介電常數介質結構後的XPS光譜圖，圖上可以顯 示含氟的圖譜，其將阻礙金屬擴散阻絕層的黏著力；另一 方面，第三B圖為以本發明蝕刻後清洗方法清洗雙鑲嵌旋 塗銅、低介電常數介質結構後的XPS光譜圖，其中含氟的 圖譜已不複見。 雖然本發明以特定介電材料、導電材料及裝置來說明 ，但熟悉多層内連接微機電的人士應有所認知，不限於上 述的特定介電材料、導電材料及裝置；凡其它未脫離本發 明所揭示之精神下所完成之等效改變或修飾，均應包含在 下述之申請專利範圍内。 再者，本發明的實施例雖然直指半導體元件的雙鑲嵌 結構，對於熟悉多層内連接微機電的人士也應有所認知， 本發明也可使用在底材封裝到内連接電路系統上；這些多 階或多層底材使用有機絕緣高分子及鋁導線等；本發明的 雙鑲嵌結構是適用到許多以導電介層連接的多層結構。Page 8 472319 V. Description of the invention (6) Residues. The third picture A is the XPS spectrum of the double-mosaic low-k dielectric material structure after cleaning the Si N cover layer with an amine-containing organic lotion. The fluorine-containing spectrum can be displayed on the diagram, which will hinder the diffusion of metal. The adhesion of the layer; on the other hand, the third graph B is the XPS spectrum of the dual damascene spin-coated copper and low-dielectric constant dielectric structure cleaned by the post-etching cleaning method of the present invention. The fluorine-containing spectrum has disappeared. Although the present invention is described with specific dielectric materials, conductive materials, and devices, those familiar with multi-layer interconnected micro-electro-mechanical systems should be aware that they are not limited to the specific dielectric materials, conductive materials, and devices described above; Equivalent changes or modifications made under the spirit of the disclosure should be included in the scope of patent application described below. Furthermore, although the embodiments of the present invention refer directly to the dual damascene structure of semiconductor elements, those who are familiar with multilayer interconnected micro-electro-mechanical systems should also be aware that the present invention can also be used to package substrates to interconnected circuit systems; these Multi-layer or multi-layer substrates use organic insulating polymers and aluminum wires. The dual-mosaic structure of the present invention is applicable to many multi-layer structures connected by conductive interlayers.
第9頁 472319 圖式簡單說明 第一圖為以傳統方法中的雙鑲嵌結構的剖面示意圖； 第二圖為以本發明方法中的雙鑲嵌結構的剖面示意圖 第三A圖為以傳統蝕刻後清洗方法清洗雙鑲嵌旋塗銅 、低介電常數介質結構後的XPS光譜示意圖；及 第三B圖為以本發明方法蝕刻後清洗方法清洗雙鑲嵌 旋塗銅、低介電常數介質結構後的XPS光譜示意圖。 主要部分之代表符號： 10 第一低介電常數介電層 12 第二低介電常數介電層 13 銅導體結構 14 覆蓋層 16 第三低介電常數介電層 17 遮罩層 110 第一低介電常數介電層 120 第二低介電常數介電層 130 銅導線結構層 140 覆蓋層Page 472319 Brief description of the diagram The first diagram is a schematic cross-sectional view of a dual damascene structure in a conventional method; the second diagram is a cross-sectional schematic view of a dual damascene structure in a method of the present invention; the third A is a conventional post-etching cleaning Methodology XPS spectrum diagram after cleaning dual damascene spin-coated copper and low dielectric constant dielectric structure; and Figure 3B is the XPS after cleaning dual damascene spin-coated copper and low dielectric constant dielectric structure using the post-etch cleaning method of the present invention Spectral diagram. Main symbols: 10 first low-k dielectric layer 12 second low-k dielectric layer 13 copper conductor structure 14 covering layer 16 third low-k dielectric layer 17 mask layer 110 first Low dielectric constant dielectric layer 120 Second low dielectric constant dielectric layer 130 Copper wire structure layer 140 Cover layer
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