TWI229393B - Fabricating method of low temperature poly-silicon film - Google Patents

Abstract

A fabricating method of low temperature poly-silicon film is described. An amorphous silicon layer is formed on a substrate, and then a laser anneal step is performed on the amorphous silicon layer for forming a poly-silicon layer from the amorphous silicon layer. Usually, mounds are formed on the surface of the polysilicon layer. A surface planarization treatment step is performed. Since the surface planarization treatment step is performed after a laser anneal step, irregularity problem caused by the mounds formed on the grain boundary can be resolved.

Description

1229393 V. Description of the invention α) Field of the invention The present invention relates to a method for manufacturing a thin film, and more particularly to a method for manufacturing a low-temperature polycrystalline silicon thin film. In the prior art, in general components, switches are required to drive the operation of the components. The switches can be thin film transistors or thin film diodes. For thin film transistors, they can be based on the channel area. The materials are divided into amorphous stone eve (am 〇rph 〇ussi 1 ic ο η, abbreviated a-S i) thin film transistor and polycrystalline stone eve (ρ ο 1 y-si 1 oc ο η) thin film transistor. Compared with amorphous silicon thin film transistors, the crystal stone thin film transistors have lower power consumption and larger electron mobility, so they have gradually received market attention. The early polycrystalline silicon thin-film transistor had a process temperature of up to 1,000 degrees Celsius, so the choice of substrate material was greatly limited. However, due to the recent development of lasers, the process temperature can be reduced to below 60 degrees Celsius, and the use of The polycrystalline silicon thin film transistor obtained by this manufacturing method is also called a low temperature poly-silicon (LTPS) thin film transistor. In the manufacturing process of the low-temperature polycrystalline silicon film transistor, a polycrystalline silicon layer is first formed on the substrate, and then the source / non-electrode region and the channel region are formed in the polycrystalline silicon layer, and then A gate insulating layer and a gate electrode are sequentially formed on the polycrystalline silicon layer. The manufacturing method of the various polycrystalline silicon layers described above is usually to first deposit an amorphous layer on a substrate, and then perform a tempering process to transform the original amorphous silicon layer into a polycrystalline silicon layer. The tempering process is, for example, Laser knot

11402twf.ptd Page 9 1229393 V. Description of the invention (2) Crystal 4 dagger (laser crystal ization), excimer laser tempering (excimer 1 asera η nea 1 ing (ELA for short), continuous lateral curing method (sequential lateral curing method) solidification (SLS for short) or solid state laser (SSL) for short. However, after the tempering process is completed, several protrusions will form on the surface of the polycrystalline silicon layer. The reason for the formation of these protrusions is that during the tempering process, the amorphous silicon layer will be rearranged, and the density of the liquid silicon is greater than Due to the density of solid silicon. A more detailed explanation is that when the amorphous silicon layer is rearranged into a polycrystalline stone layer by a tempering process, 'part of the amorphous cut will first be used as a seed for recrystallization', and then grown into larger crystals. These large crystals continue to grow, and then combine with each other to form a larger crystal. However, during the bonding process, because these silicon crystals and molten silicon (liquid silicon) have different densities from each other, some silicon crystals will push each other. Extrude onto the surface of the polycrystalline silicon layer to form protrusions. It is worth mentioning that the early tempering methods used in low-temperature polycrystalline silicon were mostly excimer laser tempering, but because the grain size formed was small (about 500 angstroms), component consumption was The power will be large, and the electron mobility is small, so the tempering process that is more commonly used recently is the continuous lateral curing method or the solid-state laser method. These two processes can form larger silicon grains (about 200 microns), but the accompanying protrusions will be larger, and the excessively large protrusions will cause the subsequent breakdown voltage of the thin-film transistor formed ( breakdown voltage) or its current will change, and even imperfections such as the breakdown of the gate insulation layer will not be yielded. Therefore, when these thin film transistors are used as the switches of the components, the operation of the components will be affected. The above question

11402twf.ptd Page 10 1229393 V. Description of the invention (3) Although the problem can be a phenomenon, it is made of a certain degree of shadow crystal silicon thin film. SUMMARY OF THE INVENTION In view of the fact that the film manufacturer has protrusions, the method of the present invention is intended to deconstruct the present invention. In the first tempering process, for example, continuous, the polycrystalline silicon planarization process is engraved and the molecular laser is formed on the layer of the amorphous silicon layer. Therefore, the low-temperature polycrystalline crystal can improve the use of excessively thick gate ring. Therefore, Cheng is concerned about this method, and another solution is to make a substrate, make the lateral layer step, before the fire place, the thickness of the silicon layer followed by the thickness of the gate insulation layer to improve the oversized insulation layer. In addition, it will cause a problem that the protrusions on the surface of the polycrystalline stone layer have a low temperature. The purpose of this report is to explain all the deficiencies of the solution. One of the purposes is to know the low-temperature form of a non-solidified surface of a component with many low temperatures. The low-temperature table forms a crystalline silicon method and a convergent medium-type surface etching step. The polycrystalline amorphous layer is provided by the chip breaking action to turn the solid into a number of planes. On the substrate, there is a problem that the surface of a low-temperature polycrystalline thin film made of polycrystalline silicon prepared by cryogenic technique. Fabrication of a silicon film The silicon layer is then changed to a polycrystalline silicon layer laser method. Of these protrusions. Following the Tannin process steps, grinding the above-mentioned manufacturing method to form a buffer stone and thin protrusions against the right, and in this, for example, the middle layer of the processing method, the polycrystalline silicon thin layer and its surface film, and the shadow of this crystal Shi Xi tempering is an electrical step. The manufacturing method of slurry etching and quasi-formation of a buffer polycrystalline silicon film in the process of layer-by-layer process can solve the problem of protrusions on the conventional surface. Current uniformity of transistor

11402twf.ptd Page 11 1229393 V. Description of the invention (4) Improve the stability of the operation of the component. In order to make the above and other objects, features, and advantages of the present invention clearer, ”Beiyi 11 ′ exemplifies a preferred embodiment, and in conjunction with the accompanying drawings, the detailed description is as follows: FIG. 1A to FIG. FIG. 1D is a schematic cross-sectional view showing a process flow of a low-temperature polycrystalline silicon thin film according to a preferred embodiment of the present invention. ^, Please refer to FIG. 1A first, a method for manufacturing a low-temperature polycrystalline silicon thin-film transistor is first & A substrate 1 Q ′ is provided, where the substrate 1 Q ′ is, for example, a glass substrate. After that, an amorphous stone layer 1 0 3 is formed on the substrate 100, and the amorphous stone layer 103 is tempered. Process i 〇1. The tempering process i 〇1 is, for example, a laser tempering process. The laser tempering process may be a sequential lateral solidification (SLS) and a solid state laser (solid state laser). laser (SSL for short). The purpose of the tempering process 101 is to re-arrange the amorphous silicon layer 103 by recrystallization to form a polycrystalline layer (not shown). During the recrystallization, Part of the amorphous silicon The crystal seed is then grown to become a larger crystal, such as polycrystalline silicon crystal 1 〇4, and the portion between polycrystalline silicon silicon crystalline 1 〇4 is a molten amorphous silicon layer 〇3 a. Please Referring to FIG. 1B, in the process of continuing the tempering process of 〇1, the density of the polycrystalline silicon crystalline silicon 〇4 and the molten amorphous silicon layer 1,0 3 a gradually growing from each other will make the crystals丨 〇4 pushes the molten amorphous silicon layer 1 〇 03 a to each other, so that the molten amorphous silicon layer 〇 03 a rises on the surface of the amorphous silicon layer 〇 03, and finally, it is to be tempered. Polycrystalline

11402twf.ptd Page 12 1229393 V. Description of the invention (5) · A protrusion 106 will be formed on the surface of the silicon layer 104a (as shown in FIG. 1C). Next, referring to FIG. 1D, the substrate 1 0 0 on which the polycrystalline silicon layer 104 is formed is subjected to a surface treatment step 108 to remove surface protrusions 106. This step is, for example, a plasma etching treatment step, Chemical wet etching process steps, oxidation-treatment and plasma etching process steps, oxidation treatment and chemical wet etching process steps, polishing process steps, or excimer laser tempering process steps, and the like. Among them, the reaction gas source of the plasma etching process step may use a gas containing fluorine or chlorine, such as SF6 and (: 12. In addition, the chemical wet etching process step may use a dilute solution of hydrogen fluoride (HF) as an etching solution. In addition, oxidation The treatment and plasma etching treatment steps are performed after the oxidation treatment, and then the plasma etching treatment step is performed. The oxidation treatment is, for example, the use of oxygen in the plasma for oxidation (〇 2 Ρ 1 asma). The step may use a gas containing fluorine or chlorine, such as SF6 and (: 12 as the reaction gas source. In addition, the oxidation treatment and the chemical wet etching step are, for example, an oxidation treatment, and then a chemical wet etching step. The oxidation treatment is, for example, oxidation using oxygen in a plasma (02 p 1 asma), and the chemical wet etching treatment step is, for example, using a dilute solution of hydrogen fluoride (HF) as an etching solution. In addition, the polishing treatment step is, for example, using Chemical mechanical grinding method to grind it. In addition, the excimer laser tempering treatment step is compared with the previous continuous side curing method. The solid-state laser method is a lower-energy laser tempering step. Therefore, using the excimer laser tempering step can make the protrusions 1 0 6 on the surface of the polycrystalline silicon layer 1 0 6 appear molten. Therefore, after the tempering process of converting amorphous silicon into polycrystalline silicon,

11402twf.ptd Page 13 1229393 V. Description of the invention (6) The surface of the low-temperature polycrystalline silicon film completed by additional surface planarization treatment steps will be relatively flat. Of course, in the above process, before forming the amorphous silicon layer 103, a buffer layer 102 may be formed on the substrate 100, and then an amorphous silicon layer may be formed on the buffer layer 102. 1 0 3. In addition, after the formation of the polycrystalline debris layer 1 0 4 a on the substrate 100, conventional techniques can be used to continue the subsequent process to form a gate insulation layer, a gate electrode, a source / drain region, a channel region, and a source. Thin film transistor (not shown) of the electrode / drain metal layer. The material of the gate insulating layer is, for example, silicon oxide or silicon nitride. A method of forming the source / drain region is, for example, doping a polycrystalline silicon layer 104a, and the doping method is, for example, an ion implantation method. Moreover, the source metal layer is electrically connected to the source region, and the drain metal layer is electrically connected to the drain region. Therefore, it can be known from the above that the process of the low-temperature polycrystalline silicon thin film of the present invention can eliminate the protrusions of the polycrystalline silicon layer grain boundaries (g r a i η b o n d a r y) through the surface planarization processing step, so that the device current characteristics can be more consistent. In addition, the surface flattening treatment step of the present invention can prevent the breakdown voltage of the thin film transistor formed later from decreasing and affecting the operation of the device. In addition, the present invention can solve the problem that the conventional protrusion may pierce the gate insulating layer without increasing the thickness of the gate insulating layer, and can also improve the current stability of the element. In addition, the present invention is applicable to any device using a polycrystalline silicon thin film transistor, especially a low temperature polycrystalline silicon thin film transistor as a switch.

11402twf.ptd Page 14 1229393 V. Description of the invention (7) Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit and scope of the present invention. However, some changes and retouching can be made, so the scope of protection of the present invention shall be determined by the scope of the appended patent application.

11402twf.ptd Page 15 1229393 Brief Description of Drawings Figures 1A to 1D are schematic cross-sectional views showing a process flow of a low-temperature polycrystalline silicon thin film according to a preferred embodiment of the present invention. The drawing does not indicate 100. The substrate 10 1: the tempering process 102: the buffer layer 103: the amorphous silicon layer 103 a: the molten amorphous silicon layer 104 · the polycrystalline silicon crystal 104a: the polycrystalline silicon layer 106: the protrusion 108: the surface is flat Chemical treatment

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Claims (1)

1229393 Scope of patent application 1. In the case of the right one and the method of making 2. The method of making the method 3. The method of making the last name 4. The method of making and the electricity 5. The method of making and the method of making the method 4. 7. Manufacturing method A method for manufacturing a low-temperature polycrystalline silicon thin film, including at least: forming an amorphous stone layer on a substrate; and performing a tempering process on the amorphous stone layer to transform the amorphous silicon layer into crystalline silicon. Layer, wherein a plurality of protrusions are formed on the surface of the polycrystalline silicon layer; the polycrystalline silicon layer is subjected to a surface planarization treatment step. The method for manufacturing a low-temperature polycrystalline silicon thin film according to item 1 of the patent application scope, wherein the surface planarization step includes performing a plasma etching step. The method for manufacturing a low-temperature polycrystalline silicon thin film according to item 1 of the patent application scope, wherein the surface planarization step includes performing a chemical wet-type step. The method for manufacturing a low-temperature polycrystalline silicon thin film according to item 1 of the scope of the patent application, wherein the surface planarization treatment step includes performing an oxidation treatment and a slurry etching treatment step. The method for manufacturing a low-temperature polycrystalline silicon thin film according to item 1 of the scope of the patent application, wherein the surface planarization step includes performing an oxidation treatment and a wet etching treatment step. The manufacturing of the low-temperature polycrystalline silicon thin film according to item 1 of the scope of the patent application, wherein the surface flattening treatment step includes performing a polishing process such as the manufacturing of the low-temperature polycrystalline silicon thin film described in the aspect of the patent application, wherein the surface is flattened. The steps include performing an excimer mine processing step. 11402twf.ptd Page 17 1229393 6. Scope of patent application 8. The method for manufacturing a low-temperature polycrystalline silicon thin film as described in item 1 of the scope of patent application, wherein the tempering process includes a laser tempering process. 9. The method for manufacturing a low-temperature polycrystalline silicon thin film as described in item 8 of the scope of the patent application, wherein the laser tempering process is selected from sequential lateral solidification (SLS) and solid state laser (solid state laser) laser (SSL for short). 10. The method for manufacturing a low-temperature polycrystalline silicon thin film according to item 1 of the scope of patent application, wherein before forming the amorphous silicon layer on the substrate, it further comprises forming a buffer layer on the substrate. 11402twf.ptd Page 18