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【發明所屬之技術領域】 特別是應用於發光 一本發明係為一種光電半導體元件 二極體之光電半導體元件。 【先前技術】 發光二極體係為目前用途最廣之光電 :途範圍包含家電產品、醫刚、交通號！：：：二其 $之儀器。目前許多開發發光二極體；心=發 良發光二極體内部之元件，使得該發光二努= 之功能或發光效果。 ^具備較突出 如中華民國專利號1〇32 69所示之「光電半導體 」，其係揭露一種輻射式發射及或接收 γ 其發射及或接收輕射之半導體晶片=匕 及ί; “載體上。該槽之内表面設計成-反射 1妾收之光線，且晶片載體為電性與熱學上 2 另半導體晶片和至少一部分晶片載體區域由封裳；二：： 印參閱第一圖係為習用之光電半導體組件之平2 2 槽4圖·亦|為^述專利之平面圖。係包括一半導體晶片1 ; 一 i接區'2。出外部連接區11及複數個相對邊凸出外部 上述專利亦產生下列之缺點： 1 ·其導線架所形成之晶片載體，為電性與埶學庄π J徑’當晶片載體接合在金屬散熱器上，會有漏…同 電危險。 顺[Technical field to which the invention belongs] In particular, it is applied to light emission. The present invention is a photoelectric semiconductor element that is a photovoltaic semiconductor element. [Previous technology] The light-emitting diode system is currently the most widely used optoelectronics: the range includes home appliances, medical doctors, traffic numbers! ::: Two of its instruments. At present, many light-emitting diodes have been developed; the heart = the internal components of the light-emitting diode, so that the light-emitting diode = function or light-emitting effect. ^ It has a more prominent "optoelectronic semiconductor" as shown in the Republic of China Patent No. 1032 69, which exposes a radiation-emitting and / or receiving semiconductor chip that emits and / or receives light-emitting = daggers and "; on the carrier The inner surface of the groove is designed to reflect 1% of the light received, and the wafer carrier is electrically and thermally. 2 The semiconductor wafer and at least a part of the wafer carrier area are sealed by the skirt; 2: Please refer to the first picture for printing. Photoelectric semiconductor module flat 2 2 slot 4 figure. It is also a plan view of the patent mentioned above. It includes a semiconductor wafer 1; an i-connection region '2. The external connection region 11 and a plurality of opposite sides protrude outside the above patent. The following disadvantages also occur: 1 · The wafer carrier formed by its lead frame is electrically conductive and has a diameter of π J diameter. When the wafer carrier is bonded to a metal heat sink, there is a risk of leakage ... Same as electricity.
第5頁 五、發明說明（2) 2·其連接件為單一件， 供驅動電壓相同之發光— σ /、晶片載體，僅能提 J ι知尤一極體並聯使用。 係為一種 獨立晶片 ;複數個 一導線架 片為焦點 係用部分 係將該第 片為焦點 為多層結 的電性， 器上，不 獨立件， 使用。 光電半導 載體，該 半導體晶 環狀曲面 所形成者 導線架所 一導線架 所形成者 構’其中 將電性與 會有漏電 可提供多 體元件 些獨立 片，係 ，該環 ;複數 形成者 環狀曲 。本發 間層為 熱學途 危險。 個驅動 數個導線 固定於該 獨立晶片 部分導線 件，該些 狀曲面， 體圍繞， 片載體為 以隔離晶 ，當接合 設計之連 之發光二 【發明内容 本發明 架；複數個 些導線架上 載體上；第 架以該些晶 獨立連接件 該環狀曲面 且以該些晶 獨立件，且 片與導線架 在金屬散熱 接件為多個 極體串並聯 ’係包括複 晶片載體係 固定於該些 狀曲面係用 個獨立連接 ，·及第二環 面由一封裝 明設計之晶 絕緣體，可 徑分隔開來 並且本發明 電壓不相同 【實施方式】 的所it Π::查委員能更進一步瞭解本發明為達成定 技術、手段及功效，請來閱以Τ i @ 砰細說明與附圔^ y L . 月多阅以下有關本發明 由此得一、、菜入曰目相仏本發明之目#、特徵與特點，當 說明用，並非i ί體之瞭解 '然而所附圖式僅提供參考 、’非用來對本發明加以限制者。 1227935 五、發明說明（3) 為了詳述本發明之最佳 第三圖，第二圖係為 而第三圖係為第二圖 電半導體元件係包括 獨立晶片載體上；複 載體係固定於該些導 紗構，其中該獨立曰曰曰 =路以導通該些半導 艨（A圖示）’係 1，其中該獨立晶片 ^ 第〆導線架環狀 ^此晶片為焦點所 >乂該& 本發明 之線3 - 複數個 數個獨 線架上 片載體 體晶片 用以隔 載體之 曲面10 形成者 t冶係塗佈可增強反射之 曲面係政 & 该唆獨立連接件 <為一拋物曲面或一 1 4 a速换件，其部份 齋1生接點，另一 係用部 位於該 部份突 者 實施例’請同時參閱第二圖及 之光電半導體元件之平面圖， 3所不之剖面圖。本發明之光 半導體晶片6，係固定於該此 立晶片載體8，該些獨立晶片 ’該些獨立晶片載體係為多層 之上表層為導體’且形成電路 ’該獨立晶片載體之中間層為 離該半導體晶片與該些導& 下表層係可為導體或絕緣體。 ，該環狀曲面係用部分導線架 ，該第一導線架環狀曲面之曲 =料其中該第一導線架環& 分導後加#複數個獨立連接件 :線木所形成者，其 屮兮^ 做為該些半導體曰 出该封裝髀 ^艰晶 體’用以連接外部電 狀曲面係將 且以該些曰二第一導線架環狀 曲面之曲:f為焦點所形成 射之材料，▲面係可由向反射 面，該第二ί第二環狀曲面係 窗口 20，；：狀曲面之曲面為 μ囱D係由該第 環狀曲面1 8 該環 由〆封裴體1 6所圍繞， ，其中該第二導線架環狀 增強反 橢圓曲 穿透之 第 成或塗佈可 樹物曲面或一 町為 /光潰面；一光線可Page 5 V. Description of the invention (2) 2. The connection piece is a single piece for the same driving voltage of light emission-σ /, chip carrier, can only be used in parallel. It is a kind of independent chip; a plurality of lead frames are used as the focus. The used parts are used to focus the first piece as a multilayer junction. Photoelectric semiconducting carrier, the semiconductor crystal ring-shaped curved surface formed by the lead frame formed by a lead frame formed by the structure of the lead frame, which will provide electrical and leakage, can provide multi-body components, independent pieces, systems, the ring; plural formed ring Shaped. The hair layer is thermally dangerous. A plurality of wires are driven to be fixed to a part of the wire pieces of the independent chip, the curved surfaces are surrounded by the body, and the chip carrier is an isolated crystal, which is connected when the design is connected. [Summary of the invention; a plurality of lead frames On the carrier; the first frame uses the crystal independent connecting pieces, the annular curved surface and the crystal independent pieces, and the sheet and the lead frame are connected in series and in parallel with a plurality of polar bodies on the metal heat dissipation connector; These curved surfaces are independently connected, and the second torus is formed by a crystal insulator with a package design, which can be separated by diameter and the voltage of the present invention is not the same. [Embodiment] It Π :: 查 委 能For further understanding of the present invention, in order to achieve certain techniques, methods and effects, please read the detailed description and attached ^ y L. Read more about the present invention to get a better understanding of the present invention. The purpose of the present invention #, features and characteristics, when used for illustration, is not an understanding of the body. However, the drawings are provided for reference only, and are not intended to limit the present invention. 1227935 V. Description of the invention (3) In order to describe the best third drawing of the present invention, the second drawing is the third drawing and the third drawing is the second drawing. The semiconductor device system includes an independent wafer carrier; the complex carrier is fixed on the carrier. Some guide yarn structures, where the independent day is said to pass through the semiconducting wires (A picture) 'system 1, where the independent wafer ^ the first lead frame ring ^ this wafer is the focus of the > & Line 3 of the invention-a plurality of single wire racks on the carrier body wafer to separate the curved surface of the carrier 10 maker t coating system to enhance the curved surface system & the independent connector < It is a parabolic curved surface or a 1 4a speed-changing part, some of which are fast contacts, and the other parts are located in the part of the embodiment. Please refer to the second figure and the plan view of the optoelectronic semiconductor element. Section 3 section. The optical semiconductor wafer 6 of the present invention is fixed to the vertical wafer carrier 8. The independent wafers 'the independent wafer carriers are multiple layers and the surface layer is a conductor' and the circuit is formed. The semiconductor wafer and the underlying layers may be conductors or insulators. The looped curved surface uses a part of the lead frame. The curvature of the looped curved surface of the first lead frame is equal to the number of the first lead frame ring & the number of independent connectors after the shunting.屮 半导体 As the semiconductors, the package 髀 ^ crystal is used to connect the external electrical curved surface system and the curved surfaces of the first lead frame ring curved surfaces: f as the focal material. The surface can be a reflective surface, the second second second curved surface system window 20 ;: the curved surface is a μ-shaped D system composed of the second circular surface 1 8 and the ring is enclosed by the seal body 6 Surrounded by, where the second lead frame ring-shaped enhanced anti-elliptic penetration penetrates or coats the surface of the tree or the surface of a light or light; a light may
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狀曲面與該第二環狀曲面連接所形成者，其中該窗口内係 内置有a亥些半導體晶片與該些獨立晶片載體；一透明之光 學元件2 2 ’該光學元件係可蓋上該光線可穿透之窗口，其 中該光學元件係可為一凸面鏡、一平面鏡或四面鏡。 本發明設計之晶片載體為獨立件，且為多層結構，其 中間層為絕緣體，可以隔離晶片與導線架的電性，將電性A shape formed by connecting the curved surface and the second annular curved surface, in which the semiconductor wafers and the independent wafer carriers are built in the window; a transparent optical element 2 2 'The optical element can cover the light A penetrable window, wherein the optical element may be a convex mirror, a flat mirror, or a four-sided mirror. The wafer carrier designed by the present invention is an independent piece and has a multi-layer structure, and the intermediate layer is an insulator, which can isolate the electrical properties of the chip and the lead frame,
與熱學迷徑分隔開來’當接合在金屬散熱器上，不會有漏 電危險。 W 並且本發明設計之連接件為多個獨立件，可提供多個 驅動電壓不相同之發光二極體串並聯使用。 ^對於本發明所設計之反射面係由多曲面合成者，曲面 係可為抛物曲面或橢圓曲面，且以發光二極體晶片為其焦 點，可以有效將光線反射至正面方向。 八Μ 職是’本發明確能藉上 然不同於習知者的設計，堪 申請前未見於刊物或公開使 件，爰依法提出發明專利申 惟，上述所揭露之圖式 而已，凡精于此項技藝者當 之改良，而這些改變仍屬於 定之專利範圍中。 述所揭露之技術，提供一種週 能提高整體之使用價值，又其 用，誠已符合發明專利之要 請。 、說明，僅為本發明之實施例 可依據上述之說明作其他種種 本發明之發明精神及以下所界Separated from the thermal path, when connected to a metal radiator, there is no danger of leakage. W And the connecting piece designed by the present invention is a plurality of independent pieces, which can provide multiple light emitting diodes with different driving voltages in series and parallel use. ^ For the reflective surface designed by the present invention, the surface is composed of multiple curved surfaces. The curved surface can be a parabolic surface or an elliptical surface, and the light emitting diode chip is used as the focal point, which can effectively reflect light to the front direction. The eighth job is that the present invention can indeed borrow a design that is different from those of the knowers. It can not be seen in publications or public couriers before the application, and filed for an invention patent application according to law. Only the schemes disclosed above are good at This artisan is considered to be an improvement, and these changes are still within the scope of the fixed patent. The disclosed technology provides a way to improve the overall use value, and its use, which has been in line with the requirements of invention patents. The description is only an embodiment of the present invention. Various other aspects can be made according to the above description.
1227935 圖式簡單說明 圖 式 簡 單 說 明 ] 第 一 圖 係 為 習 用 之 光 電半導體組件之平面圖； 第 二 圖 係 為 本 發 明 之 光電半導體元件之平面圖； :及 第 二 圖 係 為 第 二 圖 之 線3 -3所 示之剖面圖。 圖 式 中 之 參 昭 號 數 ] 半 導 體 晶 片 1 槽 4 複 數 個 半 導 體 晶 片 6 複數個獨立晶片 載體 8 第 一 導 線 架 環 狀 曲 面 10 複 數 個 凸 出 外 部 連 接 區 11 相 對 邊 凸 出 外 部 連 接 區 12 複數個獨立連接 件 14 封 裝 體 16 第二環狀曲面 18 窗 Π 20 光學元件 221227935 Schematic illustrations Schematic illustrations] The first diagram is a plan view of a conventional optoelectronic semiconductor component; the second diagram is a plan view of an optoelectronic semiconductor component of the present invention; and the second diagram is a line 3 of the second diagram -3 cross section. Reference number in the drawing] Semiconductor wafer 1 Slot 4 Multiple semiconductor wafers 6 Multiple independent wafer carriers 8 First lead frame ring-shaped curved surface 10 Multiple convex external connection areas 11 Opposite sides convex external connection areas 12 Multiple Independent connectors 14 package 16 second annular curved surface 18 window Π 20 optical element 22