TWI227547B - Method of fabricating a flash memory cell - Google Patents

Abstract

A method of fabricating a memory cell is described. The method includes providing a substrate; forming a patterned mask layer on the substrate; etching the substrate by using the patterned mask layer as a mask to form a trench; forming a first dielectric layer on the substrate; forming a first gate and a second gate on the sidewalls of the trench; forming a first source/drain region in the substrate under the trench; forming a second dielectric layer on the substrate; forming a passivation layer on the second dielectric layer; removing partial of the passivation layer, the second dielectric layer and the first dielectric layer to expose the surface of the substrate at the bottom of the trench; forming a third gate completely filled in the trench; removing the mask layer; forming a third dielectric layer on the substrate; forming a fourth gate and a fifth gate on the sidewalls of the first gate and the second gate; forming a second source/drain region in the substrate beside the side of the fourth gate and the fifth gate.

Description

1227547 V. Description of the invention (1) [Technical field to which the invention belongs _ The present invention relates to a semiconductor device and a manufacturing method, and more particularly to a flash memory cell and a manufacturing method thereof ^. [Previous technology] Because the flash memory element can be repeatedly accessed, erased, etc., and the stored data will not be read after power off =, read ^ Therefore, it has become a personal computer and electrical 4 excellent non-volatile memory elements. A typical flash memory device used is made of doped polycrystalline silicon (Floating Gate) and control gate (construct gate) (ground structure). And 〇, the floating gate and the control gate are separated by a gate ^ ^ = poles' and the floating gate and the substrate are separated by a tunnel oxide layer (Tunnel 0 X ide). The flash memory is used to write data because of controlling the gate; the bias voltage is applied to the source / drain region to inject electrons into the floating gate. When reading the data in the flash memory, the working voltage is applied to the control gate. At this time, the charged state of the floating gate will affect the on / off of its lower channel (Channel), and the on / off of this channel The relationship is based on the interpretation data value "0" or "1". When flash memory is erasing data (Erase), 'the relative potential of the substrate, source region, drain region, or control gate is increased' to use the tunneling effect to pass electrons through the floating gate Tunneling oxide layer (Tunnel ing χ ide) and discharged into the substrate or drain (source) (ie

Substrate Erase or Drain (Source) Side Erase), or pass through the inter-gate dielectric layer and drain into the control gate.

12129twf.ptd Page 7 1227547 V. Explanation of the invention (2) In the absence of erasing the data in the flash memory, because the amount of electrons discharged from the floating gate is not easy to control, it is easy to cause the floating gate to be discharged. Too many electrons with positive charge 9 This phenomenon is called over-erase (Ove r-Eras e). 〇 When this over-erase is too severe, the channel under the floating gate will not be applied to the control gate. At the working voltage, the state of continuous conduction is caused and the data is misjudged. Therefore, in order to solve the problem of excessive erasing of components, many flash memories will use a split gate (S p 1 it Ga te) design. In addition to the control gate and floating gate, its structural features also have a selection gate (or erase gate) located above the base of the side wall of the control gate and floating gate. 〇 Among them, this selection gate and control The gate floating gate and the substrate are separated by another inter-gate dielectric layer. So when the over-erase phenomenon is too serious, that is, the channel under the floating gate is under the state where the control gate is not applied with operating voltage That is, when the conducting state is selected, the channel under the selected gate can still remain closed. That is, the closed state of the selected gate will make the drain region and the source region appear non-conducting. This can prevent misjudgment of data. The separation gate structure requires a larger separation gate area and a larger memory cell size, so its memory cell size is larger than that of a stacked gate memory cell J There is a problem that the so-called inability to increase the component integration degree. In addition, since the device performance of the flash memory is related to the gate coupling ratio between the floating gate and the control gate (Ga te Couple Rat i 〇 > GCR) 丨And this gate coupling rate is related to the area between the control gate and the floating gate. Therefore J is the area sandwiched between the control gate and the floating gate

12129twf.ptd Page 8 1227547

ί ί The higher the gate closing rate, the better the component performance. However, as the accumulation of widows increases, it is becoming increasingly difficult to increase the area between the control gate and the floating gate. ❿ 明 Referring to Fig.1, the figure shows the structure of the flash memory cell disclosed in U.S. Patent No. 6,13,453. As shown in the figure, in order to increase the element accumulation, the cell line is formed in a trench on a silicon substrate 20. The memory cell line consists of two fixed vertical floating gates 3 1 a, 3 丨 b, bit lines 3 2, gap walls 2 5, drain regions 2 7, source regions 2 8, and a silicon oxide cap layer. 2 4 and control gate (character line) 3 3 are formed. Next, please refer to FIG. 2A to FIG. 2D, which show the manufacturing process of the flash memory cell disclosed in the US patent “6,130,45.3”. First, please refer to FIG. 2A to provide the substrate 20, And a patterned thick gate oxide layer 21 and a silicon nitride dielectric layer 23 have been formed on the substrate 20 to expose the trench 40 in the substrate 20. Then, a thin layer is formed on the surface of the trench 40. The gate oxide layer 22. Then, a polycrystalline silicon layer 31 is filled in the trench 40. Then, referring to FIG. 2B, a source region is formed in the substrate 20 on both sides of the gate structure (that is, the trench 40). 2 8. Next, carry out reactive ion etching (RIE) to form floating gates 31a and 3ib on the side wall of the trench 40 and form the trench 42. After that, please refer to FIG. 2C to deposit a silicon nitride layer 25 Then, please refer to FIG. 2D, after the silicon nitride layer 25 is oxidized and etched to form a silicon nitride spacer 25a, a drain region 27 is formed in the substrate 20 at the bottom of the trench 42. Following this, the trench Polycrystalline stone layer is filled in 4 2 to form bit line 3 2. Among them, floating gates 3 1 a, 3 1 b and bit line 3 2 are formed. The gap

1227547 V. Description of the invention (4) The wall 25a is formed on the bit line 3 2 after the floating gates 3 1 a and 3 1 b are formed according to the contents disclosed in the US patent US 6, 1 3 0, 4 53. Before, a dielectric layer, such as a silicon nitride layer 25, must be deposited first, and then an oxidation process is performed, and the dielectric layer at the bottom 20 is removed by reactive ion etching to expose the substrate 20 at the bottom. However, in the process of removing the bottom dielectric layer, a part of the dielectric layer on the side wall is also removed, thereby causing damage to the dielectric layer on the side wall and affecting the performance of the memory cell. [Summary of the Invention] In view of this, the object of the present invention is to provide a method for manufacturing a flash memory cell, so as to avoid problems that affect the performance of the memory cell due to damage to the dielectric layer during the manufacturing process. The invention provides a method for manufacturing a flash memory cell. This method first provides a substrate. Then, a patterned mask layer is formed on the substrate. Then, the patterned mask layer is used as a mask to etch the substrate to form a trench in the substrate. After that, a first dielectric layer is formed on the substrate. Then, a first gate and a second gate are formed on each of the two sidewalls of the trench, and the first gate and the second gate are separated by a distance, and a first dielectric layer at the bottom of the trench is exposed. A first source / drain region is then formed in the substrate at the bottom of the trench. Then, a second dielectric layer is formed on the substrate. After that, a protective layer is formed on the second dielectric layer. The material of the protective layer is, for example, a semiconductor material or a conductive material. Then, a part of the protective layer, the second dielectric layer and the first dielectric layer are removed to expose the substrate surface at the bottom of the trench. Then, a third gate is formed on the substrate to fill the trench. Then, the mask layer is removed. After the base

12129twf.ptd Page 10 1227547 V. Description of the invention (5) A third dielectric layer is formed. Then, corresponding fourth and fifth gates are formed on the sidewalls of the first and second gates. Then, a second source / drain region is formed in the substrate on the side of the fourth gate and the fifth gate. Because after the second dielectric layer is formed in the present invention, an undoped polycrystalline silicon protective layer is formed to cover the second dielectric layer. Therefore, when a subsequent removal step (etching process) is performed to expose the substrate at the bottom of the trench, this protective layer can protect the second dielectric layer to prevent the second dielectric layer from being damaged during the process. ). Therefore, the flash memory can have better data maintenance characteristics. The present invention proposes another method for manufacturing a flash memory cell. This method first provides a substrate on which a liner layer and a curtain layer having an opening are formed, and a trench formed in the substrate at the opening. After that, a tunnel oxide layer is formed on the surface of the trench. Then, after the conductor layer is filled in the trench, an etch-back step is performed so that the top of the conductor layer is higher than the surface of the lining layer and lower than the surface of the cover layer. Then, a pair of gap walls are formed on the side walls of the trench and cover part of the conductor layer. Then, using the pair of the partition wall and the mask layer as an etching mask, a part of the conductor layer is removed to form a first floating gate and a second floating gate on the side wall of the trench. Thereafter, a first source / drain region is formed in a substrate at the bottom of the trench. Next, a first inter-gate dielectric layer is formed on the substrate and the surface of the trench. Then, a protective layer is formed on the first inter-gate dielectric layer. The material of the protective layer is, for example, a semiconductor material or a conductive material. Then, a part of the protective layer, the first inter-gate dielectric layer and the tunneling oxide layer are removed to expose the substrate surface at the bottom of the trench. After that, a control gate filling the trench is formed on the substrate, and the top of the control gate is higher than the first floating gate and the first gate.

12129twf.ptd Page 11 1227547 V. Description of the invention (6) The top of two floating gates. Then, the liner and the cover layer are removed. Then, a second inter-gate dielectric layer is formed on the substrate. Then, the corresponding first selection gate and second selection gate are formed on the gap wall, the sidewall of the first floating gate and the second floating gate. Thereafter, a second source / drain region is formed in the substrate on the sides of the first selection gate and the second selection gate. After the first inter-gate dielectric layer is formed in the present invention, an un-doped polycrystalline silicon protective layer is formed to cover the first inter-gate dielectric layer. Therefore, when the subsequent removal step (etching process) is performed to expose the substrate at the bottom of the trench, this protective layer can protect the first inter-gate dielectric layer from being suffered during the process. To damage. Therefore, the flash memory can have better data maintaining characteristics. In addition, since the first floating gate (or the second floating gate) and the control gate of the present invention are formed in the trench of the substrate, the size of the memory cell can be reduced, and the degree of integration of the components can be increased. Moreover, the area sandwiched between the first floating gate (or the second floating gate) and the control gate is related to the trench depth, so each trench can be increased by forming deeper trenches in the process. The area clamped. As a result, the gate coupling rate can be improved, thereby further improving the operating speed and component efficiency of the device. In addition, the length of the channel region of the memory cell of the present invention is also related to the trench depth. Therefore, a deeper trench can be formed in the process to avoid the first source / drain region and the second source electrode. The problem of abnormal Punch Through between the poles. In addition, by using the manufacturing method of the present invention, two memory cells of the same gate can be shared and controlled simultaneously. That is, the first floating gate, the first

12129twf.ptd Page 12 1227547 V. Description of the invention (7) $ Selection: The pole and the control gate system constitute a memory cell, and the first choice and the control gate system constitute another memory. Save the process without inventing the process, and the cost of the process can be reduced to make the above and other purposes of the present invention particularly distasteful. ΠΓ 七 I Α 1 ^ and advantages can be made clearer. The best embodiment, combined with the trap, will be described in detail as follows: σ The drawings are shown as [embodiment], referring to Figures 3A to 3J, the figure shows a preferred embodiment of the present invention Flow chart of the manufacturing method of flash memory cell. : First, please refer to FIG. 3A to provide a substrate 300. This substrate 300 has formed an element isolation structure. The element isolation structure is arranged in a stripe shape and has an active area. The method for forming the element isolation structure is, for example, a Local Oxidation (LOCOS) method or a shallow trench isolation method (Uhallow Trench Isolation, STI). Next, a thicker dielectric layer 3 is formed on the surface of the substrate 300. 1. The material of the $ electric layer 301 is, for example, silicon oxide, and the formation method thereof is, for example, Chemical Vapor Deposition (CVD). In addition, in another preferred embodiment, a thinner liner (not shown) can also be formed on the surface of the substrate 3000, and the formation method is, for example, a thermal oxidation method. Then, a patterned mask layer 3 04 is formed on the dielectric layer 3 01. The material of the patterned mask layer 3 04 is, for example, silicon nitride, and the method of forming the patterned mask layer is, for example, first using a chemical vapor phase. The deposition method deposits a layer of mask material, and then forms a lithographic etching process. Followed by a patterned cover layer 3 0 4

Mil Mi 12129twf.pt (j page 13 1227547 V. Description of the invention ⑻ is a mask of the face 300, so as to form a trench 306 in the substrate 300. The channel 30 6 is formed on the substrate 3 0 0 The first dielectric layer, for example, is formed on a trench substrate such as a through oxide layer 308. Among them, the through oxide layer 308 is a silicon oxide, and the formation method is, for example, a thermal oxidation method The connection layer is filled with a conductive layer 31 in 306. Among them, the material washing method of the conductive layer 310 is heterogeneous polycrystalline stone, and the formation method is, for example, using a chemical vapor phase to form a layer. After the impurity polysilicon layer is pushed in, the ion implantation step is performed. After the layer 3 1 /, the conductor on the surface of the mask layer 304 is removed by referring to the second figure, and then the conductive layer 310 a is formed. The removal method includes etch back step shadows. J = strict chemical mechanical polishing is completed. Then, 'micro 307, 俥 (patterning process), forming a trench in the conductive layer 310a. H Into two floating gate electrodes 314 & and 3141), and the step of implanting ί ions is shown in FIG. Bottom_ / take the first-source / drain region 316, as shown in Figure 3D. Layer, ΞΞ 如? A second dielectric is formed on the substrate 3 ° according to FIG. 3E; for example, a V dielectric layer 318 is used. Among them, the material of the interlayer dielectric layer 318 is, for example, tick silicon / silicon nitride / silicon oxide. Next, a protection layer q 9 Λ ^ is formed on the inter-gate dielectric layer 3 1 8. The material of the J layer 320 includes a semiconductor material or a conductive material. The polycrystalline stone is doped, and the formation method is, for example, that the thickness of J 疋 is not about 100 angstroms. Porous phase deposition method. In addition, please refer to FIG. 3F, remove part of the inter-gate dielectric layer 318 and the protective layer 32G, and expose the base layer 1230twf. ptd Page 14 1227547 V. Description of the invention (9) The surface of the bottom 300 and the inter-gate dielectric layer 318a and the protective layer 32〇a are formed. The 'removed-method' includes an anisotropic etching process (eg, a dry I 'etching process). It is worth mentioning that because the inter-gate dielectric layer 318 is covered with a protective layer 3 2 0, during this removal step (etching process), the inter-gate dielectric layer 3 1 8 can be prevented from being subjected to the etching process. Damage while maintaining its original effectiveness. Then, a control gate electrode 3 2 2 is formed on the substrate 300 to fill the trench 3 07, as shown in FIG. 3G. The material of the control gate electrode 3 2 2 is, for example, doped polycrystalline stone. After that, please refer to Figure 3 and remove the cover layer 304. It is worth mentioning that 'if a lining layer was previously formed on the substrate 300 in Fig. 3A, the mask layer 304 and the lining layer are removed together in this step. Next, a third dielectric layer is formed to cover the entire surface of the structure, which is, for example, an inter-gate dielectric layer 325. Among them, the material of the inter-gate dielectric layer 325 is, for example, stone oxide. Then, a conductor layer 3 3 0 is formed on the inter-gate dielectric layer 3 2 5. In this embodiment, the 'conductor layer 3 3 0 is composed of a doped polycrystalline silicon layer 326, for example. In another preferred embodiment, the conductive layer 3 3 0 is composed of, for example, a doped polycrystalline silicon layer and a petrified metal layer. Next, referring to FIG. 3I, a gap wall 32 is formed on the side walls of the floating gate electrode 314a and the floating gate electrode 3 丨 4b. After that, please refer to FIG. 3J, and use the gap wall 33 2 as a self-aligning conductor layer 3 3 0 of the 'removed portion' of the mask to form a selection on the side walls of the floating gate 3 14a and the floating gate 3 14b. Gate 334a and selection gate 334b. The method for removing the conductive layer 330 is, for example, an anisotropic etching process. Next, the substrates on the sides of the selection gate 3 3 4a and the selection gate 3 3 4b

12129twf.ptd Page 15 1227547 V. Description of the invention (10) 300 forms a second source / drain region 336, and completes the production of two memory cells sharing the same control gate 3 2 2. The method for forming the second source / drain region 3 3 6 is, for example, an ion implantation process. In the above embodiment of the present invention, after the inter-gate dielectric layer 3 1 8 is formed, an undoped polycrystalline silicon protective layer 3 2 0 is formed to cover the inter-gate dielectric layer 3 1 8. Therefore, when the subsequent removal step (etching process) is performed to expose the substrate 300 at the bottom of the trench 307, the protective layer 32 can protect the inter-gate dielectric layer 3 1 8 to avoid the inter-gate dielectric. The electrical layer 3 1 8 was damaged during the manufacturing process. Therefore, the flash memory can have better data maintaining characteristics. In addition, for the control gate 322, the formed non-doped polycrystalline silicon protective layer 3 2 0 can be used as a buffer for the interface between the gate dielectric layer 3 and the control gate 322. In addition, the protective layer 320 is made of the same material as the control gate electrode 3 2 2, so the two can be combined into the same gate electrode without being removed separately. Please refer to FIG. 4A to FIG. 4G, which show a flowchart of a method for manufacturing a flash memory cell according to another preferred embodiment of the present invention. First, referring to FIG. 4A, a substrate 400 is provided. This substrate 400 has formed at least one element isolation structure. The element isolation structure is a stripe layout, and an active area is defined. Among them, the formation method of the element isolation structure is, for example, a region oxidation method or a shallow trench isolation method. Next, a lining layer 40 is formed on the surface of the substrate 400. The material of the lining layer 40 is, for example, silicon oxide, and the formation method is, for example, a thermal oxidation method. In addition, in another preferred embodiment, a thick dielectric layer (not shown) can also be formed on the surface of the substrate 400, and the formation method is, for example, chemical vapor deposition

1227547 V. Description of Invention (11). Then, a mask layer 40 is formed on the liner layer 402. The material of the mask layer 400 is, for example, silicon nitride, and the formation method is, for example, a chemical vapor deposition method. Subsequently, the mask layer 404, the liner layer 402, and the substrate 400 are patterned to form a trench 406 in the substrate 400. Thereafter, a tunnel oxide layer 408 is formed on the surface of the trench 406. The material of the tunneling oxide layer 408 is, for example, silicon oxide, and the formation method is, for example, a thermal oxidation method. Next, a conductive layer 410 is filled in the trench 406. The material of the conductor layer 410 is, for example, doped polycrystalline silicon, and the formation method is, for example, forming an undoped polycrystalline silicon layer by a chemical vapor deposition method, and then performing an ion implantation step to form it. Then, please refer to FIG. 4B, perform an etch-back step, and etch a part of the conductor layer 410, leaving the conductor layer 410a in the trench 406, so that the top of the conductor layer 410a is higher than the surface of the liner 402 and lower than The surface of the cover layer 40. Next, a spacer 412 is formed on the side wall of the trench 406, and covers a part of the upper surface of the conductive layer 410a. The material of the spacer 412 is, for example, a material having a different etching selectivity from the conductive layer 4 1 a. The method for forming the partition wall 4 丨 2 is, for example, forming an insulating material layer (not shown), and then forming the insulating material layer by dividing the insulating material layer using an anisotropic method. After that, referring to FIG. 4C, the mask layer 40 and the spacer 412 are used as an etching mask, and then a part of the conductor layer 4i0a is removed to form a side wall of the trench 406 = the gate 41 "And the floating gate 4141). Π is' free from the formation of the first source / nano in the substrate 40 0 at the bottom of the J chip canal 406. I hope / neutral, the first source / non-electron region 416 The formation method is, for example, an ion implantation process.

12129twf.ptd Page 17 1227547 V. Description of the invention (12) Then, please call Rizha @ dh @ 成 闸 Inter dielectric layer * center on the substrate 400 and the surface of the trench 406 to form silicon / silicon nitride / oxide Example of the material of Shi Xiyu's interlayer dielectric layer 4 1_ If the oxygen protective layer 4 is composed of doped polycrystalline silicon between the gate and the gate, the pot step is formed into a square material or a conductive material, which is not formed, for example. ^ The second formation method is, for example, a chemical vapor deposition method, and the pretreatment degree is, for example, about 100 angstroms. The gate, Zhan 2 refers to item 4E, and removes the part of the oxide layer 408, = 0, and the protective layer 420 to expose the base of the bottom of the trench 406. An inter-gate dielectric layer 418a and a protective layer 420a are formed. The method of making shoes includes a non-isotropic money engraving process (for example: dry-type surname engraved *), because the gate dielectric layer 418 is covered with a dull layer 4 2 0, so it is removed here In the step (etching process), the inter-gate dielectric layer 418 can be damaged by the etching process, and the original performance can be maintained. Then, a control gate 4 2 6 is formed on the substrate 4 0 to fill the trench 4 0 6. The top of the control gate 4 2 2 is higher than the tops of the floating gate 4 4a and the floating gate 4 14b. The material of the control gate 422 is, for example, doped polycrystalline silicon. In other words, a cap layer 4 2 4 is formed to fill the trench 4 0 6 and cover the control gate 422. After that, please refer to FIG. 4F and remove the liner 4 2 and the cover 4 0. It is worthwhile It is mentioned that if a thicker dielectric layer was previously formed on the substrate 400 in FIG. 4A and FIG. T, in this step, it is only necessary to remove the mask layer 400. ^ On the substrate 400 Forms covering the substrate 400 and the surface structure of the substrate 400

1227547___ V. Description of the invention (13) Inter-gate dielectric layer 4 2 5. The material of the inter-gate dielectric layer 4 2 5 is, for example, oxidized stone. Then, a conductive layer 4 3 0 is formed on the inter-gate dielectric layer 4 2 5. In this embodiment, the conductive layer 4 3 0 is composed of a doped polycrystalline silicon layer 4 2 6 or a doped polycrystalline silicon layer 4 2 6 and a silicided metal layer 4 2 8. Next, after forming the gap wall 4 3 2 0 on the side walls of the gap wall 412, the floating gate electrode 4 14a, and the floating gate electrode 41 4b, 'refer to FIG. 4G, and use the gap wall 4 32 as a self-aligning mask' The conductor layer 4 3 0 (doped polycrystalline silicon layer 4 2 6 and silicide metal layer 42 8) is removed to form a selective gate on the sidewalls of the spacer 412, the floating gate 41 乜, and the floating gate 41. 434a and selection gate 434b. The removal method of the conductive layer 430 is, for example, an anisotropic etching process. Then, the source / drain region 436 is formed on the substrates on the sides of the selection gate 43 and the selection gate 434b, and the production of the shared co-control gate memory cell is completed. Among them, the second source / drain region The method of forming 436 is, for example, an ion implantation process. In addition, in another embodiment, μ 1 ^ iS Μ 乂 good embodiment 'is further included in the selection of the gate 434a to replace the side wall to form another gap (not shown) (Shown) to facilitate the LDD process, or Doped Drain, referred to as the window process of the present invention. After 418, an embodiment is formed because the inter-gate dielectric layer dielectric layer 418 is formed. Therefore: ^ The doped polycrystalline silicon protective layer 420 covers the gate to make the bottom of the trench 4 0 6 ^ In the subsequent removal step (etching process), when the bottom is exposed, the protective layer 4 2 0 can protect

! 227547 ~ ^^ ----------- V. Description of the invention (14) Protect the inter-gate dielectric layer 4 1 8 to avoid the inter-gate dielectric layer 4 1 8 from being suffered during the manufacturing process. damage. Therefore, the flash memory can have better data maintenance characteristics. In addition, for the control gate 4 2 2, the formed undoped polycrystalline silicon protective layer 4 2 0 can be used as a buffer for the interface between the gate dielectric layer 4 1 8 and the control gate 4 2 2. The protective layer 4 2 0 is made of the same material as the control gate 4 2 2, so the two can be combined into the same gate without being removed separately. In addition, since the floating gate and the control gate of the present invention are formed in the trench of the substrate, the size of the memory cell can be reduced, and the integration degree of the components can be increased. Moreover, the area sandwiched between the floating gate and the control gate is related to the depth of the trench, so the deeper trenches can be formed in the process to increase the area sandwiched between each other. As a result, the gate coupling rate can be improved, which can further improve the operation speed and component performance of the device. In addition, the length of the channel region of the memory cell of the present invention is also related to the trench depth. Therefore, a deeper trench can be formed in the process to avoid the first source / inverted region and the second source. The problem of abnormal electrical penetration between the drain / drain regions. In addition, by using the manufacturing method of the present invention, two memory cells sharing a same closed pole can be manufactured at the same time, as shown in FIG. 4G. That is, the floating gate 4 a, the selection gate 4 3 4 a, and the control gate 4 2 2 constitute a memory cell. —F the gate 41 4b, the selection gate 434 b, and the control gate 422 constitute another ancient system. ; I remember f ° so 'component accumulation degree can be retrieved by the process of the present invention, and the process cost can also be reduced. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to

Page 20 1227547_ 5. Description of the invention (15) The invention is limited. Any person skilled in the art can make some modifications and retouches without departing from the spirit and scope of the invention. The attached application patent shall prevail.

12129twf.ptd Page 21 1227547 Brief description of the diagram Figure 1 is a cross-section diagram of a conventional flash memory cell. Figures 2A to 2D are schematic cross-sectional views of the conventional manufacturing process of a flash memory cell. Figures 3A to 3J are cross-sectional schematic diagrams of the manufacturing process of a flash memory cell according to a preferred embodiment of the present invention. Figures 4A to 4G are according to Zhao 4 \\\ A schematic cross-sectional view of the manufacturing process of a flash memory cell in a preferred embodiment. [Schematic mark description], 20 > 300, 400: substrate 2 1, 22: gate oxide layer 23: silicon nitride dielectric layer 24 , 424: top cap layer 25: silicon nitride layer 25a ^ 332, 412, 432 spacer 27: drain region 2 8 ·· source region 31: polycrystalline silicon layers 31a, 31b ^ 31 4a 314b% 414a 41 4b: Floating gate 32: bit line 33 > 3 2 2, 4 2 2: control gate 40, 42, 306, 307, 406: trench 301: dielectric layer 3 0 4, 404: cover layer 308, 408: Tunneling oxide layer

12129twf.ptd Page 22 1227547 Schematic description 310, 310a, 330 > 410, 410a, 430: Conductor layer-316, 336, 416, 436: Source / drain region 318, 318a, 325, 418, 418a , 425: inter-gate dielectric layer 3 2 0, 320a, 420 > 42 0a: protective layer 3 2 6, 4 2 6: doped polycrystalline silicon layers 334a, 334b, 434a, 434b: select gate 4 0 2: liner Layer 4 2 8: Silicided metal layer

12129twf.ptd Page 23

Claims (1)

1227547 VI. Scope of patent application 1. A method for manufacturing a flash memory cell, comprising: providing a substrate; forming a patterned mask layer on the substrate; and using the patterned mask layer as a mask to etch the mask A substrate for forming a trench in the substrate; forming a first dielectric layer on the substrate; forming a first gate and a second gate on each side wall of the trench, the first gate and the second gate The second gates are separated by a distance and expose part of the first dielectric layer at the bottom of the trench; a first source / drain region is formed in the substrate at the bottom of the trench; a second is formed on the substrate A dielectric layer; forming a protective layer on the second dielectric layer;-'-removing part of the protective layer, the second dielectric layer and the first dielectric layer to expose the substrate at the bottom of the trench A surface; forming a third gate on the substrate to fill the trench; removing the mask layer; forming a third dielectric layer on the substrate; on the first gate and the second gate A corresponding fourth gate and a fifth gate are formed on the sidewall; and A second source / > and a pole region are formed in the substrate on the side of the fourth gate and the fifth gate. 2. The method for manufacturing a flash memory cell according to item 1 of the scope of the patent application, wherein the material of the protective layer includes one of a semiconductor material and a conductive material. 12129twf.ptd Page 24 1227547 6. Scope of patent application 3. The method for manufacturing a flash memory cell as described in item 1 of the scope of patent application, wherein the material of the protective layer includes undoped polycrystalline silicon. 4. The method for manufacturing a flash memory cell according to item 3 of the scope of the patent application, wherein the method for forming the protective layer includes a chemical vapor deposition method. 5. The method for manufacturing a flash memory cell according to item 3 of the scope of the patent application, wherein the thickness of the protective layer is about 100 angstroms. 6. The method for manufacturing a flash memory cell according to any one of claims 1 to 3 in the scope of patent application, wherein the first gate, the second gate, the third gate, the fourth gate The material of the gate and the fifth gate is doped polycrystalline stone. 7. The method for manufacturing a flash memory cell as described in item 1 of the scope of the patent application, wherein the first gate and the second gate are floating gates, and the third gate controls the gate, and the first gate Four gates and the fifth gate select gate 0 8. The method for manufacturing a flash memory cell as described in item 1 of the scope of patent application, wherein the fourth gate and the fifth gate are doped by a It is composed of a polycrystalline silicon layer and a silicided metal layer. 9. The method for manufacturing a flash memory cell according to item 1 of the scope of patent application, wherein the first dielectric layer is a tunneling oxide layer, and the second dielectric layer and the third dielectric layer are gates. Dielectric layer. 10. The method for manufacturing a flash memory cell according to item 1 of the scope of the patent application, wherein the method of forming the first gate electrode and the second gate electrode on a side wall of the trench includes: filling a trench into the trench. Conductor layer 12129twf.ptd Page 25 1227547 6. The scope of the patent application is subjected to an etching step so that the top of the conductor layer is lower than the surface of the cover layer; a gap is formed on the side wall of the trench and covers part of the conductor layer And using the gap wall and the mask layer as an etching mask, removing a part of the conductor layer, and forming the first gate electrode and the second gate electrode on the sidewall of the trench. π. The method for manufacturing a flash memory cell according to item 1 of the scope of patent application, wherein the method of forming the first gate electrode and the second gate electrode on a side wall of the trench includes: filling a conductor in the trench Layer; removing the conductor layer on the surface of the cover layer; and patterning the conductor layer to form the first gate electrode and the second gate electrode on the sidewall of the trench. 1 2. The method for manufacturing a flash memory cell according to item 1 of the scope of patent application, wherein before the step of forming a patterned mask layer on the substrate, further comprising forming a liner on the substrate, and The step of removing the cover layer further includes removing the liner. 1 3. The method for manufacturing a flash memory cell as described in item 12 of the scope of patent application, wherein the material of the liner layer is silicon oxide, and the material of the cover layer is nitrogen fossil. 1 4. The method for manufacturing a flash memory cell according to item 1 of the scope of patent application, wherein before the step of forming a patterned mask layer on the substrate, it further comprises forming a fourth dielectric on the substrate. Floor. 1 5. —A flash memory cell manufacturing method, including ... 12129twf.ptd Page 26 1227547 6. The scope of the patent application provides a substrate on which an opening layer and a curtain layer have been formed, and a trench formed in the substrate is formed at the opening; A tunnel oxide layer is formed on the surface of the trench; a conductor layer is filled in the trench; an etching step is performed so that the top of the conductor layer is higher than the surface of the liner layer and lower than the surface of the cover layer; A pair of gap walls are formed on the side walls of the trench and cover a part of the conductor layer. Using the pair of gap walls and the mask layer as an etch mask, a part of the conductor layer is removed to form a first floating wall A gate electrode and a second floating gate electrode; forming a first source / drain region in the substrate at the bottom of the trench; forming a first inter-gate dielectric layer on the substrate and the surface of the trench; Forming a protective layer on the first inter-gate dielectric layer; removing part of the protective layer, the first inter-gate dielectric layer and the tunneling oxide layer to expose the substrate surface at the bottom of the trench; on the substrate One of the trenches A control gate, the top of which is higher than the top of the first floating gate and the second floating gate; removing the liner layer and the cover layer; forming a second on the substrate An inter-gate dielectric layer; forming a corresponding first selection gate and a second selection gate on the pair of gap walls, side walls of the first floating gate and the second floating gate; and 12129twf.ptd Page 27 1227547_ 6. Scope of patent application A second source / dead region is formed in the substrate on the side of the first selection gate and the second selection gate. 1 6. The method for manufacturing a flash memory cell as described in item 15 of the scope of patent application, wherein the material of the protective layer includes a semiconductor material and a conductive material. 1 7. As described in item 15 of the scope of patent application A method for manufacturing a flash memory cell, wherein a material of the protective layer includes undoped polycrystalline silicon. 1 8. The method for manufacturing a flash memory cell according to item 17 of the scope of patent application, wherein the method for forming the protective layer includes a chemical vapor deposition method. 19. The method for manufacturing a flash memory cell according to item 17 in the scope of the patent application, wherein the material of the conductor layer and the control gate is doped polycrystalline silicon. 20. The method for manufacturing a flash memory cell according to item 15 of the scope of patent application, wherein the material of the first inter-gate dielectric layer includes silicon oxide / silicon nitride / stone oxide. 2 1. The method for manufacturing a flash memory cell according to item 15 of the scope of patent application, wherein the material of the second inter-gate dielectric layer includes silicon oxide. 2 2. The method for manufacturing a flash memory cell according to item 15 of the scope of the patent application, wherein the first selection gate and the second selection gate are composed of a doped polycrystalline silicon layer and a silicided metal layer . 2 3. The method for manufacturing a flash memory cell according to item 15 of the scope of patent application, wherein the material of the liner layer is silicon oxide, and the material of the cover layer is nitrogen fossil. 12129twf.ptd Page 28