TWI227541B - Method for removal of hemispherical grained silicon in deep trench - Google Patents
Method for removal of hemispherical grained silicon in deep trench Download PDFInfo
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- TWI227541B TWI227541B TW092131135A TW92131135A TWI227541B TW I227541 B TWI227541 B TW I227541B TW 092131135 A TW092131135 A TW 092131135A TW 92131135 A TW92131135 A TW 92131135A TW I227541 B TWI227541 B TW I227541B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0387—Making the trench
Description
1227541 玖、發明說明 【發明所屬之技術領域】 本發明是有關於一種移除半球形晶粒矽 (Hemispherical Grained Silicon; HSG)之方法,特別是在 深溝渠結構中,利用矽鍺(SiGe)做為蝕刻終止層,以移除 半球形晶粒石夕層之方法。 【先前技術】 近年來微電子工業快速發展,元件基組日趨微小化, 對微小尺寸之動怨隨機存取記憶體(DynamiC Ran(J〇ln
Access Memory; DRAM)而言,維持每個晶胞的電容並不 谷易,目刚其儲存電容至少要在25fF以上。增加電容表 面積或使用高介電係數之介電材料均可改善此問題。其 中’利用半球形晶粒矽(Hemispherical Grained silicon; HSG)以增加電容表面積的方法,已廣泛應用於堆疊式 dram。 然而,半球形晶粒矽應用到溝渠式DRAM時卻面臨 了困難:半球形晶粒矽與單晶矽的物性相似 溝渠上半部之半球形晶粒矽時,會破壞溝渠 ,因此在蝕刻
因寄生電容而導致儲存電容下降。
1227541 上以做為餘刻終止層,經多道步驟處理,移 後,*沉接一 * > 工千#的乳化物 、半球开)晶粒矽層,並去除溝渠上半部 形晶粒石夕。缺屮制扣傲 口丨之半球 造的困難度 繁複’大幅提高了溝渠式DRAM製 【發明内容】 半球之目的就是在提供—種在深溝渠結構中移除 + 東:粒矽(Hemispherical Grained Silicon; HSG),且 不會破壞溝渠側壁之方法,以及—種在溝渠式電容中導入 半球形晶粒矽後,可維持或提高每個晶胞的儲存電容之方 法。 鑒於上述目的,本發明之一態樣,係提供一種利用石夕 鍺(SWe)做為—終止層,並以濕㈣製程移除深溝渠中 半球形晶粒石夕之方法。濕㈣製程所用之氫氧化卸/丙嗣/ 水的混合液對半球形晶粒矽與矽鍺層的蝕刻速率選擇性 比很高,故在移除溝渠上半部之半球形晶粒矽層時,不會 破壞溝渠側壁,同時其平整度更符合後續製程之需求。另 -=面’梦鍺層亦提高了埋藏帶(buriedst叫叫區域的 固態溶解度,因此可降低埋藏帶的阻抗,進而提高驅動電 流。 本發明之另一態樣,係提供一種導入半球形晶粒矽至 溝渠式電容之方法《其蝕刻終止層係為鍺原子佈植所形成 之埋藏石夕錯層’可利用預定角度將埋藏石夕錯層只佈植於溝 1227541 渠之領形區(collar region)内,故製得之電容在半球形晶 粒石夕層與溝渠側壁間並不存在蝕刻終止層,因此可維持Z 提高晶胞的儲存電容。另一方面,由於此法所佈植之蝕刻 終止層,可選擇性地只形成於溝渠之上半部,而無需增加 去除溝渠下半部蝕刻終止層的步驟,故有效簡化導入半球 形晶粒矽至溝渠式電容之製程。 【實施方式】 本發明之移除深溝渠結構中半球形晶粒矽之方法的 一較佳實施例,將參照附件圖式詳述如下。 第1A圖係為一具研磨墊104與溝渠1〇2結構之基 板,以一預定角度(較佳的為約8。〜約12。,更佳的為約ι〇Τ) 施加鍺原子佈植100及快速熱處理後,形成一埋藏矽鍺層 於溝木102側壁之領形區(c〇uar 内,以做為姓 刻終止層之用。由於藉由控制佈植角度可使埋藏矽鍺層 108選擇性地只形成於溝渠1〇2之上半部,而不會形成在 溝渠102 了半部,因此無須進行去除溝《1〇2 了半部埋藏 广錯層108的步驟。此外,此埋藏石夕錯層1〇8亦提高了埋 赛帶(buried strap; Bs)區域的固態溶解度,可降低埋藏帶 的卩且l/u而提呵驅動電流。另一方面,埋藏矽鍺層工⑽更可 仏為罩幕層之用,其在㈣溝渠時可保護溝渠之上半部, ,再進仃濕式蝕刻時只蝕刻領形區以下的部分而形 并瓦形結構之溝渠。 接著’參照第1B圖及第lc圖,沉積一半球形晶粗 1227541 矽層116於埋藏矽鍺層1〇8及溝渠ι〇2上再 玻璃層丨25於半球形晶粒矽層ιΐ6之上。 沉積一绅梦 隨後進行綠㈣與去除之製程。 形成-光阻層叫溝渠102下半部内,其深度用圖義 ==高度;然後去除溝渠1〇2上半部未被光阻 層32覆盍之砷矽玻璃層125。 阻二!覆 所示,去除溝渠102上半部未被光 、晶:㈣f 球形晶粒石夕層116。此去除步驟係採用 程’當所用之氫氧化卸/丙酮/水之混合液組成為 ''' 4時’對半球形晶粒梦層116與埋藏石夕鍺層1〇8的 蝕刻速率選擇性比高達20 :卜故在去除溝渠102上半部 之半球形晶粒矽層116的同時,不會破壞溝渠ι〇2之侧 〃平整度更可符合後續製程之需求,以改善整合後 的電性性質,如有效提高漏電流等。 ,去除溝渠102上半部未被光阻層132覆蓋之半球形晶 粒矽層U6後,再移除殘餘的光阻層132。如第1F圖所 八心之’儿積一覆蓋層1 5 0 ,,其材料係為四乙氧基矽烷 (TEOS) 〇 退火處理砷矽玻璃層125,以驅入砷原子而形成一埋 藏電極160。然後進行濕蝕刻製程去除覆蓋層15〇及溝渠 102下半部之砷矽玻璃層125,結果如第圖所示。 最後’如第1H圖所示,沉積一介電層18〇於溝渠ι〇2 之上’其材料係為氧化矽/氮化矽(Si〇2/SiN)。所得之溝渠 式電容結構,在半球形晶粒矽層丨丨6與溝渠丨〇2侧壁之 I 1227541 間,並無餘刻終止層,故可維持、甚至提高每個晶胞之儲 存電容。 由上述本發明之較佳實施例可知,應用本發明之移馀 深溝渠結構中半球形晶粒矽之方法,可藉由佈植方式選擇 性地將埋藏石夕錯層只形成於支渠之上半部,無需增加去除 溝渠下半部埋藏石夕鍺層的步驟,故可簡化製程。且進行濕 蝕刻製耘時所用之氫氧化鉀/丙酮/水混合液對半球形晶 .粒石夕與埋藏補層的㈣速率選擇性很高,因此將埋藏: 鍺層做為蝕刻終止層’在去除半球形晶粒矽時,不會破壞 溝渠之側壁,故可改善整合後的電性性質。又因為二求形 晶粒矽層與溝渠側壁間並不存在蝕刻終止層,因此可維 持、甚至提高晶胞的儲存電容。埋藏石夕錯層除了做為姓刻 終止層外,其亦增加了埋藏帶區域的固態溶解度,可降低 埋藏帶的阻抗而提高驅動電流。 雖然本發明已以一較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 神=範圍内,當可作各種之更動與潤飾,因此本發明之= 護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述與其他目的、特徵、和優點能更明 顯易懂,配合所附圖式,加以說明如下·· 第1A圖至第1H圖係繪示本發明之一較佳實施例 中,在深溝渠結構中移除半球形晶粒矽的製程剖面圖。 1227541 【元件代表符號簡單說明】 100 :鍺原子佈植 104 :研磨墊 116 :半球形晶粒矽層 132 :光阻層 160 :埋藏電極 102 :溝渠 108 :埋藏矽鍺層 125 :砷矽玻璃層 150 :覆蓋層 1 80 :介電層
Claims (1)
1227541 拾、申請專利範園 晶粒石夕層之方法, 1 · 一種移除深溝渠結構中半球形 至少包含: 形成一餘刻終止層於一 (collar region)内; 基材上溝渠側壁之一領形區
形成-半球形晶粒石夕層於該溝渠及該韻刻終止層上’· 形成一砷矽玻璃層於該半球形晶粒矽層上;曰 形成一光阻層於該溝渠下半部内; 去除該溝渠上半部未被該光阻層覆蓋之該切玻璃 層;以及 去除該溝渠上半部未被該光阻層覆蓋之該半球形晶 粒石夕層。 * 2.如申請專利範圍第丨項所述之移除深溝渠結構中 半球形晶粒矽層之方法,更包含: 去除殘餘之該光阻層; 形成一覆蓋層於該溝渠上; 形成一埋藏電極於該溝渠侧壁内; 去除殘餘之該砷矽玻璃層及該覆蓋層;以及 形成一介電層。 3 ·如申睛專利範圍第1項所述之移除深溝泪处 半球形晶粒石夕声> t、土甘 i A、、、口構中 藏石夕鍺層。 ^糸為一埋 11 1227541 4·如申請專利範圍第3項所述之移除深溝渠結構中 半球形晶粒矽層之方法,其中上述之埋藏矽鍺層更做為一 罩幕層’用以形成一瓶形結構之溝渠。 5·如申請專利範圍第3項所述之移除深溝渠結構中 半球形晶粒矽層之方法,其中上述之埋藏矽鍺層係利用一 預定角度佈植鍺原子以形成於該溝渠之上半部内。 籲 6·如申請專利範圍第5項所述之移除深溝渠結構中 半球形晶粒矽層之方法,其中上述之預定角度係為約8。〜 · 約 12。。 入如申請專利範圍第3項所述之移除深溝渠結構中 半球形晶粒石夕層U法,其中上述之埋藏石夕鍺層係更利用 决速熱處理以形成於該溝渠之上半部内。 、,8·如t 4專利範圍帛1項所述之移除深溝渠結構申 半球形晶粒石夕層之方法’其中上述之去除該溝渠上半部未 =該光阻層覆蓋之該半球形晶㈣層,係㈣—濕餘刻製 9. 半球形 曰如申%專利範圍帛8項所述之移除深溝渠結構 旧粒石夕層之方法,其中上述之濕㈣製程係使用 中 氫 12 1227541 氧化鉀/丙酮/水之混合液。 * 1〇.如申請專利範圍第9項所述之移除深溝渠結構中 t球形晶粒石夕層之方法,其中上述之混合液的比例,係為 風乳化卸/丙崎=〇.8/1/3.5〜1.2/1/4.2,其中當氫氧化〜 丙明/水之比例為約1/1/4時,對該半球形晶粒發層盘該石夕 鍺層之蝕刻速率選擇性比高達2〇: 1。 “ u ·如申咕專利範圍第1項所述之移除深溝渠結構中 半球形晶粒石夕層之方法,其中上述之半球形晶粒石夕層與該 神石夕玻璃f,係利用_沈積製㈣形成。 . ^ •如巾μ專利範圍第1項所述之移除深溝渠結構中 半球形晶粒石夕層之方法,其中上述之去除該溝渠上半部未 、乂光阻層覆蓋之_石夕玻璃層,係使用—濕触刻製程。 U. 一種製造溝渠式電容之方法,至少包含: 提供一基材,該基材至少具一溝渠結構; 形成一蝕刻終止層於該溝渠之上半部内; 沉積-半球形晶粒矽層於該溝渠及該蝕刻終止層上; 沉積一砷矽玻璃層於該半球形晶粒矽層上; 形成一光阻層於該溝渠内; 去除該溝渠上半部之該光阻層; 去除該溝渠上半部未被該光阻層覆蓋之該砷矽玻璃 13 !227541 層; 去除該溝渠上半部未被該光阻層覆蓋之該半球形晶 极石夕層; 去除殘餘之該光阻層; 沉積一覆蓋層於該溝渠上; 形成一埋藏電極於該溝渠側壁内; 蝕刻殘餘之該砷矽玻璃層及該覆蓋層;以及 沉積一介電層。 14·如申請專利範圍第13項所述之製造溝黍式電分 之方法’其中上述之蝕刻終止層係為一埋藏矽鍺層 I5·如申請專利範圍第14項所述之製造溝渠式m > 之方法,其中上述之埋藏矽鍺層更做為一罩幕層,用以形 成一瓶形結構之溝渠。 16·如申請專利範圍第14項所述之製造溝雍式電容 之方法,其中上述之埋藏矽鍺層之形成步驟,更包含: 利用一預定角度佈植鍺原子;以及 快速熱處理製程。 I7·如申請專利範圍第13項所述之製造溝#武電^ 之方法’其巾上述之去除該溝渠上半部未被該心廣覆慕 之該半球形晶粒石夕層,係使用一濕餘刻製程。 1227541 18·如申請專利範圍第17項所述之製造溝渠式電容 之方法,其中上述之濕蝕刻製程係使用氫氧化鉀/丙酮/水 之混合液。 19·如申請專利範圍第13項所述之製造溝渠式電容 =法’其中上述之形成-埋藏電極,係使料火處 7坡璃層,以驅入砷原子所形成。 20. 如申請專利範圍第13項所述之、生 之方法,其中上述之覆蓋層係為四乙氧基心冓層渠。式電容 21. 如申請專利範圍第13項所述之 電容 之方法,其中上述之介電層係為氧化矽層:溝渠式 曰氣化矽層 15
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US8227311B2 (en) | 2010-10-07 | 2012-07-24 | International Business Machines Corporation | Method of forming enhanced capacitance trench capacitor |
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