TWI226692B - Method of making wire interconnection between two conductive pads - Google Patents

Method of making wire interconnection between two conductive pads Download PDF

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Publication number
TWI226692B
TWI226692B TW092123763A TW92123763A TWI226692B TW I226692 B TWI226692 B TW I226692B TW 092123763 A TW092123763 A TW 092123763A TW 92123763 A TW92123763 A TW 92123763A TW I226692 B TWI226692 B TW I226692B
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wire
conductive
hole
tip
dielectric
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TW092123763A
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Chinese (zh)
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TW200509348A (en
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Chi-Tsung Chiu
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Advanced Semiconductor Eng
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7815Means for applying permanent coating, e.g. in-situ coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512Aligning
    • H01L2224/85148Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518Translational movements
    • H01L2224/85181Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

A method of making a wire interconnection between two conductive pads by a capillary having an inner hole, a middle hole surrounding the inner hole and an outer hole surrounding the middle hole is disclosed. The method includes the steps of forming a ball formed on one end of a wire threaded through the inner hole of the capillary, bonding the ball of the wire to one of the conductive pads to form a ball bond employing the capillary, dispensing a dielectric material from the middle hole of the capillary onto the surface of the ball bond to form a dielectric film covering the ball bond, dispensing a conductive material from the outer hole of the capillary onto the surface of the dielectric film covering the ball bond, moving the capillary while the dielectric material and the conductive material continue to flow from the capillary onto the wire threaded through the inner hole of the capillary thereby forming a loop between the first and the second conductive pads, and making a stitch bond to the second conductive pad to finish the wire interconnection.

Description

12266921226692

【發明所屬之技術領域】 本發明係有關於一種在兩導電接墊之間形成導線連接 (wire interconnection) ^ ^ ^ 〇 【先前技術】 隨著半導體裝置的訊號傳輸高速化、集積化及封裝結 體積小型化,使得半導體裝置的〗/〇數不斷的提高,因此 使得半導體裝置中的銲線(b〇nd ing wi re)之間距越來越接 近,結果常常造成半導體裝置之銲線電路短路(sh〇ri: circuit )的情況。另外,由於在半導體裝置中的訊號交 錯傳送更加激烈’因此由電磁干擾(electromagnetic interfere)所產生之不理想的雜散電阻、雜散電容及雜 散電感,會導致在銲線中傳送之訊號產生雜訊(n〇ise )’進而增加功率的耗損及熱量的產生。 為了解決上述問題,熟知該項技術者係將一介電層 (dielectric layer)以及一金屬層鍍在銲線的表面。第 1圖所示係為民國91年11月13曰申請之中華民國第 0 9 1 1 3 3 2 7 2號專利申請案所揭示之半導體封裝構造1 〇 〇,其 包含一基板1 1 0、一晶片1 2 0、複數個導線連接1 3 〇以及一 封膠體140。各導線連接130係分別具有一中心導線132、 一介電層134以及一金屬層136。各導線132係分別接合基 板1 1 0與晶片1 20,各介電層1 34係分別包覆於各導線丨32的 表面,各金屬層136係分別包覆於各介電層134的表面。 在前述專利申請案中,該導線1 3 2係利用習知的打線接 合技術形成;該介電層1 3 4係利用習知的電漿化學氣相沉[Technical field to which the invention belongs] The present invention relates to a method for forming a wire interconnection between two conductive pads ^ ^ ^ ○ [Prior art] With the speeding up, integration and packaging of signal transmission of semiconductor devices The miniaturization of the semiconductor device has continuously improved the number of semiconductor devices. Therefore, the distance between bonding wires in semiconductor devices is getting closer and closer. As a result, the bonding wire circuits of semiconductor devices often cause short circuits ( sh〇ri: circuit). In addition, because the interleaving of signals in semiconductor devices is more intense, the undesirable stray resistance, stray capacitance, and stray inductance caused by electromagnetic interference will cause the signal transmitted in the wire to be generated. Noise 'further increases power consumption and heat generation. In order to solve the above problems, a person skilled in the art has plated a dielectric layer and a metal layer on the surface of the bonding wire. Figure 1 shows the semiconductor package structure 100 disclosed in the Republic of China Patent Application No. 0 9 1 1 3 3 2 7 2 filed on November 13, 1991, which includes a substrate 1 1 0, A chip 120, a plurality of wires are connected to 130, and a gel 140. Each wire connection 130 has a central wire 132, a dielectric layer 134, and a metal layer 136, respectively. Each of the wires 132 is respectively bonded to the substrate 110 and the chip 120, each of the dielectric layers 134 is respectively coated on the surface of each of the wires 32, and each of the metal layers 136 is respectively coated on the surface of each of the dielectric layers 134. In the aforementioned patent application, the wire 1 3 2 was formed using a conventional wire bonding technology; the dielectric layer 1 3 4 was formed using a conventional plasma chemical vapor deposition method.

00712.ptd 第6頁 1226692 五、發明說明(2) nsv的方式,將介電層沉積在中心導線層的表 u二^ #屬f 6是利用沉積或是濺鍍的方式所形成,因 士刖述專利申睛案所教導之導線連接形成方法相當複雜耗 時。 【發明内容】 本發明之主要目的係提供一種在兩導電接墊之間形成導 線連接的新穎、方法’其可克服或改善前述先前技術之問 題。 根據本發明之方法係使用一種特殊的銲嘴(capi llary) 在兩導電接墊之間形成導線連接。該銲嘴具有一内側孔、 一中間孔環繞該内侧孔以及一外側孔環繞該中間孔。 ,據^發明之方法係包含下列步驟:形成一球體(baii) 於穿設在該銲嘴内側孔之導線之一末端;利用該銲嘴將該 導線之球體接合於該第一導電接墊以一人1 b〇nd) ^ -介電材料由該鲜嘴之中間孔成配^至接^= 之表面以形成一介電層包覆該球接合;將一 銲嘴,外側孔配送至包覆在該球接合上之介由: ,该銲嘴且使該介電材料與導電材料繼續由^ :設=嘴内側孔之導線上,藉此形成一線心 ΐ 了 ί ί接塾之間,且該線弧係具有介電層包覆該導線以 及八^導電層覆蓋於該介電層上;在該線弧形成之後,形 成一壓印接合(stitch bond)於該第二導電接墊而完成該 線路連接。 π ^ / 根據前述方法形成之導線連接,其用以傳輸電子訊號之00712.ptd Page 6 1226692 5. Description of the invention (2) nsv method, the dielectric layer is deposited on the surface of the center wire layer ^ #general f 6 is formed by deposition or sputtering, because The method of forming a wire connection taught in the patent application is quite complicated and time-consuming. SUMMARY OF THE INVENTION The main object of the present invention is to provide a novel and method of forming a wire connection between two conductive pads, which can overcome or improve the aforementioned problems of the prior art. The method according to the invention uses a special cap llary to form a wire connection between two conductive pads. The welding tip has an inner hole, an intermediate hole surrounding the inner hole, and an outer hole surrounding the intermediate hole. According to the invention method, the method includes the following steps: forming a sphere (baii) at one end of the wire passing through the hole inside the welding tip; using the welding tip to join the sphere of the wire to the first conductive pad to 1 person 1 b〇nd) ^-The dielectric material is matched from the middle hole of the fresh mouth to the surface connected to ^ = to form a dielectric layer to cover the ball joint; a nozzle and the outer hole are distributed to the cover The ball joint is formed by:, the solder tip and the dielectric material and the conductive material are continued from ^: set = the wire in the hole inside the mouth, thereby forming a line between the ί and 塾, and The wire arc system has a dielectric layer covering the wire and an eight-layer conductive layer covering the dielectric layer. After the wire arc is formed, a stamp bond is formed on the second conductive pad to complete the process. The line is connected. π ^ / a wire connection formed according to the foregoing method, which is used to transmit electronic signals

00712.ptd 第7頁 1226692 導線係包覆於介電 擾以及降低中心導 方法係使用前述之 墊之間時,一起形 因此可有效簡化製 為了讓本發明之 顯揭不及了解,下 圖示,作詳細說明 【實施方式】 層以及導電層,藉 線的阻抗值。此外 特殊銲嘴而在形成 成該介電層以及導 程增進產率。 上述和其他目的、 文特舉本發明較佳 如下。 此可完全阻隔電磁干 ,由於根據本發明之 導線連接於兩導電接 電層於中心導線上, 特徵、和優點能更明 實施例,並配合所附 本發明係長:出在兩導電接墊間形成導線連接(w i r e interconnect ion)的方法。根據本發明一實施例的導線連 接形成方法將參照第2 - 7圖描述於下。 首先,如2圖所示,形成一球體(ba 11)212於一導線210 之末端。詳細言之,該球體(ba 1 1 ) 2 1 2可利用電子點火或 氫焰的方式將導線2 1 0之末端燒結而成。該導線2 1 0係穿設 在一銲嘴2 3 0之内側孔2 3 2内。該銲嘴2 3 0係為一打線機 (未示於圖中)之一部分。值得注意的是,該銲嘴2 3 0具 有一中間孔2 3 4環繞該内側孔2 3 2以及一外側孔2 3 6環繞該 中間孔2 34。接著,該銲嘴23 0係被該打線機移至一目標導 電接墊上。如圖所示,在本實施例中該目標導電接墊係為 一晶片240上之晶片銲墊242,而另一導電接墊係為基板 2 6 0上之接墊2 6 2。 接著,參見第3圖,利用該銲嘴230將第2圖所示之導線 2 1 0之球體2 1 2接合於該晶片銲墊2 4 2以形成一球接合(ba 1 100712.ptd Page 7 1226692 When the wire system is covered with dielectric interference and the method of reducing the center conduction is used between the aforementioned pads, the shape can be effectively simplified. Detailed description [Embodiment] The resistance value of the layer and the conductive layer, and the borrow line. In addition, a special solder tip is formed to form the dielectric layer and the lead improves productivity. The above and other objects, and the present invention are particularly preferred as follows. This can completely block the electromagnetic interference. Since the wire according to the present invention is connected to two conductive electrical connection layers on the central wire, the characteristics and advantages can be more clearly exemplified, and in accordance with the attached invention, the length is: between the two conductive pads A method of forming a wire interconnect ion. A method for forming a wire connection according to an embodiment of the present invention will be described below with reference to FIGS. 2-7. First, as shown in FIG. 2, a sphere (ba 11) 212 is formed at the end of a wire 210. In detail, the sphere (ba 1 1) 2 1 2 can be sintered at the end of the wire 2 10 by means of electronic ignition or hydrogen flame. The wire 2 1 0 is passed through an inner hole 2 3 2 of a welding tip 2 3 0. The welding tip 230 is a part of a wire drawing machine (not shown). It is worth noting that the welding tip 2 3 0 has a middle hole 2 3 4 surrounding the inner hole 2 3 2 and an outer hole 2 3 6 surrounding the middle hole 2 34. Next, the soldering tip 230 is moved to a target conductive pad by the wire bonding machine. As shown in the figure, in this embodiment, the target conductive pad is a wafer pad 242 on a chip 240, and the other conductive pad is a pad 2 62 on the substrate 260. Next, referring to FIG. 3, using the welding tip 230, the sphere 2 1 2 of the wire 2 1 0 shown in FIG. 2 is bonded to the wafer pad 2 4 2 to form a ball joint (ba 1 1

00712.ptd 第8頁 1226692 五、發明說明(4) b ο n d ) 2 1 4。詳細言之,其係先利用該銲嘴2 3 0將第2圖所示 之導線2 1 0之球體2 1 2下壓於該晶片靜墊2 4 2上,然後該球 體2 1 2會因打線機施力且施加超音波能量而被擠壓形成該 球接合(ball bond)214。 接著,將一介電材料由該銲嘴2 3 0之中間孔2 3 4配送至該 球接合214之表面以形成一介電層252 (參見第3圖)包覆 該球接合2 1 4,並且將一導電材料由該銲嘴2 3 0之外側孔 236配送至包覆在該球接合上之介電層252表面而形成一導 電層2 54 (參見第3圖)。 參見第4圖以及第5圖,在將介電材料與導電材料配送至 至該球接合2 1 4表面上之後,移動該銲嘴2 3 0以形成一線弧 216於該晶片銲墊242與接墊262之間。參見第4圖,在該銲 嘴2 3 0向上移動時,該介電材料係持續由該銲嘴2 3 0之中間 孔2 34流至由銲嘴23 0之内側孔2 32延伸而出的導線210上, 並且該導電材料係持續由該銲嘴2 3 0之外側孔2 3 6流至該介 電材料上。接著,將該銲嘴2 30朝該接墊2 6 2移動而形成該 線弧216 (參見第5圖),且其具有介電層252包覆該導線 210以及具有導電層254覆蓋於該介電層252上。 參見第5圖’在該線弧2 1 6形成之後,繼續移動該銲嘴 2 3 0但使該介電材料與導電材料停止由該銲嘴流出,藉此 在該線弧2 1 6末端形成一未覆蓋該介電材料與導電材料之 導線裸露部21 8。 ^ 然後利用該銲嘴2 3 0將第5圖所示之導線裸露部2丨8下壓 於該接墊2 6 2上,然後該導線裸露部218會因打線機施力且00712.ptd Page 8 1226692 V. Description of the invention (4) b ο n d) 2 1 4 In detail, it first uses the welding tip 2 3 0 to press the ball 2 1 2 of the wire 2 1 0 shown in FIG. 2 onto the wafer static pad 2 4 2, and then the ball 2 1 2 will cause The wire bonder applies force and applies ultrasonic energy to be squeezed to form the ball bond 214. Next, a dielectric material is distributed from the middle hole 2 3 4 of the welding tip 2 3 0 to the surface of the ball joint 214 to form a dielectric layer 252 (see FIG. 3) covering the ball joint 2 1 4. And a conductive material is delivered from the outer hole 236 of the welding tip 230 to the surface of the dielectric layer 252 covering the ball joint to form a conductive layer 2 54 (see FIG. 3). Referring to FIG. 4 and FIG. 5, after the dielectric material and the conductive material are delivered to the surface of the ball joint 2 1 4, the welding tip 2 3 0 is moved to form a line arc 216 between the wafer pad 242 and the wafer. Between pads 262. Referring to FIG. 4, when the welding tip 2 30 moves upward, the dielectric material continuously flows from the middle hole 2 34 of the welding tip 2 3 0 to extend from the inner hole 2 32 of the welding tip 23 0. On the conductive wire 210, and the conductive material continuously flows from the hole 2 3 6 on the outer side of the welding tip 2 30 to the dielectric material. Next, the solder tip 2 30 is moved toward the pad 2 6 2 to form the wire arc 216 (see FIG. 5), and it has a dielectric layer 252 covering the wire 210 and a conductive layer 254 covering the dielectric. On the electrical layer 252. See FIG. 5 'After the line arc 2 1 6 is formed, continue to move the tip 2 3 0 but stop the dielectric material and the conductive material from flowing out of the tip, thereby forming at the end of the line arc 2 1 6 An exposed portion of the wire 218 that does not cover the dielectric material and the conductive material. ^ Then use the soldering tip 2 3 0 to press the exposed wire portion 2 丨 8 shown in Fig. 5 onto the pad 2 6 2. Then, the exposed wire portion 218 will be forced by the wire machine and

00712.ptd 第9頁 1226692 五、發明說明(5) 施加超音波能量而被擠壓形成一壓印接合(st丨tch bond)219(參見第6圖)。之後,如第6圖所示,將該銲嘴 2 3 0略微升起’並將介電材料由該銲嘴23〇之中間孔234配 送至該壓印接合219之表面以形成介電層包覆該壓印接合 219 ’並且將導電材料由該銲嘴23〇之外側孔236配送至包 覆在該壓印接合219上之介電層表面。在本實施例中,由 該銲嘴2 3 0外側孔2 3 6可以持續配送導電材料直到相鄰導線 壓印接合2 1 9上的導電層2 5 2係連成一片並且連接到一接地 端,例如基板上的接地墊(g r 0 u n d p a d ),以便導線上的 導電層2 5 2能夠透過基板的接地墊部來接地。 最後,以線夾具(wire clamp ) 2 3 9夾緊導線2 10並且進一 步將該銲嘴2 3 0略微升起。參見第7圖,隨著該銲嘴2 3 0往 上升起,該導線會斷裂在該壓印接合2 1 9尖銳邊緣之最弱 點。 由於前述方法係使用銲嘴2 30而在形成導線連接於兩導 電接墊之間時,一起形成該介電層252以及導電層254於該 中心導線2 1 0上,因此可有效簡化製程增進產率。 根據本發明另一實施例的導線連接形成方法將參照第2- 7 圖描述於下。 首先,如8圖所示,形成一球體(ball)212於一導線210 之末端。該銲嘴2 31係為一打線機(未示於圖中)之一部 分。值得注意的是’該銲嘴2 31具有一中間孔2 34環繞該内 側孔2 32。接著,該銲嘴231係被該打線機移至一晶片240 上之晶片銲墊242上。00712.ptd Page 9 1226692 V. Description of the invention (5) The ultrasonic energy is applied to be extruded to form a stamp bond 219 (see Fig. 6). Thereafter, as shown in FIG. 6, the soldering tip 2 3 0 is slightly raised 'and the dielectric material is delivered from the middle hole 234 of the soldering tip 23 to the surface of the imprint joint 219 to form a dielectric layer package. The embossed joint 219 ′ is covered and a conductive material is delivered from the outer hole 236 of the tip 23 to the surface of the dielectric layer covering the embossed joint 219. In this embodiment, conductive material can be continuously distributed from the welding hole 2 3 0 outside hole 2 3 6 until the conductive layer 2 5 2 on the adjacent wire embossed joint 2 1 9 is connected into one piece and connected to a ground terminal. For example, a ground pad (gr 0 undpad) on the substrate, so that the conductive layer 2 5 2 on the wire can be grounded through the ground pad portion of the substrate. Finally, the wire 2 10 is clamped with a wire clamp 2 3 9 and the welding tip 2 3 0 is further raised slightly. Referring to Fig. 7, as the tip 2 30 rises, the wire will break at the weakest point of the sharp edge of the stamped joint 2 1 9. Since the foregoing method uses the solder tip 2 30 and forms a dielectric layer 252 and a conductive layer 254 on the center conductor 2 10 together when forming a wire connected between two conductive pads, the process can be effectively simplified to increase production. rate. A method for forming a wire connection according to another embodiment of the present invention will be described below with reference to FIGS. 2 to 7. First, as shown in FIG. 8, a ball 212 is formed at the end of a wire 210. The welding tip 2 31 is part of a wire drawing machine (not shown). It is worth noting that 'the welding tip 2 31 has a middle hole 2 34 surrounding the inner side hole 2 32. Then, the soldering tip 231 is moved to the wafer pad 242 on a wafer 240 by the wire bonding machine.

00712.ptd 第10頁 1226692 五、發明說明(6) 接著,參見第9圖,利用該銲嘴2 3 1將第2圖所示之導線 210之球體212接合於該晶片銲墊242以形成一球接合(ball bond)214。接著,將一介電材料由該銲嘴231之中間孔234 配送至該球接合214之表面以形成一介電層252 (參見第9 圖)包覆該球接合2 1 4。 參見第10圖以及第11圖,在將介電材料配送至至該球接 合214表面上之後,移動該銲嘴231以形成一線弧2 16於該 晶片銲墊242與接墊262之間。參見第1〇圖,在該鏵嘴231 向上移動時,該介電材料係持續由該銲嘴2 3 1之中間孔2 3 4 流至由銲嘴2 3 1之内側孔2 3 2延伸而出的導線2 1 0上。接 著,將該銲嘴2 3 1朝該接墊2 6 2移動而形成該線弧2 1 6 (參 見第11圖),且其具有介電層252包覆該導線210。 參見第1 1圖,在該線弧2 1 6形成之後,繼續移動該銲嘴 2 3 1但使該介電材料與導電材料停止由該銲嘴流出,藉此 在該線弧2 1 6末端形成一未覆蓋該介電材料與導電材料之 導線裸露部2 1 8。 接著,利用該銲嘴2 3 1將第11圖所示之導線裸露部2 1 8下 壓於該接墊26 2上,然後該導線裸露部218會因打線機施力 且施加超音波能量而被擠壓形成一壓印接合(stitch bond)219 (參見第12圖)。之後,如第12圖所示,將該銲 嘴231略微升起,並將介電材料由該銲嘴231之中間孔234 配送至該壓印接合2 1 9之表面以形成介電層包覆該壓印接 合 219 〇 最後,以線夾具(wire clamp)239夾緊導線210並且進一00712.ptd Page 10 1226692 5. Description of the invention (6) Next, referring to FIG. 9, using the soldering tip 2 3 1 to join the ball 212 of the wire 210 shown in FIG. 2 to the wafer pad 242 to form a Ball bond (ball bond) 214. Next, a dielectric material is distributed from the middle hole 234 of the welding tip 231 to the surface of the ball joint 214 to form a dielectric layer 252 (see FIG. 9) covering the ball joint 2 1 4. Referring to FIG. 10 and FIG. 11, after the dielectric material is distributed onto the surface of the ball joint 214, the welding tip 231 is moved to form a line arc 2 16 between the wafer pad 242 and the pad 262. Referring to FIG. 10, when the nozzle 231 moves upward, the dielectric material continues to flow from the middle hole 2 3 4 of the welding tip 2 3 1 to extend from the inner hole 2 3 2 of the welding tip 2 3 1 Out of the wires 2 1 0. Next, the solder tip 2 3 1 is moved toward the pad 2 6 2 to form the wire arc 2 1 6 (see FIG. 11), and it has a dielectric layer 252 covering the wire 210. Referring to FIG. 11, after the line arc 2 1 6 is formed, continue to move the welding tip 2 3 1 but stop the dielectric material and the conductive material from flowing out of the welding tip, thereby at the end of the line arc 2 1 6 An exposed wire portion 2 1 8 is formed which does not cover the dielectric material and the conductive material. Next, using the welding tip 2 3 1 to press the exposed part 2 1 8 of the wire shown in FIG. 11 onto the pad 26 2, and then the exposed part 218 of the wire will be subjected to the force of the wire bonder and the ultrasonic energy. It is extruded to form a stitch bond 219 (see FIG. 12). Thereafter, as shown in FIG. 12, the soldering tip 231 is slightly raised, and a dielectric material is distributed from the middle hole 234 of the soldering tip 231 to the surface of the imprint joint 2 1 9 to form a dielectric layer coating. This imprint joint 219. Finally, the wire 210 is clamped with a wire clamp 239 and further

00712.ptd 第11頁 1226692 五、發明說明(7) 步將該銲嘴2 3 1略微升起。參見第1 3圖,隨著該銲嘴2 3 1往 上升起,該導線會斷裂在該壓印接合2 1 9尖銳邊緣之最弱 點〇 由於前述方法係使用銲嘴2 3 1而在形成導線連接於兩導 電接墊之間時,將該介電層2 52形成在該中心導線210上, 因此可有效簡化製程增進產率。 根據本發明第8 _ 1 3圖所示方法形成之導線連接,其中心 導線210係被介電層252所包覆,因此介電層252可以避免 相鄰的導線2 1 0相互接觸,所以不會產生電路短路的情 形’同時介電層2 5 2也可以降低電磁干擾的現象。此外, 根據本發明第2 - 7圖所示方法形成之導旅連接另設有一導 電層2 54包覆於介電層252外,藉此產生屏蔽效應 (shielding effect )來反射穿越介電層的電磁波,使得 不同導線連接之間不會因為電磁干擾而產生不理想的雜散 電阻、雜散電容及雜散電感,而進一步有效地抑制雜訊問 Ϊ二值得注意的是,第7圖所示導線連接的結構係類似同 纜的結構,所以導線2 10能夠如同同軸電纜般藉 ,=2 52之厚度來控制導線21〇之阻抗值約為5〇〜75 (ohms ) 〇 — 雖然本發明已以 定本發明,任何熟 範圍内,當可作各 圍當視後附之申請 前述較佳實施例揭示 習此技藝者,在不脫 種之更動與修改。因 專利範圍所界定者為 ,然其並非用以限 離本發明之精神和 此本發明之保護範 準。00712.ptd Page 11 1226692 V. Description of the invention (7) Step 2 raise the welding tip 2 3 1 slightly. Referring to FIG. 13, as the tip 2 3 1 rises, the wire will break at the weakest point of the sharp edge of the embossed joint 2 1 9. Because the aforementioned method uses the tip 2 3 1 to form the wire When connected between two conductive pads, the dielectric layer 2 52 is formed on the center wire 210, which can effectively simplify the manufacturing process and increase the yield. In the wire connection formed according to the method shown in FIG. 8_13 of the present invention, the center wire 210 is covered by the dielectric layer 252, so the dielectric layer 252 can prevent adjacent wires 2 1 0 from contacting each other, so A short circuit situation will occur ', and the dielectric layer 2 5 2 can also reduce the phenomenon of electromagnetic interference. In addition, the conductive connection formed according to the method shown in Figs. 2-7 of the present invention is further provided with a conductive layer 2 54 covering the dielectric layer 252, thereby generating a shielding effect to reflect the light passing through the dielectric layer. Electromagnetic waves, so that undesired stray resistance, stray capacitance, and stray inductance will not be generated between the connection of different wires due to electromagnetic interference, and further effectively suppress the noise question. It is worth noting that the wires shown in Figure 7 The connection structure is similar to the structure of the same cable, so the wires 2 and 10 can be borrowed like a coaxial cable, and the thickness of the wire 2 is 2 to control the impedance of the wire 21. The impedance value is about 50 to 75 (ohms). Although the present invention has been Within the scope of the present invention, the above-mentioned preferred embodiment can be applied as an attachment to various aspects of the present invention to reveal those skilled in the art, without making changes and modifications. Because the scope of the patent is defined, it is not intended to limit the spirit of the present invention and the protection scope of the present invention.

1226692 圖式簡單說明 【圖式簡單說明】 第1圖··中華民國第0 9 1 1 33 2 7 2號專利申請案所揭示之半 導體封裝構造之剖示圖; 第2 - 7圖:其係用以說明根據本發明一實施例之導線連 接(wire interconnection)形成方法;及 第8 -1 3圖:其係用以說明根據本發明另一實施例之導線 連接形成方法。 圖號說明: 100 半 導 體 封 裝構造 110 基 板 120 晶 片 130 導 線 連 接 140 封 膠 體 132 導 線 134 介 電 層 136 金 屬 層 210 導 線 21 2 球 體 214 球 接 合 21 6 線 弧 218 導 線 裸 露 部 21 9 壓 印 接 合 230 銲 嘴 23 1 銲 嘴 232 孔 234 孔 236 孔 239 線 夾 具 240 晶 片 242 晶 片 銲 墊 252 介 電 層 254 導 電 層 260 基 板 262 接 墊1226692 Brief Description of Drawings [Simplified Illustration of Drawings] Figure 1 ·· Sectional view of the semiconductor package structure disclosed in the Republic of China Patent Application No. 0 9 1 1 33 2 7 2; Figures 2-7: It is used to describe a method for forming a wire interconnection according to an embodiment of the present invention; and FIGS. 8 to 13 are diagrams for explaining a method for forming a wire connection according to another embodiment of the present invention. Description of drawing number: 100 semiconductor package structure 110 substrate 120 chip 130 wire connection 140 encapsulant 132 wire 134 dielectric layer 136 metal layer 210 wire 21 2 sphere 214 ball joint 21 6 wire arc 218 wire exposed part 21 9 embossed joint 230 solder Nozzle 23 1 Solder tip 232 hole 234 hole 236 hole 239 wire clamp 240 wafer 242 wafer pad 252 dielectric layer 254 conductive layer 260 substrate 262 pad

00712.ptd 第13頁00712.ptd Page 13

Claims (1)

1226692 六、申請專利範圍 , · 1、一種在第一與第二導電接墊之間形成導線連(wire interconnection)的方法,其包含· 提供一銲嘴(capi 1 lary),其具有一内側孔、一中間孔 環繞該内側孔以及一外側孔環繞該中間孔; 形成一球體(ba 1 1 )於穿設在該銲嘴内侧孔之導線之一末 端; 利用該銲嘴將該導線之球體接合於該第一導電接墊以形 成一球接合(ball bond), 將一介電材料由該銲嘴之中間孔配送至該球接合之表面 以形成一介電層包覆該球接合; 將一導電材料由該銲嘴之外側孔配送至包覆在該球接合 上之介電層表面; 移動該銲嘴且使該介電材料與導電材料繼續由該鮮嘴流 至該穿設於銲嘴内側孔之導線上,藉此形成一線弧於該第 一與第二導電接墊之間; 在該線弧形成之後,形成一壓印接合(st itch bond)於 該第二導電接墊而完成該線路連接。 ' 2、依申請專利範圍第1項之在第一與第二導電接墊之間形 成導線連接的方法,其中在該線弧形成步驟中,該介電材 料係持續由該銲嘴之中間孔流至該導線上且該導電材料係 持續由該銲嘴之外側孔流至該介電材料上,藉此所形成線 弧具有一介電層包覆該導線且具有一導電層覆蓋於該介電 層上。1226692 6. Scope of patent application, 1. A method for forming a wire interconnection between a first and a second conductive pad, comprising: providing a capi 1 lary with an inner hole A middle hole surrounds the inner hole and an outer hole surrounds the middle hole; a sphere (ba 1 1) is formed at one end of the wire passing through the inner hole of the welding tip; and the ball of the wire is joined by using the welding tip Forming a ball bond on the first conductive pad, distributing a dielectric material from the middle hole of the tip to the surface of the ball bond to form a dielectric layer covering the ball bond; The conductive material is distributed from the outer hole of the welding tip to the surface of the dielectric layer covering the ball joint; the welding tip is moved and the dielectric material and the conductive material continue to flow from the fresh tip to the penetrating solder tip On the wire of the inner hole, a line arc is formed between the first and second conductive pads; after the line arc is formed, a stitch bond is formed on the second conductive pad to complete The line is connected. '2. The method of forming a wire connection between the first and second conductive pads according to item 1 of the scope of the patent application, wherein in the wire arc forming step, the dielectric material is continuously passed through the middle hole of the welding tip Flowing onto the wire and the conductive material continues to flow from the hole outside the tip to the dielectric material, whereby the formed arc has a dielectric layer covering the wire and a conductive layer covering the dielectric On the electrical layer. 00712.ptd 第14頁 1226692 六、申請專利範圍 3、 依申請專利範圍第1項之在第一與第二導電接墊之間形 成導線連接的方法,其中在該壓印接合形成步驟係包含: 在該線弧形成之後,繼續移動該銲嘴且使該介電材料與 導電材料停止由該銲嘴流出,藉此在該線弧末端形成一未 覆蓋該介電材料與導電材料之導線裸露部; 將該導線裸露部接合於該第二導電接墊以形成一壓印接 合於該第二導電接墊上;以及 將該介電材料由該銲嘴之中間孔配送至該壓印接合之表 面以形成介電層包覆該壓印接合並且將該導電材料由該銲 嘴之外側孔配送至包覆在該壓印接合上之介電層表面。 4、 依申請專利範圍第1項之在第一與第二導電接墊之間形 成導線連接的方法,其中該第一導電接墊係為一晶片上之 晶片銲墊,且第二導電接墊係為一基板上之接墊或導線架 上之引線。 5、 一種在第一與第二導電接墊之間形成導線連接(wire interconnection)的方法,其包含· 提供一銲嘴(c a p i 1 1 a r y ),其具有一内側孔、一中間孔 環繞該内側孔以及一外側孔環繞該中間孔; 形成一球體(ba 1 1 )於穿設在該銲嘴内側孔之導線之一末 端; 利用該銲嘴將該導線之球體接合於該第一導電接墊以形00712.ptd Page 14 1226692 VI. Application scope 3, The method for forming a wire connection between the first and second conductive pads according to item 1 of the scope of patent application, wherein the step of forming the embossed joint includes: After the line arc is formed, continue moving the tip and stop the dielectric material and conductive material from flowing out of the tip, thereby forming an exposed portion of the wire at the end of the line arc that does not cover the dielectric material and the conductive material. ; Bonding the exposed part of the wire to the second conductive pad to form an embossed bond to the second conductive pad; and distributing the dielectric material from the middle hole of the welding tip to the surface of the embossed bond to A dielectric layer is formed to cover the embossed joint and the conductive material is distributed from the outer hole of the welding tip to the surface of the dielectric layer covered on the embossed joint. 4. The method for forming a wire connection between the first and second conductive pads according to item 1 of the scope of the patent application, wherein the first conductive pad is a wafer pad on a wafer, and the second conductive pad It is a pad on a substrate or a lead on a lead frame. 5. A method for forming a wire interconnection between a first and a second conductive pad, comprising: providing a solder cap (capi 1 1 ary) having an inner hole and an intermediate hole surrounding the inner side A hole and an outer hole surround the middle hole; a sphere (ba 1 1) is formed at one end of the wire passing through the inner hole of the welding tip; the ball of the wire is bonded to the first conductive pad by the welding tip In shape 00712.ptd 第15頁 1226692 六、申請專利範圍 成一球接合(ball bond); 將一介電材料由該銲嘴之中間孔配送至該球接合之表面 以形成一介電層包覆該球接合; 將一導電材料由該銲嘴之外側孔配送至包覆在該球接合 上之介電層表面; 移動該銲嘴且使該介電材料與導電材料繼續由該銲嘴流 至該穿設於銲嘴内側孔之導線上,藉此形成一線弧於該第 一與第二導電接墊之間; 在該線弧形成之後,繼續移動該銲嘴且使該介電材料與 導電材料停止由該銲嘴流出,藉此在該線弧末端形成一未 覆蓋該介電材料與導電材料之導線裸露部; 將該導線裸露部接合於該第二導電接墊以形成一壓印接 合於該第二導電接墊上;以及 將該介電材料由該銲嘴之中間孔配送至該壓印接合之表 面以形成介電層包覆該壓印接合並且將該導電材料由該銲 嘴之外側孔配送至包覆在該壓印接合上之介電層表面。 6、依申請專利範圍第5項之在第一與第二導電接墊之間形 成導線連接的方法,其中在該線弧形成步驟中,該介電材 料係持續由該鲜*嘴之中間孔流至該導線上且該導電材料係 持續由該銲嘴之外側孔流至該介電材料上,藉此所形成線 弧具有一介電層包覆該導線且具有一導電層覆蓋於該介電 層上。00712.ptd Page 15 1226692 6. The scope of the patent application is a ball bond; a dielectric material is distributed from the middle hole of the tip to the surface of the ball joint to form a dielectric layer covering the ball joint ; Distribute a conductive material from the outer hole of the welding tip to the surface of the dielectric layer covering the ball joint; move the welding tip and continue the flow of the dielectric and conductive material from the welding tip to the penetration A wire arc is formed on the wire in the hole inside the welding tip between the first and second conductive pads; after the wire arc is formed, the welding tip is continued to move and the dielectric material and the conductive material are stopped. The solder nozzle flows out, thereby forming an exposed part of the wire that is not covered with the dielectric material and the conductive material at the end of the wire arc; joining the exposed part of the wire to the second conductive pad to form an embossed joint to the first Two conductive pads; and distributing the dielectric material from the middle hole of the tip to the surface of the embossed joint to form a dielectric layer covering the embossed joint and distribute the conductive material from the outer side hole of the tip To wrap over the imprint A dielectric layer formed on the surface together. 6. The method for forming a wire connection between the first and second conductive pads according to item 5 of the scope of the patent application, wherein in the wire arc forming step, the dielectric material is continuously passed through the middle hole of the fresh * mouth Flowing onto the wire and the conductive material continues to flow from the hole outside the tip to the dielectric material, whereby the formed arc has a dielectric layer covering the wire and a conductive layer covering the dielectric On the electrical layer. 00712.ptd 第16頁 1226692 六、申請專利範圍 7、依申請專利範圍第5項之在第一與第二導電接墊之間形 成導線連接的方法,其中該第一導電接墊係為一晶片上之 晶片銲墊,且第二導電接墊係為一基板上之接墊或導線架 上之引線。00712.ptd Page 16 1226692 6. Application for patent scope 7. Method for forming a wire connection between the first and second conductive pads according to item 5 of the patent application scope, wherein the first conductive pad is a chip And the second conductive pad is a pad on a substrate or a lead on a lead frame. 00712.ptd 第17頁00712.ptd Page 17
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