TWI226666B - Deep submicron T shaped gate semiconductor device and manufacturing the same - Google Patents

Abstract

Submicron T-gate formation using I-line stepper with phase shift mask (PSM) technique [1,2,3] has become very attractive due to its low capital investment and high throughput for GaAs MMIC technology. The present invention teaches a novel submicron (<0.2 mm) T-gate technology using shift mask technique. The 8% half-tone PSM was selected for the definition of the isolated narrow space. Before lithography, 2500 Å Si3N4 film was deposited on the wafer. After I-line PSM exposure and RIE etching of the silicon nitride film, openings with less than 0.25 mum wide were formed on the Si3N4 film. To further reduce the dimension of the openings, the wafer was then deposited addition 500 Å nitride and etched back using RIE without any mask. Less than 0.2 mum openings were formed on the wafer after the dry etch. The wafer was then coated with another layer of photoresist to form lift-off structure. This novel process is a high throughput T-gate process compared to conventional E-beam lithography technology for GaAs MMIC production.

Description

1226666 V. Description of the invention (1) Field of the invention The present invention relates to a method for manufacturing deep sub-micron semiconductor devices, and in particular, a method for manufacturing a -18-micrometer t-type gate for millimeter wave and ^ FET. BACKGROUND OF THE INVENTION Low-noise GaAs modulation doped field effect transistors (M0FET) are millimeter-wave radar,

^, Or components indispensable for direct broadcasting satellites, low signal-to-noise ratio and low price are inevitable. In order to achieve low signal-to-noise ratio, the key lies in the gate length of field effect transistors with deep submicrons. To reduce the signal-to-noise ratio, it is generally known to increase the cross-conductance gm without increasing the source and gate capacitance Cgs and the gate resistance Rg 'to reduce the length of the gate. Although the cylindrical gate increases gm, Rg also increases. There are proposals to use T-gates to increase both gm and decrease Rg. In order to manufacture deep sub-micron gates, using electron beam lithography (e-beaD1 nthography) is an effective method ', but the process of electron beam lithography is too slow, the production is limited, and it is not suitable for mass production. I-line stepper is used for the manufacture of 0 · 35 / ζιη integrated circuits. It has the advantages of mass production and low cost. The smaller line width is urgently needed in semiconductor manufacturing. -Push down the resolution of the ray, such as using off-axis illumination, phase shift mask (PSM), or proximity effect correction

1226666 V. Description of the invention (2) correction), where PSM is the best solution. However, using a four-layer interactive phase shift mask (chrome + 3 phase shift) can only be pushed down to 0.25 / m. in

The literature is 0 · 15 // m T-Shaped Gate Fabrication for GaAs MOSFET Using Phase Shift lithography "IEEE

Trans, on Electron Devices, 1 9 96 Vol. 43-No. 2 PP.238 244 ’Talking about the use of pEL (pattern-Edge

Line) method can obtain a resolution of 0.15, but a positive photoresist must be used, and a positive photoresist can only form a columnar gate, but cannot form an opening to make a τ gate, so a false must be formed first. The gate (dummy gate) is then lift-off to form a T-type gate, and the manufacturing process is very complicated. See Figure 1_ Previous Techniques' Modulation doped has been formed on the semi-insulated GaAs wafer as a crystalline layer such as n — A1〇2Ga () 8As / und〇ped Al〇2Ga〇8As / undoped I n015Ga0 85 As / undoped GaAs / Semi-insulated GaAs wafer 1 is implanted with boron ions as an isolation region, so that its surface is flat and it is good for forming fine patterns. Then use pEL phase-shifting photomask technology to make a false gate 2. This false gate is then further reduced to a width of 0 · 1 5 // m with a plasmon of 0. This false gate defines the bottom width of the τ-type gate. (Foot print), as shown in Figure 1 (a). (See Fig. 1 (1)), a layer of monolithic oxide (Si 02) 3 is deposited by electronic flash evaporation to obtain an opening at the bottom of a T-shaped gate, and the thickness of monolithic oxide 3 is about 4000 Angstroms. Then, remove the false gate by tearing to obtain an opening 5, and etch it on the substrate: a wide opening 5 is formed, and at the same time, lithography is used to etch and deposit the source / immortal dioxide dioxide and deposit A layer of AuGeNi / Au is used as the source / drain electrode 4 and is heated to form an alloy. This is shown in Figure 1 (c). And then first! Figure ((1) and then lithography &quot;

1226666

A large opening 6 of a T-type gate head layer with a width of l # m is formed, and then a layer of Ti / Ai is deposited on the photoresist 5 as the gate electrode and the photoresist 5 and On the metal, a layer of nitride oxide (Si3 04) with a thickness of 1000 angstroms is deposited as a passivation layer to obtain a MODFET (modulation doped field effect transistor) as shown in FIG. 2. Another document entitled "〇 · 2 iith〇graplay using Inline and alterating phase shift mask, proc · SPICE, Vol. 2726, pp · 453-460", discusses the use of alternative phase shift masks and The I-ray stepper can obtain a gate line width of 0 · 2 5 // m or even 0 · 1 8 // m. However, it requires a high degree of skill and cannot obtain a T-type gate, which cannot be used for mass production. Generally, 丨 -ray stepper is used together with the design criteria for optimizing the reticle and the phase shift reticle for optimizing the exposure conditions of the stepper. For the manufacture of T-gates, a line width of 0.25 can be obtained. Need to open the hole is less than 0.2 β m, which requires the use of PSM technology plus some technical processes. The invention uses the PSM technology plus the technique of RIE etching back nitride nitride to form the side wall without adding a mask to obtain an opening of 0 · 1 8 7 / zm, which is used for manufacturing a field effect transistor of a T-gate. . OBJECTS AND SUMMARY OF THE INVENTION An object of the present invention is to provide a method for fabricating a T-gate of a semiconductor device. This method can use k-ray stepper and phase shift mask technology to make k less than 0 · 1 8 // m The gate line width field effect transistor can be suitable for mass production needs;

Page 8 1226666 V. Description of the invention (4) Another purpose of the present invention is to use a nitrided wall to make an opening smaller than 0.18 mm from the resolution limit of the photomask further. Another purpose is to use the tear method Uift_. Is a τ type: ι pole. The above purpose of the present invention is to apply for a grant

Method reached. In response to the foregoing plutonium, the present invention proposes a method for manufacturing deep sub-micron field-effect transistors, including at least the following steps: (8) Modulated doped epitaxial wafers have been formed on a semi-absolute gallium halide wafer. A first nitride film is deposited on the channel region, the source / drain region, and the wafer on which the source / drain electrode has been formed. (B) The photoresist and phase shift mask are used to expose the first nitride film in a stepper. Opening pattern; (c) removing the exposed silicon nitride film by dry etching to form the first opening as the bottom opening of the T-gate; ((0 depositing a second nitride film, (e) anisotropic Dry etching and etch back to form a pair of side walls to further reduce the first opening; (f) lithography is used to form the first opening on the first opening; Head nail pattern; (row gate electrode # ^ etched to form a recessed structure of the gate area, (h) a layer of gate metal is fully deposited as the gate electrode; (i) the tear method (1 if t- of f) method to remove the photoresist and the gate metal on it to form a gate; (j) continue to complete the protective layer and the post-metallization process with MODFET.

1226666

V. Description of the invention (5) Furthermore, the present invention proposes a deep sub-micron T-gate field effect transistor element, which at least includes: (a) —Semi-insulated gallium arsenide wafer with ^ change =. The channel region and source / drain region of the crystal and the formed source / drain electrode; less (b) a bottom opening with a τ gate on the channel region, which uses a phase mask to step in I-rays Machine-made first opening, a second silicon nitride film is deposited thereon and etched back by dry etching to form a pair of side walls to form a bottom opening smaller than the gate of the first opening; (c) a recessed struct ^ Gate region; (d) — T-gate; Detailed description of the invention The following is a description of the fabrication of a sub-micron semiconductor device according to an embodiment of the present invention with reference to FIGS. 3 (a) to 3 (m). Method for manufacturing T-type gates. FIGS. 3 (a) to 3 (m) show steps in a method for manufacturing a T-type gate for manufacturing a sub-micron half-body device according to an example of the present invention. A cross-sectional view of a semiconductor element is used to show the method. As shown in Figure 3 U), a semi-insulating GaAs wafer} is formed, for example, Doped (modulation doped) or other conventional doped structure of the epitaxial layer of 20, using photolithography to form a photoresist layer 9 (positive or negative photoresist)% to cover the operating area (active area) of the element, Etching removes the worm crystal layer outside the active area to form the element barrier (isolation) 30 'and then removes the photoresist, as shown in Figure 3 (b).

Page 1212666 V. Description of the invention (6), · Apply another layer of photoresist 9 to expose the source / drain regions 20b, 20c in a lithography process, as shown in Figure 3 (c) ; Then fully deposit source / drain metal 4 (GeAuNiAu), as shown in Figure 3 (d); then lift-off to remove the photoresist and the metal layer thereon, at 4 ° C GeAuNiAu is alloyed with (jaAs below) at a temperature of about 0 degrees to obtain source / drain electrodes 4a, 4b, as shown in FIG. 3 (e); and then the first layer is fully deposited by chemical vapor deposition. The first silicon nitride (sl film 3, 2000 angstroms to 3,000 angstroms, as shown in FIG. 3 (f); then, a positive photoresist layer 9 is coated on the wafer, and then

Use a half-tone phase-shift mask 'PSM' of 8%, and use an I-ray stepper to perform exposure to obtain a pattern of the first opening smaller than 0.25, such as As shown in Fig. 3 (2); dry etching of silicon nitride by reactive ion etching to form the gate first opening 丨 »This opening is the smallest line width available with a phase shift mask, and Removal, as shown in Figure 3 (h). Comprehensively deposit another thin layer of second silicon nitride (s "N4) film n on the wafer by chemical vapor deposition, which is between 2M, 00 angstroms and 600 angstroms, as shown in Figure 3 And then using non-electrolytic etching to form a sequence of nitrides with a width of about 300 angstroms to 400 angstroms per side. This is the most critical process of the present invention. Is it controlled by the second nitride grinding? Second, to form the ideal narrow openings by forming side walls of different widths. 9a Bamboo ^ T ° f The bottom width is the true width of the gate, as shown in Figure 3 (j); Utilizing a phase shift mask) and exposing the husband with positive photoresistance η: uPPer head of the T-shaped gate, wide opening 14 and window sound p 8dLe ^ ^ ^ See, 1 "m .But it is also possible to use negative photoresistance. At this time, negative husband resistance is beneficial to the formation of the opening. The tearing structure ⑴ft_off thus formed ...

1226666 V. Description of the invention (7) Structure) is helpful to simplify the formation of the gate electrode. As shown in Figure 3 (k), 'After the gate is left to form a recessed structure of the gate region 18, it is comprehensive. Deposit gate electrode such as Ti / pt / Au metal layer 6, as shown in Fig. 3 (1); and then tear the photoresist 13 and the photoresist Ti / The Pt / Au metal 6 is removed to form a τ gate 6a, as shown in FIG. 3 (m). The T-gate is now complete. Subsequent processes, such as forming a silicon nitride protective layer and gate wiring pad openings, are all known to the skilled person and will not be repeated here. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the present invention. 'Every other equivalent change or the manufacture of gates applied to other components without departing from the spirit disclosed by the present invention should be It is included in the scope of patent application described below.

Page 12 1226666 Brief description of the drawings The foregoing and other objects, features, and advantages will be immediately understood and understood by the following preferred embodiments in conjunction with the drawings, wherein the same elements are marked with the same code. Fig. 1 (known technique) Cross-sectional view of MODFET process steps (a) Forming a false gate on a wafer; (b) Electron deposition of a layer of silicon dioxide (SiO2) to obtain a bottom of a D-type gate (C) Remove the false gate by tearing to obtain an opening, and etch to form a wider opening on the substrate; (d) Form a T-gate stud layer with a width of about 1 / zm The larger opening of the (Upper head) deposits a layer of Ti / A1 as the gate electrode. Figure 2 (known technique) Sectional view of MODFET Figure 3 is a sectional view of the manufacturing steps of the deep sub-micron τ-type gate field-effect transistor disclosed according to the present invention Area (active area); (b) forming an element barrier (isolation) by etching to remove the photoresist; (c) coating a photoresist to expose the source / drain region by a lithography process; (d) a full deposition source / Metal of the drain electrode; (e) The photoresist and metal layer are removed by lift-off, and GeAuNiAu and GaAs are alloyed at a temperature of about 400 degrees Celsius to obtain a source / drain electrode;

1226666 on page 13 Brief description of the diagram (f) Chemical vapor deposition with positive photoresist coating, Huazhou Λ); Figure of the first opening; Eye-shifted photomask and 1-ray stepper exposure (h ) #Etched silicon nitride formation ((; ·)) =; thinner layer: second resistance removal; etch back to form silicon nitride sidewall. (k) Using lithography to make openings; 7 sub-M positive photoresist exposure to form T-gate stud width. (l) Deposit gate electrode metal layer. (m) Form T-gate by tearing method. Explanation of symbols: 1 G a A s wafer 2 false gate 3 silicon dioxide (S i 02) 4 A u G e N i A u source / $ and electrode 4a, 4b source / drain electrode 5 negative light Resistance 6 Ti / Al metal layer 6a Ti / Al gate electrode 7 Silicon nitride protective layer 8 Silicon nitride

Page 14 1226666 Brief description of the diagram 9 Positive photoresistor 9a T-gate reduced opening 1 0 Gate first opening 11 Second silicon nitride film 1 2 Gate opening sidewall 13 Photoresistor 14 gate stud ( upper head of the T-shaped gate) wide opening 15 photoresist 1 6 source / metal electrode 17 source / drain electrode 18 recessed structure gate area 2 0 stupid layer 20a element operating area ( Active area) 2 0 b, 2 0 c source / impedance 3 0 element blocking (isolation)

Page 15

Claims (1)

1226666 6. Scope of patent application1. A method for manufacturing deep sub-micron τ-type gate field-effect electricity includes the following steps: The method of sun-solar body, to one (a) has been formed on a semi-insulating gallium arsenide wafer Channel area, source / drain area, and formed source / drain electrode ^ ^ doped epitaxial pass through a thin silicon nitride layer; (b) using a photoresist and phase shift mask to deposit on the Japanese yen Bu ray step an opening pattern; exposure to form the first (c) to remove the exposed silicon nitride by dry etching; to open the bottom of the T-gate; / to make an opening (d) A silicon nitride film; the Hi-directional μ-etchback is etched back to form a pair of side walls to further reduce-the first formed on the first opening is τ ^ larger than the first opening. head of the 1-shaped gate) pattern; (g) gate etching is performed to form a recessed (i structure) gate region; (h) a layer of gate metal is fully deposited as the gate; Open method (1 ift — of f) to remove the photoresist and its gate metal to form a T-shaped metal gate; (j) continue to complete the protective layer and after Metallization process to complete a M0DFET. 2. The method of application of the item patentable scope Shu, wherein the first silicon nitride thin Page 161226666 The thickness of the film ranges from 200 Angstroms to 3000 Angstroms. 3. The method according to item 1 of the patent application, wherein the photoresist is a positive resistance. ′ 、 Half ===; method ’wherein the phase shift is first masked by 5 degrees = :: 丨. The method of the first item of the range ’wherein the width of the first mouth Film 6 ::: 3 = The range of the two items 7 where the reduced first is opened, where the reduced first is opened 7. As in the method of the first scope of the patent application, the width of the mouth is less than 0.2 2 / m . 8. The method as described in item 1 of the scope of patent application. The width of the mouth is less than 0.18 // in. Contains: A deep sub-micron T-type gate field effect transistor element (A) —Semi-insulated gallium arsenide channel region and source / drain region and the source / drain electrode with modulated doping on the formed wafer; 1226666 6. Scope of patent application (b) There is a bottom opening of a T-shaped gate in the channel area, which is a first opening formed by an I-ray stepper using a phase shift mask, and a second is deposited on it. After the silicon nitride film is etched back by dry etching to form a pair of side walls to form the bottom opening of the gate smaller than the first opening; (c) the gate region of the recessed structure; (d) — T-gate ; # Page 18