1224836 五、發明說明（l) 【技術領域】 本發明係有關一種半導體封裝技術，特別β 金屬載板與其製造方法，以及應用於具有金屬J 體封裝元件的相關技術。 秋取之+導 【先前技術】 按’電子封裝之目的主要可作為傳遞電路 電能、提供散熱途徑以及結構保護與支持等作用 得遞 半導體後段之封裝製程中，導線架（Lead frame)° = 2 = 鱧載板（IC substrate)係作為積體電路晶片與外 接的橋樑，以用來傳輸晶片内部電子訊號至外部 傳統利用金屬導線架進行晶片安裝與打線之封裝栽 雖具有價格低廉及散熱果良好之優點；然而，隨 電路功能不斷地提昇，使得積體電路發展走向高度= :架片之Ϊ入輸出接點也大幅增加，習知利用導 ，、承载0曰片之方式最多僅能利用四邊做引腳使其 ，於，引腳數而無法提供足夠引腳；且導線 ς 連且單純的線路。 此延订相 一種可提供足夠引腳數之BGA封裝結構被提出 1 ’ ： Ϊ用—印刷電路板（PCB)作為承載晶片之載 Ξ始ί ΐ以其底部呈陣列式排列之錫球來代替傳統以金屬 周圍做弓丨腳的方式，此種封裝技術之好處在於相 :固：：：下’弓丨腳數可以變多’其封裝尺寸縮小許多。 &勢，爯積小、速度快及高密度之半導體封裝元件已為 加上封裝元件的消耗功率愈來愈大的結果，導致 第5頁 1224836 五、發明說明（2) 封裝元件的散熱 方式係在前述印 蓋印刷電路板表 散熱效果仍然有 有鑑 之優點， 元件，以 【内容】 本發 方法，其 半導體載 用於高引 電路板。 本發 體封裝元 載板上而 性，並使 數0 於此， 提出一 改善前 明之主 係利用 板之金 腳數之 明之另 件，其 提供一 完成封 問題日趨重要。BGA封裝增加散熱之解決 刷電路板上再設置一散熱片，使散熱片覆 面之晶片，以藉此增強散熱效果，但此種 限，不如傳統導線架之散熱效果。 本發明係在結合金屬導線架與印刷電路板 種半導體載板及其製造方法與半導體封裝 述之該等缺失。 、 要目的係在提供一種半導體載板及其 選擇性蝕刻或深控成型技術製作出二作為 ，載板，使其同時兼具有熱較果佳且可適 半導體封裝’以取代現有之導線架及印刷 一目的係在提供一種具有金屬載板之半導 係使一晶片直接安裝至一製作完成之金屬 良好的散熱途徑，以維持良好之散熱特 裝之半導體軻裝元件係可提供足夠之引腳 本發明之再_ 方法，其係利用絕= ; = : = =其製造 化’故可”於各種半導體構之製作使仔線路多樣 方法本Πΐ;製供-種半導體載板及其製造 無須如印刷電路拓：ί上下表面相連通之通槽或通孔，而 更路板的導通需利用鑽孔及鍍通孔技術，故可1224836 V. Description of the Invention (l) [Technical Field] The present invention relates to a semiconductor packaging technology, particularly a beta metal carrier board and a method for manufacturing the same, and related technologies applied to components having a metal J-body package. Autumn + lead [Previous technology] According to the purpose of 'electronic packaging', it can be used to transfer circuit power, provide heat dissipation pathways, and provide structural protection and support. In the packaging process of semiconductors, the lead frame ° = 2 = The IC substrate is used as a bridge between the integrated circuit chip and the external circuit to transmit the internal electronic signals of the chip to the outside. Traditionally, the metal lead frame is used for chip mounting and wiring. The package is low in cost and good in heat dissipation. Advantages; however, with the continuous improvement of circuit functions, the development of integrated circuits has increased to a high level =: the input and output contacts of rack chips have also increased significantly. It is known to use guides, and the method of carrying 0 chips can only use up to four sides. Make the pins so that the number of pins does not provide enough pins; and the wires are connected and simple lines. This renewal phase proposes a BGA package structure that can provide a sufficient number of pins. 1 ': Ϊ Use-printed circuit board (PCB) as the carrier of the carrier chip. Ϊ́ Replace with solder balls arranged in an array at the bottom. The traditional way to make bows and feet around metal is the advantage of this kind of packaging technology: phase: solid ::: the number of legs can be increased, and its package size is reduced. & potential, small package, fast speed and high density semiconductor package components have been the result of increasing the power consumption of package components, leading to page 5 1224836 V. Description of the invention (2) Heat dissipation method of package components The heat-dissipating effect of the printed circuit board surface of the aforementioned cover still has the advantage of being learned. According to the present method, the semiconductor is used for high-inductance circuit boards. The package body of the body is designed to be flexible on the carrier board, and the number is zeroed here. An improvement on the main function of the former is to make use of the board's gold pin number. It is becoming increasingly important to provide a complete cover. Solution to increase heat dissipation in BGA package. A heat sink is set on the circuit board to increase the heat dissipation effect. However, this limitation is not as good as that of traditional lead frames. The present invention relates to such defects described in a combination of a metal lead frame and a printed circuit board, a semiconductor carrier board, a manufacturing method thereof, and a semiconductor package. The main purpose is to provide a semiconductor carrier board and its selective etching or deep-control molding technology to produce a second-generation carrier board that simultaneously has better thermal performance and is suitable for semiconductor packaging, to replace the existing lead frame. The purpose of printing and printing is to provide a semiconductor system with a metal carrier board, which enables a wafer to be directly mounted to a finished metal. A good heat dissipation path to maintain good heat dissipation. Specially mounted semiconductor packaged components can provide sufficient guidance. The re-invented method of the script is based on the use of absolute =; =: = = its manufacturing method can be used to make a variety of semiconductor structures to make a variety of circuits. This method is used to manufacture semiconductor substrates and their manufacture. Such as printed circuit extensions: Through holes or vias that communicate with the upper and lower surfaces, and the conduction of the circuit board requires the use of drilling and plated through-hole technology, so
1224836 五、發明說明（3) 省去繞線之麻煩而縮小載板尺寸，或是在相同尺寸下可提 供較大之可利用面積。 本發明之一實施態樣係在一金屬板上係形成有一貫穿 之圖案化通槽設計，並於金屬板之圖案化通槽内填充一絕 緣材料，以便將該金屬板隔絕為複數個導電區域。 本發明之另一實施態樣係在一金屬板上形成有一貫穿 之圖案化通槽設計，並於此金屬板之圖案化通槽中填充絕 緣材料或不同導電性之材料，用以將該金屬板隔絕為複數 個導電區域、電阻或其他元件。 本發明之另一實施態樣係為半導體載板之製造方法， 其係先提供一金屬板，其上下表面分別形成一第一圖案化 薄膜與一第一薄膜；以第一圖案化光阻為罩幕蝕刻此金屬 板，以形成複數個上凹槽，隨後移除第一圖案化薄膜與第 一薄膜；接著在此些上凹槽内填塞填充物；再於金屬板之 上下表面分別形成一第二薄膜及一與前述第一圖案化薄膜 相對應之第二圖案化薄膜；並以第二圖案化光阻為罩幕半 蝕刻金屬板以形成複數個下凹槽，使其配合上凹槽而形成 複數通槽’用以將金屬板隔絕為複數個導電區域，之後移 除該二薄膜。 本發明之再一實施態樣係在提出一種具有前述半導體 載板之半導體封裝元件。 底下藉由具體實施例配合所附的圖式詳加說明，當更 容易瞭解本發明之目的、技術内容、特點及其所達成之功 效01224836 V. Description of the invention (3) Eliminate the trouble of winding and reduce the size of the carrier board, or provide a larger usable area under the same size. An embodiment of the present invention is a patterned through-groove design formed on a metal plate, and an insulating material is filled in the patterned through groove of the metal plate so as to isolate the metal plate into a plurality of conductive areas. . Another embodiment of the present invention is a patterned through-groove design formed on a metal plate, and the patterned through-groove of the metal plate is filled with an insulating material or a material with different conductivity for the metal. The board is isolated as a plurality of conductive areas, resistors or other components. Another embodiment of the present invention is a method for manufacturing a semiconductor substrate. First, a metal plate is provided, and a first patterned film and a first film are formed on the upper and lower surfaces, respectively. The mask etches the metal plate to form a plurality of upper grooves, and then removes the first patterned film and the first film; then fills the filler in the upper grooves; and forms one on each of the upper and lower surfaces of the metal plate. A second film and a second patterned film corresponding to the first patterned film; and half-etching the metal plate with the second patterned photoresist as a mask to form a plurality of lower grooves so as to fit the upper grooves A plurality of through grooves are formed to isolate the metal plate into a plurality of conductive regions, and then the two films are removed. Another embodiment of the present invention is to provide a semiconductor package component having the aforementioned semiconductor carrier board. In the following, detailed descriptions are provided by specific embodiments in conjunction with the accompanying drawings, so that it is easier to understand the purpose, technical content, features and functions of the present invention.
第7頁 1224836 五、發明說明（4) 【實施方法】 本發明係利用選擇性蝕刻或是深控成型技術製作出一 作為半導體載板之金屬載板，使其同時兼具有熱效果佳且 可適用於高引腳數之半導體封裝，以取代現有之導線架及 印刷電路板，並可利用此金屬載板製作做出半導體封裝元 件。 下面係藉由二不同之實施例來說明本發明之半導體載 板結構與製造方法，以及利用此載板所製作完成之半導體 封裝元件。 第一（a)圖至第一（g)圖分別為本發明在製作半導體載 板與其封裝元件之各步驟構造剖視圖。以蝕刻法為例：首 先，如第一（a)圖所示，進行光阻塗佈經影像轉移，使其 在一金屬板10之上、下表面分別形成有一圖案化薄膜12與 一薄膜14，且圖案化薄膜丨2之圖案請同時參考第二圖所 示。 再以圖案化光阻1 2為罩幕（Mask )，利用一次或數次 之選擇性钱刻方式，對金屬板丨〇進行半蝕刻，蝕刻去除裸 露之部份金屬板10，以形成如第一（b)圖所示之複數個已 定義之上凹槽16 ;而後蝕刻剝除此一圖案化薄膜12與薄膜 14 ’即可得到如第一（c)圖所示具有已定義圖案之上凹槽 16的金屬板10。 接著進行填塞（plug)製程，於上述之上凹槽16内填 塞支撐物或填充物18，並經過一研磨步驟進行填充物18之 平坦化’如第一（d)圖所示，使填充物18與金屬板1〇表面Page 7 1224836 V. Description of the invention (4) [Implementation method] The present invention uses selective etching or deep-control molding technology to produce a metal carrier board as a semiconductor carrier board, which simultaneously has a good thermal effect and It can be applied to high-pin-count semiconductor packages to replace the existing lead frames and printed circuit boards, and semiconductor package components can be fabricated using this metal carrier board. In the following, two different embodiments are used to explain the structure and manufacturing method of the semiconductor carrier board of the present invention, and the semiconductor package components manufactured using the carrier board. The first (a) to the first (g) diagrams are cross-sectional views of the steps of the present invention in each step of manufacturing a semiconductor carrier board and its package components. Take the etching method as an example: First, as shown in the first (a) figure, photoresist coating is performed and image transfer is performed, so that a patterned film 12 and a film 14 are formed on a metal plate 10 and a lower surface, respectively. Please refer to the second figure for the pattern of the patterned film 丨 2. Then, the patterned photoresist 12 is used as a mask, and the metal plate 10 is semi-etched by selective money engraving once or several times, and the exposed metal plate 10 is removed by etching to form A plurality of defined upper grooves 16 shown in (b); then the patterned thin film 12 and film 14 'are etched and stripped to obtain a defined pattern shown in FIG. 1 (c). Groove 16 of the metal plate 10. Next, a plug process is performed, and the support or filler 18 is filled in the above groove 16, and the filler 18 is flattened through a grinding step. As shown in the first (d) diagram, the filler is filled. 18 and metal plate 1〇 surface
1224836 五、發明說明（5) 齊平。其中，填充物18之材質係為樹脂、銀膠、銅膠或其 他材料。 重複前述之各步驟，以便在該金屬板1〇下表面形成複 數個下凹槽（因此製程與前述步驟相同，故於此不再重複 敘述）’使其配合上凹槽而形成複數通槽，並在金屬板1〇 下表面進行填塞製程’以形成如第一（e)圖所示之填充物 18係為絕緣材料可將該金屬板1〇隔絕為複數個導電區域， 使金屬板10中央作為安裝晶片預定區域，其周圍數個隔絕 之導電區域可用來作為對外之導電接點20。此外，填充物 亦可為一導電性材料，其係填充於金屬板特定之圖案化通 槽中，用以將區域形成特殊電性區域。 請參閱第一（f)圖所示，在隔離出導電區域之後，在 金屬板10之上下表面可選擇性的形成已定義之防焊罩幕層 (solder mask ) 22 ;接續在金屬板1〇上未被防焊罩幕層 22所覆蓋住 < 導電區域表面更經過一般表面處理步驟，以 形成一導電層24，用以增加導電區域之導電性，如此即可 完成一半導體載板2 6之製作。其中，導電層24之材質係選 自無電鍵錫、電鍍錫、無電鍍銀、電鍍鎳金及無電鍍鎳浸 金等種種之金屬表面處理。 完成金屬載板26之製作後，即可繼绩進行封裝製程， 如第一（g)圖至第一（k)圖所示。以第一（g)圖為例，在半 導體載板26之金屬板1〇表面周圍係環設有一環壁（Dam) 28 ’使環壁28圍繞安裝於金屬板上1〇之一晶片30，再利用 打線機將引線32電性連接晶片3〇上的輸出入接點與金屬板 1224836 五、發明說明（6) 0上的導電接點20，並有_透明蓋板34，如玻璃板或透明 塑膠板’安裝於環壁28上以覆蓋住該晶片30與引線32，以 形成阻隔外界物質進入的保護屏障；或如第一（h)圖所示 在環壁28内填充透明或非透明性樹脂35，並藉此保護晶片 30之電路面’此電路面即為通訊元件的作用區，進而製作 出一通訊元件。另外，樹脂35之填充方式亦可如第一（i) 圖及第一（j)圖所示。 其中，在金屬板1〇上之晶片預定區域更可形成有一容 置槽’如第一（k)圖所示，以提供容置安裝該晶片3〇之 用，以降低封裝高度。 除了上述之實施例外，本發明亦舉出另一封裝實施例 來說明本發明之技術内容，請參閱第四（3)圖至第四（f) 圖。首先，參照前述第一（a)圖至第一（d)圖所示之步驟， 以便在金屬板10上製作珣填充物18，如第四（3)圖所示， 用以將金屬板10隔絕為中央安裝晶片之預定區域，及其周 圍數個相互隔絕之導電區域用來作為對外之導電接點20。 請參閱第四（b)圖所示，再於金屬板10之上下表面選 擇性的形成已定義之罩幕層22，使其覆蓋晶片預定區域， 並在其餘金屬板10上形成一導電層24，以增加導電區域之 導電性。完成導電層24之表面處理步驟之後，即可去除罩 幕層22，請參閱第四（c)圖所示，然後在金屬板1〇上表面 之晶片預定區域上形成一薄膜36。 進行蝕刻製程，如第四（d)圖所示，蝕刻去除填充物 18下方金屬板10之部份金屬，使其形成一貫穿金屬板1〇之 第10頁 1224836 五、發明說明（7) 通槽37，而後去除該薄膜36。 接著’利用一黏膠38將一晶片30安裝至金屬板10之晶 片預定區域上’如第四（e)圖所示，再利用打線機將引線 32電性連接晶片3〇上的輸出入接點與金屬板上的導電接 點20 ;最後再參閱第四（f)圖所示，一封裝膠體4〇係覆蓋 在金屬板10之上表面，以包覆住該晶片3〇及引線32，此封 裝膠體40通常為環氧樹脂（ep〇xy resin)，藉以提供一 機械性的保護作用，避免受到外力侵害。 另外’更可接續在金屬板之下表面裝設有複數個金屬 銲球，以提供焊接至其他電子裝置上。 其中’本發明之封裝結構設計並非限定為前述二實施 例，除此之外，亦可依半導體載板之線路設計而改 型態設計。 本發明係在一金屬板上之已定義圖案化通槽或通孔 内填充有插塞或絕緣材料，以便將此金屬板隔絕為複數導 ，區域，進而形成金屬載板，此種以金屬載板作為半導體 载板之設計，係結合習知導線架與印刷電 點，故可歸納出，下列幾項優點： 孜何兴馒 同時兼具有散熱效 ，以取代現有之導1224836 V. Description of the invention (5) flush. The material of the filler 18 is resin, silver glue, copper glue or other materials. Repeat the foregoing steps, so as to form a plurality of lower grooves on the lower surface of the metal plate 10 (the process is the same as the previous steps, so it will not be repeated here). And a filling process is performed on the lower surface of the metal plate 10 to form the filler 18 shown in the first (e) figure as an insulating material. The metal plate 10 can be isolated into a plurality of conductive areas, so that the center of the metal plate 10 As the predetermined area for mounting the wafer, several isolated conductive areas around it can be used as the external conductive contacts 20. In addition, the filler may be a conductive material, which is filled in a specific patterned groove of a metal plate to form a region into a special electrical region. Please refer to the first (f) diagram. After the conductive area is isolated, a defined solder mask 22 can be selectively formed on the upper and lower surfaces of the metal plate 10; then, the metal plate 1 can be formed. The surface of the conductive region which is not covered by the solder mask curtain layer 22 is further subjected to a general surface treatment step to form a conductive layer 24 for increasing the conductivity of the conductive region. Thus, a semiconductor carrier board 2 6 can be completed. Of production. Among them, the material of the conductive layer 24 is selected from various kinds of metal surface treatments such as electroless tin, electroplated tin, electroless silver, electroplated nickel gold, and electroless nickel immersion gold. After the production of the metal carrier board 26 is completed, the packaging process can be performed as shown in the first (g) to the first (k) drawings. Taking the first (g) diagram as an example, a ring wall (Dam) 28 is provided around the surface of the metal plate 10 of the semiconductor carrier 26 so that the ring wall 28 surrounds a wafer 30 mounted on the metal plate 10. Then, the wire 32 is used to electrically connect the input / output contacts on the wafer 30 with the metal plate 1224836. V. The conductive contact 20 on the invention description (6) 0, and has a transparent cover plate 34, such as a glass plate or A transparent plastic plate is mounted on the ring wall 28 to cover the chip 30 and the lead 32 to form a protective barrier to prevent the entry of foreign substances; or fill the ring wall 28 with transparent or non-transparent as shown in the first (h) figure. The resin 35 is used to protect the circuit surface of the wafer 30. This circuit surface is the active area of the communication element, and a communication element is manufactured. In addition, the filling method of the resin 35 may be as shown in the first (i) diagram and the first (j) diagram. Among them, an accommodating groove 'can be formed in a predetermined area of the wafer on the metal plate 10, as shown in the first (k) diagram, so as to provide the accommodating and mounting of the wafer 30 to reduce the package height. In addition to the above-mentioned implementation exceptions, the present invention also enumerates another package embodiment to illustrate the technical content of the present invention. Please refer to FIGS. 4 (3) to 4 (f). First, referring to the steps shown in the first (a) to the first (d) diagrams, in order to make a radon filler 18 on the metal plate 10, as shown in the fourth (3) diagram, the metal plate 10 Isolation is a predetermined area of the centrally mounted chip, and several isolated conductive areas around it are used as external conductive contacts 20. Referring to FIG. 4 (b), a defined mask layer 22 is selectively formed on the upper and lower surfaces of the metal plate 10 so as to cover a predetermined area of the wafer, and a conductive layer 24 is formed on the remaining metal plates 10. To increase the conductivity of the conductive area. After the surface treatment step of the conductive layer 24 is completed, the mask layer 22 can be removed, as shown in FIG. 4 (c), and then a thin film 36 is formed on a predetermined area of the wafer on the upper surface of the metal plate 10. Carry out the etching process, as shown in Figure 4 (d), by etching to remove a part of the metal of the metal plate 10 under the filler 18 to form a piercing through the metal plate 10 page 1224836 V. Description of the invention (7) Groove 37, and then the film 36 is removed. Next, 'a wafer 30 is mounted on a predetermined area of the wafer of the metal plate 10 by using an adhesive 38' as shown in the fourth (e) diagram, and then a wire 32 is used to electrically connect the lead 32 to the output of the wafer 30 Point and the conductive contact 20 on the metal plate; finally referring to the fourth (f) figure, a packaging gel 40 covers the upper surface of the metal plate 10 to cover the chip 30 and the lead 32, The encapsulant 40 is usually an epoxy resin, so as to provide a mechanical protection function to avoid being attacked by external forces. In addition, a plurality of metal solder balls can be mounted on the lower surface of the metal plate to provide soldering to other electronic devices. Among them, the design of the packaging structure of the present invention is not limited to the foregoing two embodiments. In addition, the design can also be modified based on the circuit design of the semiconductor substrate. The invention is a method in which a defined patterned through-groove or through-hole in a metal plate is filled with plugs or insulating materials so as to isolate the metal plate into a plurality of conductors and regions, thereby forming a metal carrier plate. The design of the board as a semiconductor carrier is based on the combination of the conventional lead frame and printed electrical points. Therefore, the following advantages can be summarized: He Xingyu also has heat dissipation efficiency to replace the existing guide.
一、本發明製作出之半導體載板係 果佳且可適用於高引腳數之半導想封裝 線架及印刷電路板。 性，並使完成封裝之半導體封I # ”、、 干守菔釕裝兀件係可提供足夠之引腳 二、本發明係將一晶片直接安裝 ^ ^ u ^ ^ ^ Λ t 饮艾衣主製作完成之金屬 載板上而k供-良好的散熱途徑，以維持良好 屬1. The semiconductor carrier board produced by the present invention is excellent and can be applied to high-pin-count semiconducting package wireframes and printed circuit boards. The semiconductor package I # of the package is completed, and the dry ruthenium mounting element can provide enough pins. The present invention is to directly mount a chip. ^ ^ U ^ ^ ^ ^ t The finished metal carrier board is provided for a good heat dissipation path to maintain a good property.
1224836 五、發明說明（8) 數。 路=、本發明係利用絕緣材料與支撐結構之製作使得線 多樣化，故可適用於各類型之半導體封裝。 四本發明係直接製作出上下表面相連通之通槽或通 ，而無須如印刷電路板的導通需制鑽孔及鑛通孔技 ς故可省去繞線之麻煩而縮小載板尺寸，或是在相同尺 寸下可提供較大之可利用面積。 =上所述之實施例僅係為說明本發明之技術思想及特 目的在使熟習此項技藝之人士能夠瞭解本發明之内 容並據以實施，當不能以之限定本發明之專利範圍，即大 i依ϋ明所揭示之精神所作之均等變化或修飾，仍應涵 蓋在本發明之專利範圍内。 圖號說明： 10 金屬板 12 14 薄膜 16 18 填充物 20 22 罩幕層 24 26 半導體載板 28 30 晶片 32 34 透明蓋板 35 36 薄膜 37 38 黏膠 40 圖案化薄膜 上凹槽 導電接點 導電層 環壁 引線 樹脂 通槽 封裝膠體 第12頁 1224836 圖式簡單說明 第一（a)圖至第一（k)圖分別為本發明在製作半導體載板與 其封裝元件之各步驟構造剖視圖。 第二圖為第一（a)圖之俯視圖。 第三圖為第一（e)圖之俯視圖。 第四（a)圖至第四（f)圖分別為本發明另一實施例在製作半 導體載板與其封裝元件之各步驟構造剖視圖。1224836 V. Description of invention (8) number. Road = The present invention uses the production of insulating materials and support structures to make the wires diversified, so it can be applied to various types of semiconductor packages. The present invention directly makes through grooves or throughs which communicate with the upper and lower surfaces, and does not require drilling and ore through holes such as the printed circuit board, so it can save the trouble of winding and reduce the size of the carrier board, or It can provide a larger usable area under the same size. The above-mentioned embodiment is only for explaining the technical idea and special purpose of the present invention, so that those skilled in the art can understand the content of the present invention and implement it accordingly. When the scope of the patent of the present invention cannot be limited, Equal changes or modifications made in accordance with the spirit disclosed by Zhuo Ming should still be covered by the patent scope of the present invention. Description of drawing number: 10 metal plate 12 14 film 16 18 filler 20 22 cover layer 24 26 semiconductor carrier 28 30 chip 32 34 transparent cover 35 36 film 37 38 adhesive 40 groove conductive contact on patterned film Layer ring wall lead resin through-slot encapsulation gel Page 12 1283636 The drawings briefly explain the first (a) to the first (k) are sectional views of the structure of each step in the process of manufacturing a semiconductor carrier board and its packaging components according to the present invention. The second figure is a top view of the first (a) figure. The third figure is a top view of the first (e) figure. Figures 4 (a) to 4 (f) are cross-sectional views of the steps in the fabrication of a semiconductor carrier board and its package components according to another embodiment of the present invention.
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