JP2004363379A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2004363379A
JP2004363379A JP2003160892A JP2003160892A JP2004363379A JP 2004363379 A JP2004363379 A JP 2004363379A JP 2003160892 A JP2003160892 A JP 2003160892A JP 2003160892 A JP2003160892 A JP 2003160892A JP 2004363379 A JP2004363379 A JP 2004363379A
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Japan
Prior art keywords
support substrate
semiconductor device
electrode
back surface
semiconductor element
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JP2003160892A
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Japanese (ja)
Inventor
Kiyoshi Mita
清志 三田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
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Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
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Application filed by Kanto Sanyo Semiconductors Co Ltd, Sanyo Electric Co Ltd filed Critical Kanto Sanyo Semiconductors Co Ltd
Priority to JP2003160892A priority Critical patent/JP2004363379A/en
Priority to TW093114610A priority patent/TWI251451B/en
Priority to KR1020040038413A priority patent/KR100629830B1/en
Priority to CNB2004100452293A priority patent/CN100336208C/en
Publication of JP2004363379A publication Critical patent/JP2004363379A/en
Pending legal-status Critical Current

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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which breakdown due to thermal stress is prevented. <P>SOLUTION: This semiconductor device 10A has a structure in which it is provided with a supporting substrate 11, a front surface electrode 13 and a rear surface electrode 14 which are formed on the front and rear surfaces of the supporting substrate 11 and connected via a penetrating section 15, a semiconductor element 16 firmly fixed on the surface of the supporting substrate 11 and electrically connected to the surface electrode 13, and a sealing resin 18 for sealing the semiconductor element 16. A groove 12 is provided on the rear surface of the supporting substrate 11. Accordingly, cracks due to thermal stress can be prevented from being generated on a connecting portion between the penetrating portion 15 and the surface electrode 14, or a connecting portion between the penetrating portion 15 and the rear surface electrode 14. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、支持基板を有する半導体装置に関する。
【０００２】
【従来の技術】
図５を参照して、従来型の実装基板および半導体装置装置に関して説明する。図５（Ａ）は半導体装置１００の断面図であり、図５（Ｂ）はその裏面図である（特許文献１参照）。
【０００３】
図５（Ａ）を参照して、ガラスエポキシ等から成る支持基板１０１の上面に銅箔等から成る電極１０４が形成されている。また支持基板１０１の裏面には裏面電極１０５が形成され、ビアホール１０６により電極１０４と接続されている。また、電極１０４および裏面電極１０５はメッキ膜により被覆されている。
【０００４】
半導体素子１０２は支持基板１０１上に固着され、金属細線１０３により電極１０４と接続される。また半導体素子１０２を被覆するように封止樹脂１０７が形成されている。
【０００５】
図５（Ｂ）を参照して、支持基板１０１の裏面には、外周部と平行に２列に整列して、裏面電極１０５が設けられている。
【０００６】
【特許文献１】
特開平１１−２３３６８８号公報（図７参照）
【０００７】
【発明が解決しようとする課題】
上述した半導体装置１００では、裏面電極１０５に形成されるロウ材を介して実装基板に実装される。しかしながら、半導体装置１００に内蔵される半導体素子１０２と、実装基板とでは熱膨張係数が大きく異なるので、温度変化により熱応力が発生する。従来では、この熱応力の緩和を支持基板１０１やロウ材が担ってきた。しかしながら、支持基板１０１による熱応力の緩和を促進させるためには、支持基板１０１を厚く形成する必要があり、このことが半導体装置の薄型化を阻害していた。更に、熱応力が作用することにより、ビアホール１０６と電極１０４との接続部を含む接続経路が破壊されてしまう問題があった。
【０００８】
本発明は上記した問題点を鑑みて成されたものであり、本発明の主な目的は、熱応力による破壊を防止した半導体装置を提供することにある。
【０００９】
【課題を解決するための手段】
本発明は、支持基板と、前記支持基板の表面および裏面に形成されて貫通部により接続された表面電極および裏面電極と、前記支持基板の表面に固着されて前記表面電極と電気的に接続された半導体素子と、前記半導体素子を封止する封止樹脂とを具備し、前記支持基板の裏面には溝が設けられることを特徴とする。
【００１０】
更に本発明は、前記裏面電極は前記支持基板の裏面にマトリックス状に形成され、前記溝は前記裏面電極の間に格子状に設けられることを特徴とする。
【００１１】
更に本発明は、前記溝は、前記裏面電極間の中間部に形成されることを特徴とする。
【００１２】
更に本発明は、前記裏面電極にロウ材を付着することにより、実装基板に実装されることを特徴とする。
【００１３】
【発明の実施の形態】
図１を参照して、本発明の半導体装置１０の構成を説明する。図１（Ａ）は半導体装置１０の断面図であり、図１（Ｂ）はその裏面図である。
【００１４】
図１（Ａ）を参照して、本発明の半導体装置１０Ａは、支持基板１１と、支持基板の表面および裏面に形成されて貫通部１５により接続された表面電極１３および裏面電極１４と、支持基板１１の表面に固着されて表面電極１３と電気的に接続された半導体素子１６と、半導体素子１６を封止する封止樹脂１８とを具備し、支持基板１１の裏面には溝１２が設けられる構成と成っている。これら各要素の詳細を以下にて説明する。
【００１５】
支持基板１１は、半導体装置１０の各構成要素を支持する働きを有し、例えばガラスエポキシ基板から成る。また、支持基板１１の材料としてはガラスエポキシ基板以外でも良く、他の有機材料をその材料とすることもできる。また、ここでは、支持基板１１は、単層の配線構造を有するが、多層の配線構造を構成する支持基板１１が構成されても良い。
【００１６】
表面電極１３は導電性の材料から成り、支持基板１１の表面に形成される。表面電極１３は、金属細線１７が接続されるパッド部を形成し、更に、半導体素子１６の下方に引き回される配線部も構成している。
【００１７】
裏面電極１４は、支持基板１１の裏面に形成され、支持基板１１を貫通する貫通部１５を介して表面電極１３と電気的に接続されている。
【００１８】
半導体素子１６は、ＬＳＩ（Ｌａｒｇｅ Ｓｃａｌｅ Ｉｎｔｅｇｒａｔｉｏｎ）チップであり、フェイスアップで、接着剤１９を介して支持基板１１の表面に固着されている。そして、半導体素子１６の取り出し電極と表面電極１３とは、金属細線１７を介して電気的に接続されている。また、半導体素子以外の素子が半導体装置１０に内蔵されても良い。
【００１９】
封止樹脂１８は、半導体素子１６、金属細線１７、および、支持基板１１の表面を被覆している。また、封止樹脂１８は、機械的強度の向上および耐湿性の向上のために、無機フィラーが混入された遮光性のものを採用することができる。封止樹脂１８に用いる樹脂としては、熱可塑性樹脂または熱硬化性樹脂の両方を全般的に採用することができる。
【００２０】
溝１２は、支持基板１１の裏面をハーフスクライブすることにより形成され、裏面電極１４間の中間部付近に設けられる。図１（Ｂ）を参照して、裏面電極１４は、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）やＬＧＡ（Ｌａｎｄ Ｇｒｉｄ Ａｒｒａｙ）構造が実現できるように、マトリックス状に形成されている。そして、溝１２は、各行および各列の裏面電極１４の間に、格子状に形成されている。
【００２１】
図２を参照して、上記した半導体素子１４の実装構造を説明する。図２（Ａ）を参照して、実装基板２０の表面には導電路２１が形成されている。そして、裏面電極１４の裏面に付着されたロウ材２２を介して、実装基板２０の導電路２１と半導体装置１０とは接続されている。ここで、ロウ材２２としては、半田等を採用することができる。
【００２２】
半導体装置１０に内蔵される半導体素子１６と、実装基板２０とでは、熱膨張係数が大きく相違する。具体的には、半導体素子１６の熱膨張係数は２ｐｐｍ程度であり、実装基板２０が樹脂製のものである場合はその熱膨張係数は２０ｐｐｍ程度である。従って、使用状況下の温度変化により、半導体装置１０および実装基板２０が加熱された場合、半導体素子１６より実装基板２０の方が大きな膨張量を示す。従って、半導体素子１６と実装基板２０との間に介在する、導電路２１、ロウ材２２、裏面電極１４、貫通部１５、支持基板１１、および、表面電極１３には熱応力が発生する。本発明では、支持基板１１に溝１２を設けることにより、この熱応力を低減している。
【００２３】
図２（Ｂ）を参照して、溝１２の詳細を説明する。上述したように、半導体素子１６の熱膨張係数は、実装基板の１０分の１程度である。従って、半導体素子１６と実装基板２０の両方が温度上昇した場合、半導体素子１６に比べて実装基板２０が大きく膨張することから、支持基板１１や貫通部１５に大きな熱応力が発生する。具体的には、支持基板１１や貫通部１５に横方向の剪断力が作用する。本発明では、支持基板１１に溝を設けて、裏面電極１４が形成される箇所の近傍の支持基板を可動にすることにより、支持基板１１や貫通部１５に作用する熱応力を低減させている。同図を参照して、溝１２が設けられた箇所の支持基板１１は、右方向に変形している。このように、熱応力が作用した際に、裏面電極１４が設けられた箇所の支持基板１１を横方向に可動にするために、溝１２は形成されている。支持基板１１を部分的に可動にすることにより、貫通部１５と表面電極１３との接続箇所、または、貫通部１５と裏面電極１４との接続箇所が剥離してしまうのを防止することができる。
【００２４】
また、半導体装置１０と実装基板２０との間に大きな熱応力が作用した場合でも、裏面電極１４付近の支持基板が横方向に可動であることで、その熱応力は吸収される。更にまた、従来の半導体装置では、上記した熱応力を吸収するために、支持基板を厚く形成していたが、本発明の構成により、支持基板１１を薄くすることができる。上記の説明では、溝１２は支持基板１１の厚みの途中まで設けられるが、支持基板１１が分離される程度の深さまで溝１２を形成しても良い。
【００２５】
図３を参照して、他の形態の半導体装置１０Ｂの構成を説明する。半導体装置１０Ｂの基本的な構成は、図１を参照して説明した半導体装置と同様であり、相違点は、半導体素子１６がフェイスダウンでフリップチップ実装されている点にある。この様な構成を有する半導体装置１０Ｂの場合でも、上記した溝１２の形成による効果を奏することができる。
【００２６】
図４を参照して、半導体装置１０Ｂの製造方法を説明する。図４（Ａ）を参照して、支持基板の１１の表面および裏面に、表面電極１３および裏面電極１４を形成する。表面電極１３及び裏面電極１４は、支持基板１１を貫通して形成された貫通部１５により電気的に接続されている。
【００２７】
図４（Ｂ）を参照して、接着剤１９を介して半導体素子１６の固着を行い、半導体素子１６の電極と表面電極１４とを、金属細線１７により電気的に接続する。
【００２８】
図４（Ｃ）を参照して、半導体素子１６および金属細線１７が被覆されるように、封止樹脂１８を形成する。封止樹脂１８の形成方法としては、トランスファーモールド、インジェクションモールド、ポッティング等が考えられる。
【００２９】
図４（Ｄ）を参照して、ダイシングブレードを用いて支持基板１１の裏面をハーフスクライブすることにより、溝１２を形成する。溝１２の深さは、支持基板１１の厚みよりも浅く形成する。そして、各半導体装置の境界線で封止樹脂１８および支持基板１１を分割することにより、例えば図１に示すような半導体装置１０が完成する。ここで、溝１２の形成は、図４（Ａ）に示す工程で行っても良い。また、ダイシング以外の方法により溝１２の形成を行っても良い。具体的には、エッチングやレーザー等の除去方法により溝１２の形成を行うことができる。
【００３０】
【発明の効果】
本発明では、以下に示すような効果を奏することができる。
【００３１】
支持基板１１の裏面に溝１２を形成したので、半導体素子１６と実装基板２０の熱膨張係数の差により支持基板１１に熱応力が作用した場合でも、支持基板１１を部分的に可動にすることにより、発生する熱応力を低減させることができる。従って、熱応力により、貫通部１５と表面電極１４との接続箇所、または、貫通部１５と裏面電極１４との接続箇所にクラックが発生してしまうのを防止することができる。
【００３２】
更に、溝１２が設けられた支持基板１１により、熱応力の吸収を行うので、半導体装置１０と実装基板２０とを接続するロウ材２２に作用する応力を緩和することができる。
【００３３】
更に、溝１２を支持基板１１に設けることにより、半導体装置１０を実装する際にロウ材２２同士が短絡するのを防止することができる。従って、ソルダーレジストの形成をせずとも、ろう材２２の短絡を防止することができる。
【図面の簡単な説明】
【図１】本発明の半導体装置を説明する断面図（Ａ）、裏面図（Ｂ）である。
【図２】本発明の半導体装置を説明する断面図（Ａ）、断面拡大図（Ｂ）である。
【図３】本発明の半導体装置を説明する断面図である。
【図４】本発明の半導体装置の製造方法を説明する断面図（Ａ）−（Ｄ）である。
【図５】従来の半導体装置を説明する断面図（Ａ）、裏面図（Ｂ）である。
【符号の説明】
１０ 半導体装置
１１ 支持基板
１２ 溝
１３ 表面電極
１４ 裏面電極
１５ 貫通部
１６ 半導体素子
１７ 金属細線
１８ 封止樹脂
１９ 接着剤
２０ 実装基板
２１ 導電路[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a support substrate.
[0002]
[Prior art]
With reference to FIG. 5, a conventional mounting substrate and a semiconductor device will be described. FIG. 5A is a cross-sectional view of the semiconductor device 100, and FIG. 5B is a rear view thereof (see Patent Document 1).
[0003]
Referring to FIG. 5A, an electrode 104 made of copper foil or the like is formed on the upper surface of a support substrate 101 made of glass epoxy or the like. A back surface electrode 105 is formed on the back surface of the support substrate 101, and is connected to the electrode 104 through a via hole 106. The electrode 104 and the back electrode 105 are covered with a plating film.
[0004]
The semiconductor element 102 is fixed on a support substrate 101 and connected to an electrode 104 by a thin metal wire 103. Further, a sealing resin 107 is formed so as to cover the semiconductor element 102.
[0005]
Referring to FIG. 5B, on the back surface of supporting substrate 101, back electrodes 105 are provided in two rows in parallel with the outer peripheral portion.
[0006]
[Patent Document 1]
JP-A-11-233688 (see FIG. 7)
[0007]
[Problems to be solved by the invention]
In the above-described semiconductor device 100, the semiconductor device 100 is mounted on the mounting board via the brazing material formed on the back surface electrode 105. However, since the semiconductor element 102 incorporated in the semiconductor device 100 and the mounting substrate have significantly different coefficients of thermal expansion, thermal stress occurs due to a change in temperature. Conventionally, the support substrate 101 and the brazing material have been responsible for relaxing this thermal stress. However, in order to promote the relaxation of thermal stress by the support substrate 101, it is necessary to form the support substrate 101 thick, which hinders the thinning of the semiconductor device. Further, there is a problem that a connection path including a connection portion between the via hole 106 and the electrode 104 is broken due to a thermal stress.
[0008]
The present invention has been made in view of the above problems, and a main object of the present invention is to provide a semiconductor device in which destruction due to thermal stress is prevented.
[0009]
[Means for Solving the Problems]
The present invention provides a support substrate, a front surface electrode and a back surface electrode formed on the front surface and the back surface of the support substrate and connected by a penetrating portion, and fixed to the surface of the support substrate and electrically connected to the front electrode. And a sealing resin for sealing the semiconductor element, wherein a groove is provided on the back surface of the support substrate.
[0010]
Further, the present invention is characterized in that the back electrodes are formed in a matrix on the back surface of the support substrate, and the grooves are provided in a lattice pattern between the back electrodes.
[0011]
Further, the present invention is characterized in that the groove is formed at an intermediate portion between the back electrodes.
[0012]
Furthermore, the present invention is characterized in that the back electrode is mounted on a mounting substrate by attaching a brazing material to the back electrode.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
The configuration of a semiconductor device 10 according to the present invention will be described with reference to FIG. FIG. 1A is a cross-sectional view of the semiconductor device 10, and FIG. 1B is a rear view thereof.
[0014]
Referring to FIG. 1A, a semiconductor device 10A according to the present invention includes a support substrate 11, a front electrode 13 and a back electrode 14 formed on the front and back surfaces of the support substrate and connected by through-holes 15, and The semiconductor device includes a semiconductor element fixed to the surface of the substrate and electrically connected to the front electrode, and a sealing resin for sealing the semiconductor element. Configuration. Details of each of these elements will be described below.
[0015]
The support substrate 11 has a function of supporting each component of the semiconductor device 10, and is made of, for example, a glass epoxy substrate. Further, the material of the support substrate 11 may be other than the glass epoxy substrate, and another organic material may be used as the material. Although the support substrate 11 has a single-layer wiring structure here, the support substrate 11 having a multilayer wiring structure may be configured.
[0016]
The surface electrode 13 is made of a conductive material and is formed on the surface of the support substrate 11. The surface electrode 13 forms a pad portion to which the thin metal wire 17 is connected, and also forms a wiring portion that is routed below the semiconductor element 16.
[0017]
The back surface electrode 14 is formed on the back surface of the support substrate 11 and is electrically connected to the front surface electrode 13 through a penetrating portion 15 penetrating the support substrate 11.
[0018]
The semiconductor element 16 is an LSI (Large Scale Integration) chip, and is fixed to the surface of the support substrate 11 via an adhesive 19 in a face-up manner. The extraction electrode of the semiconductor element 16 and the surface electrode 13 are electrically connected via a thin metal wire 17. Further, an element other than the semiconductor element may be built in the semiconductor device 10.
[0019]
The sealing resin 18 covers the surfaces of the semiconductor element 16, the fine metal wires 17, and the support substrate 11. Further, as the sealing resin 18, a light-shielding resin mixed with an inorganic filler can be employed in order to improve mechanical strength and moisture resistance. As the resin used for the sealing resin 18, both a thermoplastic resin and a thermosetting resin can be generally employed.
[0020]
The groove 12 is formed by half-scribed the back surface of the support substrate 11, and is provided near an intermediate portion between the back electrodes 14. Referring to FIG. 1B, the back surface electrode 14 is formed in a matrix so that a BGA (Ball Grid Array) or LGA (Land Grid Array) structure can be realized. The grooves 12 are formed in a lattice shape between the back electrodes 14 in each row and each column.
[0021]
With reference to FIG. 2, the mounting structure of the semiconductor element 14 will be described. Referring to FIG. 2A, conductive paths 21 are formed on the surface of mounting substrate 20. The conductive path 21 of the mounting substrate 20 and the semiconductor device 10 are connected via the brazing material 22 attached to the back surface of the back electrode 14. Here, solder or the like can be adopted as the brazing material 22.
[0022]
The semiconductor element 16 incorporated in the semiconductor device 10 and the mounting substrate 20 have significantly different coefficients of thermal expansion. Specifically, the thermal expansion coefficient of the semiconductor element 16 is about 2 ppm, and when the mounting substrate 20 is made of resin, the thermal expansion coefficient is about 20 ppm. Therefore, when the semiconductor device 10 and the mounting substrate 20 are heated due to a temperature change under a use condition, the mounting substrate 20 exhibits a larger expansion amount than the semiconductor element 16. Therefore, thermal stress is generated in the conductive path 21, the brazing material 22, the back electrode 14, the penetrating portion 15, the support substrate 11, and the front electrode 13 interposed between the semiconductor element 16 and the mounting board 20. In the present invention, the thermal stress is reduced by providing the groove 12 in the support substrate 11.
[0023]
The details of the groove 12 will be described with reference to FIG. As described above, the thermal expansion coefficient of the semiconductor element 16 is about one-tenth of the mounting substrate. Therefore, when the temperature of both the semiconductor element 16 and the mounting board 20 rises, the mounting board 20 expands significantly as compared with the semiconductor element 16, so that a large thermal stress is generated in the support substrate 11 and the penetrating portion 15. Specifically, a lateral shearing force acts on the support substrate 11 and the penetrating portion 15. In the present invention, the thermal stress acting on the support substrate 11 and the penetrating portion 15 is reduced by providing a groove in the support substrate 11 and making the support substrate in the vicinity of the location where the back electrode 14 is formed movable. . Referring to FIG. 3, support substrate 11 at a location where groove 12 is provided is deformed rightward. As described above, the groove 12 is formed so that the support substrate 11 at the position where the back electrode 14 is provided can be moved in the lateral direction when a thermal stress is applied. By making the support substrate 11 partially movable, it is possible to prevent the connection portion between the through portion 15 and the front surface electrode 13 or the connection portion between the through portion 15 and the back surface electrode 14 from peeling off. .
[0024]
Even when a large thermal stress acts between the semiconductor device 10 and the mounting substrate 20, the thermal stress is absorbed by the support substrate in the vicinity of the back electrode 14 being movable in the lateral direction. Furthermore, in the conventional semiconductor device, the supporting substrate is formed thick in order to absorb the above-mentioned thermal stress. However, according to the configuration of the present invention, the supporting substrate 11 can be made thin. In the above description, the groove 12 is provided halfway through the thickness of the support substrate 11, but the groove 12 may be formed to such a depth that the support substrate 11 is separated.
[0025]
With reference to FIG. 3, a configuration of a semiconductor device 10B of another embodiment will be described. The basic configuration of the semiconductor device 10B is the same as that of the semiconductor device described with reference to FIG. 1, except that the semiconductor element 16 is flip-chip mounted face down. Even in the case of the semiconductor device 10 </ b> B having such a configuration, the effect of the formation of the groove 12 can be obtained.
[0026]
With reference to FIG. 4, a method for manufacturing the semiconductor device 10B will be described. Referring to FIG. 4A, a front surface electrode 13 and a back surface electrode 14 are formed on the front surface and the back surface of the support substrate 11, respectively. The front surface electrode 13 and the back surface electrode 14 are electrically connected by a penetrating portion 15 formed through the support substrate 11.
[0027]
Referring to FIG. 4B, semiconductor element 16 is fixed via adhesive 19, and the electrode of semiconductor element 16 and surface electrode 14 are electrically connected by thin metal wire 17.
[0028]
Referring to FIG. 4C, sealing resin 18 is formed so as to cover semiconductor element 16 and thin metal wires 17. As a method of forming the sealing resin 18, transfer molding, injection molding, potting, and the like can be considered.
[0029]
Referring to FIG. 4D, grooves 12 are formed by half-scribe the back surface of support substrate 11 using a dicing blade. The depth of the groove 12 is formed smaller than the thickness of the support substrate 11. Then, by dividing the sealing resin 18 and the support substrate 11 at the boundary of each semiconductor device, for example, the semiconductor device 10 as shown in FIG. 1 is completed. Here, the formation of the groove 12 may be performed in a step shown in FIG. The grooves 12 may be formed by a method other than dicing. Specifically, the groove 12 can be formed by a removing method such as etching or laser.
[0030]
【The invention's effect】
According to the present invention, the following effects can be obtained.
[0031]
Since the groove 12 is formed on the back surface of the support substrate 11, the support substrate 11 can be partially movable even when a thermal stress acts on the support substrate 11 due to a difference in thermal expansion coefficient between the semiconductor element 16 and the mounting substrate 20. Thereby, the generated thermal stress can be reduced. Therefore, it is possible to prevent the occurrence of cracks at the connection portion between the through portion 15 and the front electrode 14 or at the connection portion between the through portion 15 and the back surface electrode 14 due to thermal stress.
[0032]
Further, since the thermal stress is absorbed by the support substrate 11 in which the groove 12 is provided, the stress acting on the brazing material 22 connecting the semiconductor device 10 and the mounting substrate 20 can be reduced.
[0033]
Further, by providing the groove 12 in the support substrate 11, it is possible to prevent short-circuit between the brazing materials 22 when the semiconductor device 10 is mounted. Therefore, a short circuit of the brazing material 22 can be prevented without forming a solder resist.
[Brief description of the drawings]
FIGS. 1A and 1B are a cross-sectional view and a rear view, respectively, illustrating a semiconductor device of the present invention.
2A and 2B are a cross-sectional view and a cross-sectional enlarged view illustrating a semiconductor device of the present invention.
FIG. 3 is a cross-sectional view illustrating a semiconductor device of the present invention.
4A to 4D are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention.
5A and 5B are a cross-sectional view and a rear view, respectively, illustrating a conventional semiconductor device.
[Explanation of symbols]
REFERENCE SIGNS LIST 10 semiconductor device 11 support substrate 12 groove 13 front electrode 14 back electrode 15 penetrating portion 16 semiconductor element 17 thin metal wire 18 sealing resin 19 adhesive 20 mounting substrate 21 conductive path

Claims (4)

支持基板と、前記支持基板の表面および裏面に形成されて貫通部により接続された表面電極および裏面電極と、前記支持基板の表面に固着されて前記表面電極と電気的に接続された半導体素子と、前記半導体素子を封止する封止樹脂とを具備し、
前記支持基板の裏面には溝が設けられることを特徴とする半導体装置。A support substrate, a front surface electrode and a back surface electrode formed on the front surface and the back surface of the support substrate and connected by a through portion, and a semiconductor element fixed to the surface of the support substrate and electrically connected to the front electrode. And a sealing resin for sealing the semiconductor element,
A semiconductor device, wherein a groove is provided on a back surface of the support substrate. 前記裏面電極は前記支持基板の裏面にマトリックス状に形成され、前記溝は前記裏面電極の間に格子状に設けられることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the back surface electrodes are formed in a matrix on the back surface of the support substrate, and the grooves are provided in a lattice pattern between the back surface electrodes. 3. 前記溝は、前記裏面電極間の中間部に形成されることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the groove is formed at an intermediate portion between the back electrodes. 前記裏面電極にロウ材を付着することにより、実装基板に実装されることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the semiconductor device is mounted on a mounting substrate by attaching a brazing material to the back surface electrode.
JP2003160892A 2003-06-05 2003-06-05 Semiconductor device Pending JP2004363379A (en)

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