TWI223876B - Method of fabricating a self-aligned contact opening and structure of interconnects and fabricating method thereof - Google Patents

Abstract

A method of fabricating a self-aligned contact opening is described. A substrate having a gate dielectric layer, a gate conductive layer and a cap layer thereon is provided. A passivation layer is formed on the cap layer, wherein the removal rate of the passivation layer is smaller than that of the cap layer. The passivation layer, the cap layer, and the gate conductive layer are patterned to form several gate structures. A spacer is formed on the sidewalls of the gate structures. A dielectric layer is formed to cover the gate structures and the passivation layer. The dielectric layer is patterned to form a self-aligned contact opening. Since the passivation layer, whose removal rate is small, covers the top of the gate structure, it can avoid the gate conductive layer being exposed during the dielectric layer is patterned.

Description

1223876 V. Description of the invention (l)-[Technical field to which the invention belongs] The present invention relates to a semiconductor element and a manufacturing method thereof, and more particularly to a manufacturing method for self-aligning a contact window opening and manufacturing of an interconnector. Method and its structure. [Previous technology] At present, the resolution of the ultra large integrated circuit (ULSI) process has developed to less than 18 microns, that is, the ratio of depth to width or diameter is getting larger and the contact windows of metals and semiconductors are getting smaller. Therefore, how to overcome the ever-smaller line width and prevent misalignment of contact windows (Misa ignment) has become the focus of research and development in the semiconductor industry. In order to overcome the ever-smaller line width and prevent misalignment of the contact window, many semiconductor devices usually adopt a self-aligned contact (SAC) design. In addition, J is, if you want The electrical connection between the doped region in the substrate and the wire structure formed above the substrate can be achieved by designing a self-aligned contact window. FIG. 1A to FIG. 1D are cross-sectional schematic diagrams showing the manufacturing process of a conventional self-aligned contact window. Referring to FIG. 1A, a substrate 100 is provided. A plurality of gate structures 1 10 having a cap layer 1 08 have been formed on the substrate 100, and each gate structure 1 1 0 further includes a gate. The dielectric layer 102, the polycrystalline silicon layer 104, and the silicided metal layer 106 are the polysilicon layer 104 and the silicided metal layer 106 are gate conductive layers. Next, referring to FIG. 1B, a gap wall 1 12 is formed on a sidewall of the gate structure 110. After that, please refer to FIG. 1C, and deposit a silicon oxide dielectric on the substrate 100.

11858t.wf.ptd Page 6 1223876 V. Description of the invention (2)-Layer 1 1 4 to cover the gate structure 1 1 0. Then, the dielectric layer 1 1 4 is patterned to form a self-aligned contact window opening 1 1 6 between two adjacent gate structures 110. Then, a conductive material is filled to form a self-aligned contact window 1 1 8 (as shown in FIG. 1D). However, in the process of forming the self-aligned contact window opening 1 16, the etching selection ratio of the silicon oxide dielectric layer 1 14 to the silicon nitride top cap layer 108 is not sufficiently high (about 10 to 20). Therefore, in the process of patterning the dielectric layer 114, the gate conductive layer (polycrystalline silicon layer 104 and silicided metal layer 106) may be caused by the gradual removal of the cap layer 108. Is exposed (as shown in FIG. 1C), so that the self-aligned contact window 11 18 and the exposed gate conductive layer (polycrystalline silicon layer 104 and silicided metal layer 106) formed in the subsequent process will be short-circuited ( (As shown in Figure 1 D). [Summary of the Invention] In view of this, the object of the present invention is to provide a method for manufacturing a self-aligned contact window opening, a method for manufacturing an interconnect, and a structure thereof, so as to solve the conventional problem between adjacent gate structures. During the self-aligned contact window opening process, the gate conductive layer may be exposed due to the insufficient etching selection ratio of the dielectric layer to the cap layer, which may cause a short circuit problem. The invention proposes a method for manufacturing a self-aligned contact window opening. This method first provides a substrate on which a gate dielectric layer, a gate conductive layer and a cap layer have been formed. Thereafter, a protective layer is formed on the top cap layer, wherein the removal rate of the protective layer is lower than that of the top cap layer. Then, the protection layer, the cap layer and the gate conductive layer are patterned to form a plurality of gate structures covered with the protection layer. A spacer is then formed on the sidewalls of these gate structures. Succeed

1 1858t.wf.ptd Page 7 1223876 V. Description of the invention (3) ^ A dielectric layer is formed over the substrate to cover these gate structures and protection layers. Subsequently, the dielectric layer is patterned to form a self-aligned contact window opening between two adjacent gate structures. Because in the manufacturing method of the self-aligned contact window opening of the present invention, the gate structure is covered with a protective layer having a lower removal rate than the top cap layer, the protective layer is better than the conventional one when patterning the dielectric layer. The cap layer is more difficult to remove. Therefore, the problem that the gate conductive layer may be exposed during the process of patterning the dielectric layer can be solved, so that the problem of a short circuit with the gate conductive layer in the self-aligned contact window formed later can be avoided. . The present invention provides a method for manufacturing an interconnect. This method first provides a substrate on which a gate dielectric layer, a gate conductive layer, and a cap layer have been formed. After that, a protective layer is formed on the top cap layer, wherein the removal rate of the protective layer is lower than the removal rate of the top cap layer. Next, the protective layer, the cap layer and the gate conductive layer are patterned to form a plurality of gate structures covered with the protective layer. Then, a spacer wall is formed on the side walls of these gate structures. Next, a dielectric layer is formed over the substrate to cover these gate structures and protective layers. Subsequently, a dielectric layer is patterned to form a self-aligned contact window opening between two adjacent gate structures. Then, a conductive material is filled in the self-aligning contact window opening to form a self-aligning contact window. A wire structure is then formed on the dielectric layer to cover the self-aligned contact window. In the manufacturing method of the interconnects of the present invention, the gate structure is covered with a protective layer having a lower removal rate than the cap layer. Therefore, when the dielectric layer is patterned, the protective layer is higher than the conventional cap layer. More difficult to remove. Therefore, the gate conductive layer can be solved during the process of patterning the dielectric layer.

11858t.wf.ptd Page 8 1223876 V. Description of the Invention (4) > The problem of being exposed may be avoided, so the problem of self-aligning the contact window with the gate conductive layer may be avoided. In addition, the above-mentioned manufacturing method can be applied to a memory device in addition to the interconnection process of a general device, so that the doped regions in the substrate can be self-aligned with the contact window and the upper bit line. Sexual connection. The invention provides an interconnect structure. The structure includes a plurality of gate structures, a protective layer, a barrier wall, a dielectric layer, a self-aligned contact window and a wire structure. The gate structures include a gate dielectric layer and a gate. Electrode conductive layer and cap layer. The gate structures are arranged on a substrate. In addition, a protective layer is placed on top of these gate structures. In addition, the partition wall is disposed on the side wall of these gate structures. In addition, the dielectric layer covers the protective layer, the substrate, and these gate structures. In addition, the self-aligned contact window is disposed in the dielectric layer between two adjacent gate structures, wherein the self-aligned contact window is adjacent to the protective layer. In addition, the wire structure is disposed on the dielectric layer, and the wire structure is electrically connected to the self-aligned contact window. In the interconnect structure of the present invention, a protective layer is covered above the gate structure. The configuration of the protective layer can protect the gate structure and avoid self-alignment of the contact window and the gate during the patterning of the dielectric layer. The electrodes are in contact with each other and cause a short circuit. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to describe in detail as follows: [Embodiment] Figure 2A to FIG. 2E illustrates a structure according to a preferred embodiment of the present invention.

11858t.wf. Pt.d Page 9 1223876 V. Description of the Invention (5) · A cross-sectional schematic diagram of the manufacturing process of an interconnect. Referring to FIG. 2A, the method for manufacturing the interconnects of the present invention first provides a substrate 200, and a gate dielectric layer 202, a gate conductive layer 206, and a cap layer 208 have been formed on the substrate 200. The material of the gate dielectric layer 202 is, for example, silicon oxide. The gate conductive layer 206 is composed of, for example, a polycrystalline silicon layer 204 and a silicide metal layer 205, and the material of the silicide metal layer 205 is, for example, tungsten silicide or titanium silicide. The material of the cap layer 208 is, for example, silicon nitride. After that, please continue to refer to FIG. 2A to form a protective layer 2 10 on the top cover layer 208. The removal rate of the protective layer 210 is lower than the removal rate of the cap layer 208. The material of the protective layer 2 10 is, for example, a metal material, and the metal material is, for example, tungsten, tungsten nitride, or titanium nitride. A method for forming the protective layer 210 is, for example, a chemical vapor deposition method. Next, referring to FIG. 2B, the patterned protective layer 2 1 0, the cap layer 2 ◦ 8, the gate conductive layer 2 6 and the gate dielectric layer 2 0 2 are formed to form a plurality of protective layers 2 1 Gate structure of 0 a 2 1 2. Among them, the gate structure 2 1 2 includes a patterned cap layer 208 a, a gate conductive layer 206 a, and a gate dielectric layer 202 a, and the gate conductive layer 2 6 a is composed of a polycrystalline silicon layer 2 0 4 a and silicidation. Consists of a metal layer 2 0 5 a. In addition, in another preferred embodiment, this patterning step is performed to the gate conductive layer 206a, while the lower gate dielectric layer 202 is retained. The gate dielectric layer 202 is removed in a subsequent step of forming a self-aligned contact window opening, so that the substrate 200 is exposed. Then, please continue to refer to FIG. 2B to form a partition wall 2 1 4 on the side wall of the gate structure 2 1 2. Among them, the method of forming the partition wall 2 1 4 is to firstly

1 1858t.wf. Pt.d Page 10 1223876 V. Description of the invention (6) · A conformal spacer material layer (not shown) is formed on 2 0 0. The material of this spacer material layer is, for example, silicon nitride. . Then, this spacer material layer is anisotropically etched to form the spacer 2 1 4. Subsequently, referring to FIG. 2C, a part of the protective layer 2 10a is removed, so as to retain the predetermined protective layer 210b at the opening of the self-aligned contact window. In another preferred embodiment, the step of removing a part of the protective layer 21a is omitted, and the original protective layer 2ia of FIG. 2B is retained. Then, please continue to refer to FIG. 2C to form a dielectric layer 2 16 on the substrate 200 to cover the gate structure 2 12 and the protective layer 2 1 b. The material of the dielectric layer 2 1 6 is, for example, silicon oxide. In a preferred embodiment, the dielectric layer 2 1 6 is composed of an undoped silica glass layer (silicon oxide) and a doped silica glass layer (borophosphosilicate glass) to form the dielectric layer 2 1 6 For example, a borophosphosilicate glass is first formed by a chemical vapor deposition method to cover the gate structure 2 1 2 and the protective layer 2 1 0 b. After that, silicon oxide is formed on the borophosphosilicate glass by chemical vapor deposition. Among them, the reaction gas of the silicon oxide dielectric layer is, for example, tetra-ethyl-ortho-silicate (TEOS) ° It is particularly worth mentioning that the protective layer 2 1 0 b and the dielectric layer 2 There is a high etching selection ratio between 16. Also, the ratio of the removal rate of the dielectric layer 2 16 to the protective layer 2 10 b is larger than the ratio of the removal rate of the dielectric layer 216 to the cap layer 208a. In a preferred embodiment, the ratio of the removal rate of the dielectric layer 2 16 to the protective layer 2 1 0 b is, for example, greater than 30, and the shift of the dielectric layer 2 16 to the cap layer 2 0 8 a The ratio of the division rate is, for example, between 10 and 20. Subsequently, referring to FIG. 2D, the dielectric layer 2 1 6 is patterned to form a self-aligned contact window opening 2 1 8 between two adjacent gate structures 2 1 2. its

ll858t.wf.ptd Page 11 1223876 5. In the description of the invention (7) *, the method of patterning the dielectric layer 2 1 6 is, for example, a lithography process and a dry etching process. In addition, it is worth mentioning that because the gate layer 2 1 2 is covered with a protective layer 2 1 0 b, and the etch selectivity ratio of the dielectric layer 2 1 6 to the protective layer 2 1 0 b is greater than the dielectric layer 2 1 6 pairs of capping layers 2 〇8 a I etch selection ratio, so it is known that the gate conductive layer 2 0 6 a (silicided metal layer 2 0 5 a and The problem that the polycrystalline silicon layer 2 0 4 a) is exposed does not occur in the present invention. That is, the protective layer 2 1 0b is more difficult to be etched than the conventional cap layer 2 08a, so the protective layer 2 丨 0b can effectively block the erosion of the etching and play the gate structure under the protection 2 1 2 Therefore, when the patterned dielectric layer 2 16 is performed, the gate structure 2 丨 2 will not be exposed. After that, referring to FIG. 2E, a self-aligning contact window opening 218 is filled with a conductive material to form a self-aligning contact window 2 2 0. Among them, the conductive material is, for example, metal tungsten or polycrystalline silicon, and the filling method of the conductive material is, for example, forming a conductive material on the dielectric layer 2 6a, and the conductive 5 f is fully aligned with the contact window opening. 218 'Remove the conductive material other than the opening 2 1 8 by the back-cut method or the tritium coin lapping method. & Following this: Referring to FIG. 2E, a wire, a, a wire, and a wire structure 2 2 4 are formed on the dielectric layer 2i6a, and are electrically connected to the self-aligned contact window 2 2 0. An example of the method for forming the "2" wire structure is to embed the "two-gold metal-removing process, for example, before the dielectric layer] \ (shown), where this dielectric layer has trenches (not shown). Align the contact window 2 2 0 by yourself. Then, fill the groove material layer (not shown) in the groove standard. The material of the wire material layer is, for example, tungsten.

1223876 V. Description of the invention (8) * or copper and other wire materials. Then, a layer of the wire material other than the trench is removed by a chemical mechanical polishing method. In addition, in another preferred embodiment, the method for forming the wire structure 2 2 4 is, for example, forming a wire material layer (not shown) on the dielectric layer 2 1 6 a to cover the self-aligned contact window 2 2 0. The wire material layer is a wire material such as tungsten or aluminum. Next, a lithographic etching process is performed to define the wiring structure 2 2 4. In the process of forming the self-aligned contact window of the present invention, the gate structure is covered with a protective layer having a lower removal rate than the cap layer, so when patterning the dielectric layer, the protective layer is higher than the conventional one. The cover layer is more difficult to remove. Therefore, the problem that the conductive layer of the gate electrode may be exposed during the process of patterning the dielectric layer can be solved, and the problem that the self-aligned contact window and the conductive layer of the gate electrode can be short-circuited can be avoided. In addition, the above-mentioned manufacturing method can be applied to a memory device in addition to the interconnection process of a general device, so that the doped regions in the substrate can be self-aligned with the contact window and the upper bit line. Sexual connection. If the above process is applied to a memory device, the above-mentioned conductive structure 2 2 4 is a bit line, and the automatic alignment contact window 2 2 0 is a bit line contact window. The following describes the structure obtained by the above method. Please refer to Figure 2E. This structure includes several gate structures 2 1 2, protective layer 2 1 0 b, barrier wall 2 1 4, dielectric layer 2 1 6 a, self-aligned contact window 2 2 0 and wires Structure 2 2 4 and these gate structures 2 1 2 include a gate dielectric layer 2 0 2 a, a polycrystalline silicon layer 204a, a silicided metal layer 205a, and a cap layer 208a, and the polycrystalline silicon layer 204a and the silicided metal layer 2 0 5 a Is gate conductive layer 2 0 6 a.

11858t.wf.ptd Page 13 1223876 V. Description of the invention (9) ′ The gate structures 2 1 2 are arranged on the substrate 2 0 0. In addition, a protective layer 2 1 0 b is disposed on top of these gate structures 2 1 2. The material of the protective layer 2 1 0 b is, for example, a metal material, and the metal material is, for example, hafnium, hafnium nitride, or titanium nitride. In addition, the partition wall 2 1 4 is disposed on a side wall of the gate structures 2 1 2. In addition, the dielectric layer 2 1 6 a covers the protective layer 2 1 0 b, the substrate 2 0 0, and these gate structures 21 2. In addition, the self-aligned contact window 2 2 0 is disposed in the dielectric layer 2 1 6 a between two adjacent gate structures 2 1 2, and the self-aligned contact window 2 2 0 is related to the protective layer 2 1 0 b is adjacent. The self-aligning contact window M 0 is made of a conductive material such as metal tungsten or polycrystalline silicon. In addition, the lead structure 2 2 4 is disposed on the dielectric layer 2 1 6 a, and the lead structure 2 2 4 is electrically connected to the self-aligned contact window 2 2 0. The material of the lead structure 2 2 4 is, for example, a lead material such as tungsten, aluminum, or copper. In the interconnect structure of the present invention, the gate structure is covered with a protective layer, and the configuration of the protective layer can protect the gate structure to avoid exposing the gate conductive layer during the patterning of the dielectric layer. Out, resulting in a self-aligned contact window formed in the subsequent contact with the gate conductive layer and a short circuit. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

1 1858t.wf.ptd Page 14 1223876 Brief description of drawings _ Figures 1 A to 1 D are the conventional manufacturing process of a self-aligning contact window. Figures 2A to 2E are schematic cross-sectional views of a manufacturing process of an interconnect according to a preferred embodiment of the present invention. [Illustration of diagrammatic symbols] 100, 200: substrates 102, 202, 202a: gate dielectric layers 1 0 4, 2 0 4 and 2 0 4 a · polycrystalline silicon layers 1 0 6, 2 0 5, 2 0 5 a: Silicided metal layers 108, 208, and 208a: cap layer 1 1 0, 2 1 2: gate structure 1 1 2, 2 1 4: spacers 114, 216, 216a: dielectric layers 1 1 6 and 2 1 8: Self-align the contact window opening 1 1 8, 2 2 0: Self-align the contact window 2 0 6, 2 0 6 a: Gate conductive layer 2 1 0, 2 1 0 a, 2 1 0 b: Protective layer 2 2 4: lead structure

11858t.wf.ptd Page 15

Claims (1)

1223876 VI. Scope of patent application1. A method for manufacturing self-aligning contact window openings, comprising: providing a substrate on which a gate dielectric layer, a gate conductive layer and a cap layer have been formed; A protective layer is formed on the capping layer, wherein the removal rate of the protective layer is lower than that of the capping layer; the protective layer, the capping layer, and the gate conductive layer are patterned to form a cover layer A plurality of gate structures; forming a gap wall on the side walls of the gate structures; forming a dielectric layer over the substrate to cover the gate structures and the protective layer; and patterning the dielectric layer, A self-aligned contact window opening is formed between two adjacent gate structures to expose the surface of the substrate. 2. The method for manufacturing a self-aligned contact window opening as described in item 1 of the scope of patent application, wherein the ratio of the removal rate of the dielectric layer to the protective layer is greater than 30. 3. The method for manufacturing a self-aligned contact window opening as described in item 1 of the scope of the patent application, wherein the ratio of the removal rate of the dielectric layer to the top cover layer is between 10 and 20. 4. The method for manufacturing a self-aligning contact window opening as described in item 1 of the scope of patent application, wherein the material of the protective layer includes a metal material. 5. The method for manufacturing a self-aligned contact window opening as described in item 4 of the scope of patent application, wherein the metal material is selected from one of hafnium, iron nitride and titanium nitride. 6. Self-aligning contact window opening as described in item 1 of the scope of patent application 11858t.wf.ptd Page 16 1223876 6. The manufacturing method of patent application scope, wherein after the step of forming the gap wall on the side walls of the gate structures, and before the step of forming the dielectric layer over the substrate, It further includes removing a portion of the protection layer to retain the protection layer at a predetermined self-aligned contact window opening. 7. The method for manufacturing a self-aligned contact window opening as described in item 1 of the scope of patent application, wherein in the step of patterning the protective layer, the cap layer, and the gate conductive layer, the method further includes patterning the The dielectric layer is gated to expose the surface of the substrate. 8. A method for manufacturing interconnects, comprising: providing a substrate on which a gate dielectric layer, a gate conductive layer and a capping layer have been formed; and forming a protective layer on the capping layer, The removal rate of the protective layer is less than the removal rate of the cap layer; patterning the protective layer, the cap layer, and the gate conductive layer to form a plurality of gate structures covered with the protective layer; A side wall of the gate structures forms a gap wall; a dielectric layer is formed over the substrate to cover the gate structures and the protective layer, and the dielectric layer is patterned so that two of the adjacent ones A self-aligned contact window opening is formed between the gate structures, exposing the substrate surface; a conductive material is filled in the self-aligned contact window opening to form a self-aligned contact window; and the dielectric layer A wire structure is formed thereon to cover the self-aligning contact window. 11858twf. Pt.d Page 17 1223876 VI. Application for Patent Scope 9 · The manufacturing method of the interconnect as described in Item 8 of the Patent Application Scope, wherein the ratio of the removal rate of the dielectric layer to the protective layer is greater than 3 0. 10. The method for manufacturing an interconnect as described in item 8 of the scope of the patent application, wherein the ratio of the removal rate of the dielectric layer to the top cap layer is between 10 and 20. 1 1. The method for manufacturing an interconnect as described in item 8 of the scope of patent application, wherein the material of the protective layer comprises a metal material. 1 2. The method for manufacturing an interconnect as described in item 11 of the scope of the patent application, wherein the metal material is selected from one of Yan, iron nitride, and titanium nitride-〇1 3. The method of manufacturing the interconnects according to item 8, wherein after the step of forming the spacers on the sidewalls of the gate structures and before the step of forming the dielectric layer over the substrate, the method further includes removing a portion of the A protective layer to retain the protective layer at a predetermined self-aligned contact window opening. 14. The method for manufacturing an interconnect as described in item 8 of the scope of patent application, wherein in the step of patterning the protective layer, the cap layer, and the gate conductive layer, the method further includes patterning the gate at the same time. An electrical layer is exposed to expose the surface of the substrate. The method for manufacturing an interconnect as described in item 8 of the scope of patent application, wherein the method for forming the wire structure includes performing a damascene process. 16 · The method for manufacturing an interconnect as described in item 8 of the scope of patent application, wherein the method for forming the wire structure includes: forming a wire material layer on the dielectric layer to cover the self-alignment 1 1858t.wf.ptd Page 18 1223876 VI. Patent Application Contact Window; and pattern the wire material layer to define the wire structure. 1 7. A kind of interconnect structure including: a plurality of gate structures arranged on a substrate, wherein each of the gate structures has a gate dielectric layer, a gate conductive layer and a cap layer; A protective layer disposed on top of the gate structures; a gap wall disposed on side walls of the gate structures; a dielectric layer covering the protective layer, the substrate and the gate structures; A quasi-contact window is disposed in the dielectric layer between two adjacent gate structures, wherein the self-aligned contact window is adjacent to the protective layer; and a wire structure is disposed in the dielectric layer. And the wire structure is electrically connected to the self-aligned contact window. 18. The interconnect structure described in item 17 of the scope of patent application, wherein the material of the protective layer comprises a metal material. 19. The interconnect structure according to item 18 of the scope of patent application, wherein the metal material is selected from one of tungsten, tungsten nitride and titanium nitride. 11858t.wf.ptd Page 19