TWI223750B - Parallel data bus set, data system and method for device communications - Google Patents
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1223750 五、發明說明(1) 一、【發明所屬之技術領域】 以及此 本發明係為一種平行資料匯流排組及其系統 系統中元件聯繫的方法。 、 二、【先前技術】 資料匯流排(d a t a b u s)係連接微處理器 (micr〇processor)和隨機存取記憶體(ram/,用需 要處理或儲存=身料的一種傳輸線路。習知之資料匯^非而可 分為兩種:一種為平行匯流排(parallel “Ο,一種為串 列匯流排(serial bus)。平行匯流排的優點产认曰女々女 认膝办 y ^ ^ u 咬點在於具有很大 的頻見,但在尚頻的環境下易產生競賽狀況(rwe condition)。串列匯流排的優點在於適用於^ = e,且不需 由時脈控制,但需使用類比(anal〇g)設計。门八 值於隨的進步,㈣愈多的元件需要利用匯流排來 傳輸,且傳輸速率的要求也愈來愈高。習知之平行匯流排 的頻寬雖然大,但高頻時會因為資料傳輪的時間及路徑不 同,而產生競賽狀況,造成資料傳輸上的錯誤。而習知之 串列匯流排雖無競赛狀況的問題,但是因為其位元數較 少’所以必須採用高頻的方式來換取頻寬。 ^ 為了克服上述的缺點,目前市面上用來作為高頻寬用 途的匯流排均使用位元數較少的匯流排加上超高頻的類比 電路設計,如USB 2· 〇、HTT、SATA 、PCI Express 等。、但 類比電路要整合進主機板是十分困難的,成本也較高,而* 且並非所有的產品都需要如此複雜的設計,因此一種數位1223750 V. Description of the invention (1) 1. [Technical field to which the invention belongs] And this invention is a parallel data bus group and a method for associating components in the system. Second, [prior art] A data bus is a transmission line that connects a microprocessor (microprocessor) and a random access memory (ram /), which needs to be processed or stored = body. Known data sink ^ Instead, it can be divided into two types: one is a parallel bus (parallel "0, one is a serial bus. The advantages of parallel buses are recognized by the son-in-law and daughter-in-law y ^ ^ u It has a lot of frequency, but it is easy to produce a rwe condition in a frequency environment. The advantage of a serial bus is that it is suitable for ^ = e, and does not need to be controlled by the clock, but an analogy (anal 〇g) design. With the progress of the gate value, more and more components need to use the bus to transmit, and the transmission rate requirements are getting higher and higher. It is known that although the bandwidth of the parallel bus is large, the high frequency When the time and path of the data transfer wheel are different, the race condition will occur, which will cause errors in data transmission. Although the conventional serial bus has no problem in the race condition, it has to have fewer bits, so it must be used. Use high frequency In order to overcome the shortcomings mentioned above, the buses currently used on the market for high-frequency bandwidth use buses with a small number of bits and an analog circuit design of ultra-high frequency, such as USB 2 · 〇 , HTT, SATA, PCI Express, etc., but it is very difficult and costly to integrate analog circuits into the motherboard, and * not all products require such a complex design, so a digital
第5頁 1223750 五、發明說明(2) 電路架構,卻可用於高頻寬但是低成本以及容易設計之平 行匯流排是迫切需要的。 三、【發明内容】 本發明提供一種平行資料匯流排組、一種資料系統及 一種元件間聯繫的方法。此平行資料匯流排組包含一第一 匯流排及一第二匯流排,連接於一第一元件及一第二元件 間,用以傳送資料暨控制信號。 其中,若第一元件欲主動與第二元件做資料傳輸時 (不論是將資料輸出至第二元件或是由第二元件輸入資 料),第一元件先將一第一信號組傳送至第二元件,且第 二元件係因應由第一元件傳送來之第一信號組,回應一第 二信號組至第一元件。當第一信號組從第一元件傳送至第 二元件時,利用第一匯流排傳送。而第二元件在接收到第 一信號組後,便由第二匯流排回應第二信號組給第一元 件。 第一信號組至少包含一控制信號組,用以請求匯流排 及告知第二元件應執行之動作。若資料需從第一元件傳送 至第二元件,則第一信號組亦包含一連串欲傳送之字元及 長度之資料信號組。第一信號組經由本發明之第一匯流排 傳送時,所有的接腳同時先傳送控制信號組,若有必要, 再傳送資料信號組。 本發明所揭露之資料系統至少包含第一元件、第二元Page 5 1223750 V. Description of the invention (2) The circuit architecture, but it can be used for high-bandwidth but low-cost and easy-to-design parallel buses is urgently needed. 3. Summary of the Invention The present invention provides a parallel data bus group, a data system, and a method for contacting components. The parallel data bus group includes a first bus and a second bus connected between a first component and a second component for transmitting data and control signals. Among them, if the first component wants to actively perform data transmission with the second component (whether it is to output data to the second component or input data from the second component), the first component first transmits a first signal group to the second Element, and the second element responds to a second signal set to the first element in response to the first signal set transmitted by the first element. When the first signal group is transmitted from the first element to the second element, it is transmitted using the first bus. After the second component receives the first signal group, the second bus responds the second signal group to the first component. The first signal group includes at least a control signal group for requesting the bus and notifying the second component of the action to be performed. If data needs to be transmitted from the first component to the second component, the first signal group also includes a series of data signal groups of characters and lengths to be transmitted. When the first signal group is transmitted via the first bus of the present invention, all the pins simultaneously transmit the control signal group, and if necessary, the data signal group. The data system disclosed in the present invention includes at least a first element and a second element.
第6頁 1223750 五、發明說明(3) 件、第一匯流排及第二匯流排。第一元件與第二元件分別 具有一輸入端及一輸出端。第一匯流排係為一單向平行資 料匯流排,分別連接於第一元件之輸出端與第二元件之輸 入端。第二匯流排亦為一單向平行資料匯流排,分別連接 於第二元件之輸出端與第一元件之輸入端。Page 6 1223750 V. Description of the invention (3), the first bus bar and the second bus bar. The first element and the second element have an input terminal and an output terminal, respectively. The first bus is a unidirectional parallel data bus, which is respectively connected to the output end of the first element and the input end of the second element. The second bus is also a unidirectional parallel data bus, which is connected to the output of the second component and the input of the first component, respectively.
此資料系統中元件聯繫的方法包含下列步驟:當有一 資料需從第一元件傳送至第二元件時,第一元件經第一匯 流排,傳送控制信號組至第二元件,用以告知第二元件應 執行之動作。若第二元件需回應其控制信號組,在控制信 號組傳送之時,利用第二匯流排傳送一第一回應信號組至 第一元件。第一元件經第一匯流排傳送資料時,若第二元 件需作回應,在資料傳送之時,利用第二匯流排傳送一第 二回應信號組至第一元件。同樣地,當有一資料需從第二 元件傳送至第一元件時,第二元件經第二匯流排,傳送一 控制信號組至第一元件,用以告知第一元件應執行之動 作。若第一元件需回應控制信號組,在控制信號組傳送之 時,利用第一匯流排傳送一第三回應信號組至第二元件。 第二元件經第二匯流排傳送資料時,若第一元件需作回 應,在資料傳送之時,利用第一匯流排傳送一第四回應信 號組至第二元件。 四、【實施方式】 本發明提供一種平行資料匯流排組,連接於一第一元 件及一第二元件間,用以傳送資料。其中,第一元件欲將The method for contacting components in this data system includes the following steps: When a piece of data needs to be transmitted from the first component to the second component, the first component transmits the control signal group to the second component via the first bus to inform the second component. The action the component should perform. If the second component needs to respond to its control signal group, when the control signal group is transmitted, a second response signal group is transmitted to the first component by using the second bus. When the first component transmits data through the first bus, if the second component needs to respond, when the data is transmitted, a second response signal group is transmitted to the first component by using the second bus. Similarly, when a piece of data needs to be transmitted from the second component to the first component, the second component transmits a control signal group to the first component via the second bus to inform the first component of the action to be performed. If the first element needs to respond to the control signal group, when the control signal group is transmitted, a third response signal group is transmitted to the second element by using the first bus. When the second component transmits data via the second bus, if the first component needs to respond, when the data is transmitted, a fourth response signal group is transmitted to the second component by using the first bus. 4. Embodiment The present invention provides a parallel data bus group connected between a first element and a second element for transmitting data. Among them, the first element
第7頁 五、發明說明(4) 一第一信號組傳送 —— 元件傳送來之第一 t f 一兀件,且第二元件係因應由第一 件。如第一同& _ L就組,回應一第二信號組至第一元 (clock),而兩 弟—疋件與第二元件具有相同的時脈 一匯流排1與一第丄料之平行資料匯流排組包含一第 送至第二元件時一匯流排2。當第一信號組從第一元件傳 在接收到第一 =σ’ f利用第—匯流排1傳送。而第二元件 組給第一元件f ^組後’便由第二匯流排2回應第二信號 立’不互相旦彡鄉/、 第 匯流排1與第二匯流排2彼此獨 V/音 〇 也雜日丄八 第二元件口 |拉^ 犹疋祝’當第一信號組開始傳送後, 傳送完畢,第二元,的訊息,不論第一信號組是否已 組至第一元件。便y根據其訊息,馬上回應第二信號 向之平行匯冷、’ ’第—匯流排1與第二匯流排2皆為單 件時,必須您;垃 7 k就需從第一元件傳送至第二元 /只段由第一匯泠知t 送至第一元杜 L徘1 ’任何信號需從第二元件傳 不 件時,必須經A楚 便,在此說明蚩中,一 Γ由弟二匯流排2。為求說明時方 件,而接收i I律將要求傳送端元件視為第一元 u應鈿兀件視為第_ +杜 ^ ^ π. 乐一 7G 件。 Ισ說組至少包冬 k & 告知第二亓姓e +, 控制信號’用以請求匯流排及 ^ π件應執行何種無A 4 + 卜 亦包含一 i袭由 ^ 動作,右有必要,則第一信號組 習知之平行* 、^予疋及其長度之資料信號。不同於 1傳送時,丁如進流排’、第—信號組經由本發明之第一匯流排 信號。如第—有的接—腳同時先傳送控制信號’再傳送資料 分為四區:Γ圖所不,為了方便說明,在此將第一信號組 •弟一區11 、第二區13、第三區15及第四區17。Page 7 V. Description of the invention (4) A first signal group transmission —— The first t f one piece transmitted by the component, and the second component is caused by the first piece. For example, the first group is the same as & _L, and responds to a second signal group to the first clock (clock), and the two brothers—the component and the second component have the same clock—the bus 1 and the first component. The parallel data bus group includes a bus 2 when it is sent to the second component. When the first signal group is transmitted from the first element, the first = σ 'f is transmitted using the first bus 1. After the second element group gives the first element f ^, 'the second bus 2 responds to the second signal,' and the second bus 1 and the second bus 2 are independent of each other. It is also mixed with the second component port | pull ^ I still wish 'when the first signal group begins to transmit, the transmission is complete, the second element, whether or not the first signal group has been grouped to the first component. Then, according to its message, immediately respond to the parallel signal to the second signal, '' the first bus 2 and the second bus 2 are single pieces, you must; you need to send 7k from the first component to The second element / segment is sent from the first source to the first element. If any signal needs to be transmitted from the second element, it must pass through A. In this description, a Brother II Bus 2. For the sake of explanation, the receiving law will require the transmitting end element to be regarded as the first element, and the u should be regarded as the first element. + ^ ^ ^. Leyi 7G. Iσ said that the group included at least k & informed the second surname e +, the control signal 'is used to request the bus and what ^ π pieces should be performed without A 4 + bu also includes an i-based action ^, right is necessary , Then the first signal group is familiar with the parallel *, ^ yu 疋 and its length data signals. Different from 1 when transmitting, Ding Ru's busbar 'and the first signal group pass through the first busbar signal of the present invention. For example, some of the pins first transmit control signals at the same time, and then the data is divided into four areas: Γ is not shown. For the convenience of explanation, the first signal group • Di 1 area 11, 2nd area 13, and 1st area Third district 15 and fourth district 17.
第8頁 1223750 五、發明說明(5) 字或設定值為多少位元 當第一元件向第二 第一匯流排1先傳送第一 階段(request phase), 第二信號^依第一信號組之請求,有不同的組合方式,在 此先假没分為兩區:第五區21及第六區23。其中,第一區 11、第二區1 3及第三區1 5用以傳送控制信號,第四區1 7用 以在需要時傳送資料信號或相對於第六區23的回應訊息。 第一圖中數字” 〇 ”表示第一匯流排1或第二匯流排2閒置中 (1 d 1 e ) ’無任何信號被傳送;而文字” χ,,表示第一匯流排! 或第,二匯流排2正在傳送第一信號組或第二信號組。文 子X原應為二進位或十六進位之位元,且因系統不同而 有不同之位元數,為了說明及繪圖的方便,在此說明書之 圖式中’除非特別指出,否則不論圖式中所有區間内的文 ,皆以單一文字或數字來表示。 匕件提出一指令時,第一元件經由 區11的訊息,此第一區11為請求 用以請求第二元件接受第一元件 所要求之指令。本發明實施例之請求階段設定值如第一表 所示:Page 8 1223750 V. Description of the invention (5) How many bits are the word or set value? When the first component transmits the first phase (request phase) to the second first bus 1, the second signal ^ is based on the first signal group There are different ways of combining requests, and the leave is not divided into two areas: the fifth area 21 and the sixth area 23. Among them, the first area 11, the second area 13 and the third area 15 are used for transmitting control signals, and the fourth area 17 is used for transmitting data signals or response messages relative to the sixth area 23 when needed. The number “0” in the first figure indicates that the first bus 1 or the second bus 2 is idle (1 d 1 e) 'No signal is transmitted; and the text “χ” indicates the first bus! Or, The second bus 2 is transmitting the first signal group or the second signal group. The text X should be a binary or hexadecimal bit, and has a different number of bits due to different systems. For the convenience of illustration and drawing, In the drawings of this specification, unless otherwise specified, regardless of the text in all sections in the drawing, they are represented by a single word or number. When a command is issued by a dagger, the first element passes the message in zone 11, and this section The first area 11 is a request for requesting the second component to accept the instruction requested by the first component. The set value of the request phase in the embodiment of the present invention is shown in the first table:
閒置(i d 1 e ) 設定值 〇 匯流排請求(bus reauest) 1 匯流排授予(b u s grant) 2 中斷(interrupt) 3 乒乓請求(ping D〇ng REQ) 4 兵兵回應(ping Dong ACK) 5 第9頁 1223750Idle (id 1 e) set value 0 bus request (bus reauest) 1 bus grant (bus grant) 2 interrupt 3 ping pong request (ping D〇ng REQ) 4 ping Dong ACK 5 9 pages 1223750
五、發明說明(6) ' 兵兵重言式(ping pong retry ) 6 信息(m e s s a g e ) 7 匯流排重設(b u s r e s e t) E 熱插拔(hot plug) F 第一表V. Description of the invention (6) 'Bing Ping retry (ping pong retry) 6 Information (m e s s a g e) 7 Bus reset (b u s r e s e t) E Hot plug F
傳送完第一區11的訊息後,第一元件便傳送第二區1 3 的訊息。此第二區1 3為指令階段(command phase),用以 告知第二元件所需執行之動作。此一實施例之指令階段設 定值如第二表所示:After the message in the first zone 11 is transmitted, the first component transmits the message in the second zone 1 3. This second area 13 is a command phase, which is used to inform the second component of the action to be performed. The setting values of the command phase of this embodiment are shown in the second table:
指令階段 設定值 閒置(idle) 0 輸出入讀出(I/O read) 1 輸出入寫入(I/O write) 2 1己十意體讀出(m e m o r v read) 3 記憶體寫入(memory write) 4 記憶體讀出線(memory read line) 5 記憶體寫入線(m e m o r y w r i t e line) 6 設定讀出(configuration read) 7 設定寫入(configuration write) 8 第- 二表The set value in the instruction phase is idle 0 I / O read 1 I / O write 2 1 memory read (memorv read) 3 memory write ) 4 memory read line 5 memory write line 6 configuration read 7 configuration write 8 configuration write 8
第10頁 五、發明說明(7) 第三區1 5的訊息為—位 處取得資料或將資料存向f ’用以告知第二元件需從何 (data phase),用以傳於。第四區17則為資料階段 傳輸相對於第六區23的:應=資料信號及其長度或用以 4立當第一元件傳送第二區13:訊息的同時’第二元件已 妾收到第-區11的訊息,此時便可傳送第五區21的訊息, 以回應第一區11的請求階段。本發明之實施例中第五^21 的回應訊息設定值與第一表相同。 當第一元件傳送第四區1 7之訊息的同時,第二元件已 接收到第三區1 5的訊息,此時第二元件便可於第六區2 3傳 送相關之資料信號及其長度(如第一元件請求〜讀出動作 時),或是傳送用來回應第三區1 5或第J19區1 7之回應訊息 (如第一元件請求一寫入動作時)。本貫施例第四區1 7或是 第六區2 3的回應訊息設定值如第三表所不: 回應訊息 ___ 週置(idle)___ A 效(val id)__ ir jJiCstop) ______4—Page 10 V. Description of the invention (7) The message in the third area 15 is-to obtain data at the location or store the data at f 'to inform the second component of the data phase from which to pass. The fourth area 17 is the data phase transmission relative to the sixth area 23: should = data signal and its length or used to transmit the second area 13 while the first component 13: the message while the second component has been received The message of the first zone 11 can now send the message of the fifth zone 21 in response to the request stage of the first zone 11. In the embodiment of the present invention, the setting value of the fifth response message is the same as that of the first table. While the first component transmits the message in the fourth area 17, the second component has received the message in the third area 15 and the second component can transmit the relevant data signal and its length in the sixth area 23 (Such as when the first component requests to read operation), or send a response message in response to the third area 15 or the J19 area 17 (such as when the first component requests a write operation). In this example, the setting value of the response message in the fourth zone 17 or the sixth zone 2 3 is not as shown in the third table: Response message ___ weekly (idle) ___ A effect (val id) __ ir jJiCstop) ______ 4—
It 誤(error)_________5__一 第 表It error_________5__ 一 Table
1223750 五、發明說明(8) 若第四區1 7或是第六區2 3為資料信號以及其長度時, 則所有的接腳同時先傳送資料長度,再傳送資料信號。 值得注意的是,根據第一區11的訊息與第五區2 1的訊 息之不同,結果將會影響到第三區1 5、第四區1 7與第六區 23是否存在,甚至會產生其他的區域。也就是說,第二圖 中之所有的區域並非都是必須存在的,需視其狀況而定。 根據以上的設定值,本發明實施例定義了一些基本的 傳輸協定(protocol),如下:1223750 V. Description of the invention (8) If the fourth zone 17 or the sixth zone 23 is a data signal and its length, all pins transmit the data length first and then the data signal. It is worth noting that according to the difference between the message in the first zone 11 and the message in the fifth zone 21, the result will affect the existence of the third zone 15, the fourth zone 17 and the sixth zone 23, and may even produce Other areas. That is to say, not all the areas in the second picture must exist, and it depends on the situation. According to the above setting values, the embodiments of the present invention define some basic transmission protocols, as follows:
一、 閒置 當第一元件並無任何資料需要傳送時,第一匯流排1 呈現閒置狀態,如第三圖所示,第一信號的每一位元皆 為π 0π (參閱第一表)。由於第一元件閒置,第二元件亦不 需回應任何訊息,故第二信號的每一個位元亦為π 0π。 二、 匯流排請求/授予I. Idle When the first component has no data to transmit, the first bus 1 is idle. As shown in the third figure, each bit of the first signal is π 0π (see the first table). Since the first component is idle and the second component does not need to respond to any message, each bit of the second signal is also π 0π. Bus requests / grants
當需要傳送資料至第二元件或從第二元件接收資料 時,如第四圖所示,第一元件在第一區11先傳送一匯流排 請求設定值π Γ’(參閱第一表),第二元件係因應其匯流排 請求,於第五區2 1回應一匯流排授予設定值π 2Π (參閱第一 表),告知第一元件此平行資料匯流排組之使用權已授 予,可繼續傳送信號至第二元件。 若第二元件忙碡中而無法處理第一元件的請求或是第 二元件不存在(被移除)時,如第五圖所示,則於第五區2 1When data needs to be transmitted to or received from the second component, as shown in the fourth figure, the first component first transmits a bus request setting value π Γ 'in the first area 11 (see the first table), The second component responds to a request from the bus and responds to a bus grant setting value π 2Π in the fifth area 21 (see the first table), informing the first component that the right to use the parallel data bus group has been granted and can continue Send a signal to the second element. If the second component is busy and cannot process the request of the first component or the second component does not exist (removed), as shown in the fifth figure, in the fifth area 2 1
第12頁 1223750 五、發明說明(9) 回應一閒置設定值"0"(也就是不予回應),第一元件在接 收到π οπ的回應信號後,便停止傳送訊息。其中,第四圖 及第五圖中其他訊息暫以文字π χπ表示,其說明將於後補 述。 三、 重試(retry) 在已回應一匯流排授予設定值” 2”的情況下,由於某 種因素,例如忙碌中而無法處理第一元件的請求,第二元 件可要求第一元件重新傳送。如第六圖所示,第二元件於 第六區23回應” 0Π (代表第二元件無法處理任何資料),第 一元件便不再傳送第四區1 7裡的信號,在適當的一段時間 後,第一元件會嘗試重送訊息。其中,第四區1 7裡的數 字ff 0"表示第一元件在得不到第二元件的回應後,便處於 閒置狀態。 四、 寫入 當第一元件欲執行一輸出入寫入、記憶體寫入、記憶 體寫入線、或是設定寫入動作時,第一元件於第二區13會 傳送一輸出入寫入、記憶體寫入、記憶體寫入線或是設定 寫入設定值ff π 4”、 π 6Π或是π 8”(參閱第二表)。由於 其寫入動作均相仿,故第七圖及以下說明部分僅以記憶體 寫入為例,其餘寫入動作不在此贅述,熟此記憶者應可依 此推之。 接著,第一元件在第三區1 5中傳送資料信號欲寫入之Page 12 1223750 V. Description of the invention (9) In response to an idle set value " 0 " (that is, no response), the first component stops sending a message after receiving a response signal of π οπ. Among them, the other messages in the fourth and fifth pictures are temporarily represented by the text π χπ, and the description thereof will be supplemented later. Third, retry (retry) In response to a bus grant set value "2", due to some factors, such as busy and unable to process the request of the first component, the second component can request the first component to retransmit . As shown in the sixth figure, the second component responds in the sixth area 23 "0Π (representing that the second component cannot process any data), and the first component no longer transmits the signal in the fourth area 17, in an appropriate period of time After that, the first component will try to resend the message. Among them, the number ff 0 " in the 17th area of the fourth area indicates that the first component is in an idle state after it cannot get a response from the second component. When a component wants to perform an input / output write, a memory write, a memory write line, or a set write operation, the first component sends an input / output write, a memory write, The memory write line is either set to write the set value ff π 4 ”, π 6Π or π 8” (see the second table). Because the write operations are similar, the seventh figure and the following description are only based on the memory The body writing is taken as an example, the rest of the writing actions are not described here, and those who are familiar with this memory should be able to follow it. Then, the first component transmits the data signal to be written in the third area 15
1223750 五、發明說明(ίο) 位址,第二元件在第六區23中回應第二元件目前可接受声 理的容量(即圖中第六區2 3内之文字” γ”)。若第一元件欲处 寫^的貢料信號的大小(即圖中第四區丨7内之文字n L,,)小 於第一元件目别可接受處理的容量,則第一元件便於第四 區1 7中傳送全部的資料信號。若第一元件欲寫入的資料信 唬的大小大於第二元件目前可接受處理的容量,則第四區 1 7僅=傳送第二元件目前可接受處理的資料量。 當第一元件在傳送第四區丨7中之資料信號時,若第二 70 =能處理下一個時脈之輸入,則傳送有效設定值” 3”(參 閱第^表),第一元件便於下一個時脈繼續傳送資料信 ί。若第二,元件不能處理下—時脈的資料,則傳送閒置設 =值0 ,第一兀件在下一個時脈便不會傳送資料,直到 第二元件再度傳送有效設定值, 件才繼續傳送 資料。 矛 五、讀出 用本發明之平行資料匯流排組執行讀出資料的動 第執行寫人的動作並無太大差別。第一元件可於 二— >,輸出入讀出、記憶體讀出、記憶體讀出線 j疋s又疋,買出設定值,,r、" y或是"7”(參閱第二 S*動作均相仿,故第八圖及以下説明部分 僅以5己f思體讀出為例,盆 & ^ 憶者應可依此推之。…于、項出動作不在此^ 如第八圖所示’第一元件於第三區1 5傳送欲讀出資料 1223750 五、發明說明(11) 之位址’第二元件在第六區23中回應其可提供的資料传 之大小(即圖中第六區23内之文字"L")。若第一元件γ 求的資料容量(即圖中第四區1 7内之文字” γ”)小於第一, 件可提供之大小’則第一元件可以讀取全部之資料$量。^ 第一元件所需求的資料之容量大於第二元件可提供=二右 小,則第二元件只會在第六區23中傳送可提 資 號。 同樣地’當苐一元件在傳送第六 時,若第一元件能處理下一個時入3中2料信號 定值”3"(參閱第三表h若第一二輪二’則傳”效設 輸入,則傳送閒置設定值"0",第二亓::理下一日可脈的 定值"0"後,下一個時脈便不會傳逆次 接收到閒置設 再度傳送有效設定值"3” ,才繼續僂 且劁弟70仵 想提早結束整個動作或是傳送動作、貝」斗、。當第一元件 止設定值,,4,,(參閱第三表),以通4〜、生元成時,便傳送停 令。 、知弟二元件結束這個指 六、錯誤 在傳送資料信號時若發生錯誤 值”5”(參閱第三表),以要求重3新傳、可送出一錯誤設定 作。如第九圖所示,當第一元件 运―或止目丽的動 設在接收第六區23之資料信號發 ^讀出的動作時,假 傳送一錯誤設定值π 5”,以告知繁」'诀,可於第三區17内 元件接收到錯誤訊息後,便處於「70件傳送錯誤。第二 处於閒置狀態,等候進一步指1223750 V. Description of the invention (ίο) Address, the second component responds to the current acoustic capacity of the second component in the sixth area 23 (ie, the text "γ" in the sixth area 23 of the figure). If the size of the tributary signal to be written by the first component (ie, the text n L, in the fourth area of the figure 7) is smaller than the capacity of the first component that can be processed, the first component is convenient for the fourth component. Zone 17 transmits all data signals. If the size of the data message to be written by the first component is larger than the capacity that the second component can currently process, then the fourth area 17 = only the amount of data that the second component can currently process. When the first component is transmitting the data signal in the fourth area, if the second 70 = can process the input of the next clock, then the effective set value is transmitted "3" (see table ^), the first component is convenient The next clock continues to send information letters. If the second component cannot process the next-clock data, the idle setting is set to a value of 0, and the first component will not transmit data at the next clock. The component will not continue transmitting until the second component transmits a valid set value again. data. Spear V. Readout The parallel data bus group of the present invention is used to perform the readout of data. The first component can be in two->, input-output readout, memory readout, memory readout line j 疋 s again, buy a set value, r, " y or " 7 "(see The second S * actions are similar, so the eighth figure and the following description only take 5 己 f as an example to read out. Basing & As shown in the eighth figure, "the first component transmits the data to be read in the third area 15 1223750 5. The address of the invention description (11)" The second component responds to the information it can provide in the sixth area 23 Size (that is, the text "L" in the sixth area 23 in the figure). If the data capacity required by the first component γ (that is, the text "γ" in the fourth area 17 in the figure) is smaller than the first, the item can be provided The size of the first component can read the entire amount of data $. ^ The capacity of the data required by the first component is greater than the second component can provide = two right small, then the second component will only be transmitted in the sixth area 23 The number can be raised. Similarly, when the first component is transmitting the sixth, if the first component can process the next one, enter the 3 signal and the 2 signal setting value "3" (see After reading the third table h, if the first two rounds of the "then pass" function input, then the idle setting value " 0 " is transmitted. One clock will not transmit the idle setting and then re-transmit the effective setting value "3" before continuing. And the younger brother 70 wants to end the entire action or transmit the action early. When the first element Stop the set value, 4 ,, (refer to the third table) to pass 4 ~, when the yuan is completed, the stop order will be transmitted. 、 The second element ends the reference. 6. Error If an error value occurs when transmitting the data signal "5" (refer to the third table), request to repeat 3 new transmissions, can send out a wrong setting. As shown in the ninth figure, when the first component is operated-or the eye-catching action is set in the receiving area 23 When the data signal is read and read, a false set value π 5 "is falsely transmitted to inform the" "trick. After receiving the error message, the component in the third area 17 will be in" 70 transmission errors. " The second is idle, waiting for further instructions
第15胃 !22375〇 五、發明說明(12) 7J> ο 七、中斷 在第一元件完成某件事情之後,或是發生某些特殊狀 況,需要通知系統來處理時,如第十圖所示,第一元件可 在第一區1 1傳送一中斷設定值” 3”(參閱第一表),並於第 二區13傳送一中斷代碼(interrupt number) ,用以要 求第二元件接收此中斷訊息。其中,中斷代碼,’ N”用來表 示此一中斷指令係由哪一個元件所發出。 八、熱插拔 如第十一 A圖所示,假設第一元件為一可移除之元 件,而系統開機時兩元件原本未相連接,即第一圖中之第 一匯流排1被分為兩個部份:第一元件端之第一匯流排1 a 以及第二兀件端之第一匯流排丨b。本發明實施例之初始設 疋為第一元件端之第一匯流排丨a透過一個阻抗值較小之電 阻連接至一高電壓準位,第二元件端之第一匯流排丨b透過 了個阻抗值較大之電阻連接至一低電壓準位。第一圖中之 第一匯二排2亦分為兩個部份:第一元件端之第二匯流排 2a以及第一兀件端之第二匯流排%。本發明實施例之初始 設定為第一元件端之第二匯流排2a透過一個阻抗值較大之 =j連接,一低電壓準位,第二元件端之第二匯流排2b透 匕一個阻抗值較小之電阻連接至一高電壓準位。 在主機持續運轉的狀態下,將第一元件與第二元件相The 15th stomach! 22375 05. Description of the invention (12) 7J > ο 7. Interruption After the first element completes something or some special situation occurs and the system needs to be notified to handle it, as shown in Figure 10 The first component can transmit an interrupt setting value "3" in the first area 1 1 (see the first table), and transmit an interrupt code (interrupt number) in the second area 13 to request the second component to receive the interrupt message. Among them, the interrupt code, 'N' is used to indicate which component this interrupt instruction is issued from. 8. Hot-swap As shown in Figure 11A, suppose the first component is a removable component, and When the system was turned on, the two components were not connected, that is, the first bus 1 in the first figure is divided into two parts: the first bus 1 a at the first component end and the first bus 1 at the second component end. Row 丨 b. The initial setting of the embodiment of the present invention is the first bus bar at the first element side 丨 a is connected to a high voltage level through a resistor with a small resistance value, and the first bus bar at the second element side 丨b is connected to a low voltage level through a resistor with a larger impedance value. The first bus line 2 and line 2 in the first figure are also divided into two parts: the second bus bar 2a at the first component side and the first bus line 2a. The second busbar% of the element side. The initial setting of the embodiment of the present invention is that the second busbar 2a of the first element side is connected through a larger impedance value = j, a low voltage level, and the second element side The second bus bar 2b is connected to a high voltage level through a resistor having a small impedance value. The state machine operation is continued, the first element and the second element with
第16頁 1223750Page 16 1223750
五、發明說明(13)V. Description of Invention (13)
連接’即第一元件端之第一匯流排1 a與第二元件端之第一 匯流排1 b連接成第一匯流排i,如第十一B圖所示,此時第 一匯流排1產生一電流由高電壓準位流向低電壓準位(如虛 線箭頭所示)’因為阻抗分壓的結果(丨a的電阻值較小),亚 在第一匯流排上將會產生一個高電壓準位。如第十二圖所 示’此一結果將於第八區2 5產生一對應之熱插拔設定 值"F”(參閱第一表),之後第二元件便切斷第一匯流排1與 上述低電壓準位的連線,且於第七區丨9產生一匯流排重設 值’’ Επ (麥閱第一表),之後第一元件便切斷第一匯流排工 與上述高電壓準位的連線,使得第一匯流排1完成初始 化,以形成如第一圖所示之狀態,並可開始執行資料的傳 送。第二匯流排2之熱插拔動作與第一匯流排丨無異,故不 贅述。 九、信息Connected, that is, the first bus bar 1 a at the first component end and the first bus bar 1 b at the second component end are connected to form a first bus bar i, as shown in FIG. 11B. At this time, the first bus bar 1 Generate a current flowing from the high voltage level to the low voltage level (as shown by the dashed arrow) 'Because of the result of the impedance division (the resistance value of a is small), a high voltage will be generated on the first bus Level. As shown in the twelfth figure, 'This result will generate a corresponding hot-swap setting value "F" in the eighth zone 2 5 (see the first table), and then the second component will cut off the first bus 1 The connection to the above-mentioned low voltage level, and a bus reset value '' επ (mai read the first table) is generated in the seventh area, and then the first component cuts off the first busbar and the above-mentioned high voltage. The connection of the voltage level enables the first bus 1 to be initialized to form the state shown in the first figure, and the data transmission can be performed. The hot plugging action of the second bus 2 and the first bus丨 No difference, so I won't go into details.
當第一元件需傳送一信息(如嚴重錯誤、進入或是離 開睡眠狀態等)至系統中全部的元件或是某個特定元件 時,如第十三圖所示,第一元件在第一區n中傳送一信拿 設定值π 7Π (參閱第一表)至第二元件,並在第二區丨3傳送w 第一元件的位址,以表示信息發自第一元件,最後在第三 區1 5傳送其#息。此信息内含目的元件之位址或是代表全 部兀件的訊息,第二兀件可依其地址將此信息傳遞下去, 直到此信息到達目的元件為止。 §第一元件利用乜息來通知系統中全部元件進入睡眠When the first component needs to send a message (such as a serious error, entering or leaving a sleep state, etc.) to all the components in the system or a specific component, as shown in Figure 13, the first component is in the first area Send a letter in n to the set value π 7Π (see the first table) to the second component, and send the address of the first component in the second area 3 to indicate that the message was sent from the first component, and finally in the third Area 1 5 transmits its information. This message contains the address of the destination component or a message representing all the components. The second component can pass on this information based on its address until the information reaches the destination component. § The first component uses information to notify all components in the system to go to sleep
12237501223750
五、發明說明(14) 狀態時,所有 自動進入睡眠 出一個信息給 態,因此第二 自動醒來。當 回應,並依照 收到此信息的元 狀態。當第一元 第二元件,但是 元件在第四區21 第一元件再次發 此方式叫醒其他 件在將信息傳 件欲叫醒系統 弟—儿件此時 無須回應,但 出信息時,第 元件。 遞出去之後, 時,也是先發 正處於睡眠狀 弟二元件必須 —元件就必須 十、仲裁(arbi tration)V. Description of the invention (14) In the state, all of them automatically go to sleep and give a message to the state, so the second automatically wakes up. When responding, and in accordance with the meta status of this message. When the first element is the second element, but the element is in the fourth zone, the 21st element sends this method again to wake up the other pieces. When the message is transmitted, the system wants to wake up the system brother—the child piece does not need to respond at this time. element. After being handed out, it is also the first to be sleeping. The second element must be-the element must be X. Arbitration
由於第一元件與第二元件皆可以主動提出匯流排請求 的動作,假設第一元件與第二元件在同一個時脈提出匯流 排請求,則第一元件與第二元件必須有一仲裁行為來判定 要由哪一元件先取得匯流排授與的資格,因此必須先定義 各元件間資料傳送的優先權等級。 當相鄰兩元件同時發出匯流排請求時,具有較高優先 權等級的元件可取得匯流排的使用權,故相鄰雨元件間之 優先權等級必不相同。在此一實施例中,定義數字,’ Γ的 優先權大於數字"〇 ” ,如第十四圖所示,第一元件與第二 兀件之匯流排使用優先權為第二元件大於第一元件,故當Since both the first element and the second element can actively initiate a bus request action, assuming that the first element and the second element make a bus request at the same clock, the first element and the second element must have an arbitration action to determine Which component is to be qualified by the bus first, it is necessary to define the priority of data transmission between the components first. When two adjacent elements send a bus request at the same time, the element with a higher priority level can obtain the right to use the bus, so the priority level between adjacent rain elements must be different. In this embodiment, the number is defined, and the priority of 'Γ is greater than the number " 〇. As shown in FIG. 14, the priority of using the bus of the first element and the second element is that the second element is greater than the first. One element, so when
第一元件與第一元件同時要求匯流排的使用權時,第二元 件可優先取得。 十一、兵兵路徑 一如第十四圖所示,若第一元件欲從第三元件中存取一 貝料日守,則控制信號及資料信號需經由第二元件來傳送。When the first component and the first component require the right to use the bus at the same time, the second component can get priority. XI. Bingbing Path As shown in the fourteenth figure, if the first component wants to access a material watch from the third component, the control signal and data signal need to be transmitted through the second component.
第18頁 1223750 五、發明說明(15)Page 18 1223750 V. Description of the invention (15)
習知之做法為:若第一元件欲寫入資料到第三元件,則第 二元件可以將第一元件送來的控制信號及資料信號全部接 收之後,再傳送到第三元件,第一元件無須等待。但是若 第一元件欲從第三元件讀出一資料時,第二元件只能先接 收第一元件傳送來的控制信號,並且利用重試指令回應給 第一元件,再將控制信號送到第三元件。在第三元件未將 資料傳回給第二元件之前,第一元件就必須一直不斷的向 第二元件送出要求,而第二元件也必須不斷的利用重試指 令回應第一元件,直到第二元件收到第三元件回應的資 料。如此一來第一元件會浪費許多時間,尤其當第三元件 如果是離第一元件很遠的時候。為了避免此情況發生,可 利用乒乓路徑來作讀取的動作,以節省中間不斷的重試動 作。The conventional method is: if the first component wants to write data to the third component, the second component can receive all the control signals and data signals sent by the first component and then send it to the third component. The first component does not need to wait. However, if the first component wants to read a piece of data from the third component, the second component can only receive the control signal sent by the first component, and use the retry command to respond to the first component, and then send the control signal to the first component. Three elements. Before the third component sends data back to the second component, the first component must continuously send requests to the second component, and the second component must continue to respond to the first component with the retry command until the second component The component receives data from the third component response. This will waste a lot of time on the first component, especially if the third component is far from the first component. In order to avoid this situation, you can use the ping-pong path to do the reading action to save the continuous retrying action in the middle.
利用本發明之平行資料匯流排組執行乒乓路徑的傳輸 時,如第十四圖所示,第二元件與第三元件間由一第三匯 流排3和一第四匯流排4作連接。其中,第三匯流排3用以 將一第三信號由第二元件傳送至第三元件,第四匯流排4 用以將一第四信號由第三元件傳送至第二元件。以記憶體 讀出為例,假設第一元件需從第三元件讀出一資料,如第 十五A圖所示,第一元件於第一區1 1傳送一乒乓請求設定 值π 4Π (參閱第一表),於第二區13傳送一記憶體讀出設定 值π 3π (參閱第二表),於第三區1 5傳送欲讀取資料之位 址,並於第四區1 7傳送欲讀取資料之大小。 第二元件接收到由第一元件傳送來的控制信號及資料When using the parallel data bus group of the present invention to perform the ping-pong path transmission, as shown in FIG. 14, the second element and the third element are connected by a third bus 3 and a fourth bus 4. The third bus 3 is used to transmit a third signal from the second element to the third element, and the fourth bus 4 is used to transmit a fourth signal from the third element to the second element. Take memory readout as an example. Assume that the first component needs to read a piece of data from the third component. As shown in Figure 15A, the first component sends a ping-pong request setting value π 4Π in the first area 11 (see The first table), a memory read setting value π 3π is transmitted in the second area 13 (refer to the second table), the address of the data to be read is transmitted in the third area 15 and the seventh is transmitted in the fourth area 17 The size of the data to be read. The second component receives the control signal and data transmitted by the first component
第19頁 1223750 五、發明說明(18)Page 19 1223750 V. Description of the invention (18)
件。第一元件經第一匯流排傳送資料時,若第二元件需作 回應,在資料傳送之時,利用第二匯流排傳送一第二回應 信號至第一元件。同樣地,當有一資料需從第二元件傳送 至第一元件時,第二元件經第二匯流排,傳送一控制信號 至第一元件,用以告知第一元件應執行之動作,若第一元 件需回應控制信號,在控制信號傳送之時,利用第一匯流 排傳送一第三回應信號至第二元件。第二元件經第二匯流 排傳送資料時,若第一元件需作回應,在資料傳送之時, 利用第一匯流排傳送一第四回應信號至第二元件。Pieces. When the first component transmits data through the first bus, if the second component needs to respond, when the data is transmitted, a second response signal is transmitted to the first component by using the second bus. Similarly, when a piece of data needs to be transmitted from the second component to the first component, the second component transmits a control signal to the first component via the second bus to inform the first component of the action to be performed. The component needs to respond to the control signal. When the control signal is transmitted, a third response signal is transmitted to the second component by using the first bus. When the second component transmits data via the second bus, if the first component needs to respond, when the data is transmitted, a fourth response signal is transmitted to the second component by using the first bus.
所有圖式中之第一區11、第二區13、第三區15、第四 區17、第五區21、第六區23、第七區19及第八區25皆為虛 擬,係為了說明方便而定義之區間,實際上資料傳輸時並 無這些區間之設定。 綜合以上所述,本發明提供了 一種平行資料匯流排 組,以解決習知平行匯流排不適用於高頻的缺點。同時基 於此種平行資料匯流排組,本發明亦提供一種資料系統及 系統中元件聯繫的方法,以加速並簡化元件間資料的傳 輸0In the drawings, the first area 11, the second area 13, the third area 15, the fourth area 17, the fifth area 21, the sixth area 23, the seventh area 19, and the eighth area 25 are all virtual. It is convenient to define and define intervals. In fact, there is no setting of these intervals during data transmission. In summary, the present invention provides a parallel data bus group to solve the disadvantage that the conventional parallel bus is not suitable for high frequencies. At the same time, based on such a parallel data bus group, the present invention also provides a data system and a method for connecting components in the system to speed up and simplify data transmission between components.
第22頁 1223750 圖式簡單說明 五、【圖示簡單說明】 第一圖為本發明之平行資料匯流排組及資料系統之示 意圖, 第二圖為信號傳送順序示意圖; 第三圖為閒置信號之示意圖; 第四圖為匯流排授予信號之示意圖; 第五圖為匯流排不授予信號之示意圖; 第六圖為重試信號之示意圖; 第七圖為寫入信號之示意圖;Page 23 1223750 Brief description of the diagram V. [Simplified illustration of the diagram] The first diagram is a schematic diagram of the parallel data bus group and data system of the present invention, the second diagram is a schematic diagram of the signal transmission sequence; the third diagram is the idle signal Schematic diagram; the fourth diagram is the diagram of the bus grant signal; the fifth diagram is the diagram of the bus no signal; the sixth diagram is the diagram of the retry signal; the seventh diagram is the diagram of the write signal;
第八圖為讀出信號之示意圖; 第九圖為錯誤信號之示意圖; 第十圖為中斷信號之示意圖; 第十一 A圖為本發明之平行資料匯流排組尚未連接之 不意圖, 第十一 B圖為本發明之平行資料匯流排組初始化之示 意圖, 第十二圖為熱插拔信號之示意圖; 第十三圖為信息信號之示意圖;Figure 8 is a schematic diagram of a read signal; Figure 9 is a schematic diagram of an error signal; Figure 10 is a schematic diagram of an interrupt signal; Figure 11A is an unintended intention of the parallel data bus group of the present invention that has not been connected, Figure B is a schematic diagram of the parallel data bus group initialization of the present invention, Figure 12 is a schematic diagram of a hot plug signal; Figure 13 is a schematic diagram of an information signal;
第十四圖為乒乓路徑之示意圖; 第十五A圖為第一元件發出乒乓讀出信號之示意圖; 第十五B圖為第二元件執行乒乓讀出信號之示意圖; 第十五C圖為第二元件回應乒乓讀出信號之示意圖; 第十六A圖為系統開機時尚未初始化之示意圖; 第十六B圖為第四元件完成初始化之示意圖;Figure 14 is a schematic diagram of the ping-pong path; Figure 15A is a schematic diagram of the ping-pong read signal sent by the first element; Figure 15B is a schematic diagram of the ping-pong read signal performed by the second element; Figure 15C is Schematic diagram of the second element responding to the ping-pong readout signal; Figure 16A is a diagram that has not been initialized when the system is turned on; Figure 16B is a diagram that the fourth element has completed initialization;
第23頁Page 23
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