TWI223750B - Parallel data bus set, data system and method for device communications - Google Patents

Abstract

A parallel data bus set, a data system and a method for device communications within the data system are provided. The parallel data bus set and the data system include a first bus and a second bus configured to connect between two devices for transmitting data. The method for device communications within the data system is to transmit all control signals before any data signal is transmitted. While the control signals and the data signals are transmitted via one bus of the parallel data bus set, the method can transmit reply signals associated with the control signals or the data signal immediately via the other bus of the parallel data bus set as long as the receiver-end device receives sufficient information.

Description

1223750 V. Description of the invention (1) 1. [Technical field to which the invention belongs] And this invention is a parallel data bus group and a method for associating components in the system. Second, [prior art] A data bus is a transmission line that connects a microprocessor (microprocessor) and a random access memory (ram /), which needs to be processed or stored = body. Known data sink ^ Instead, it can be divided into two types: one is a parallel bus (parallel "0, one is a serial bus. The advantages of parallel buses are recognized by the son-in-law and daughter-in-law y ^ ^ u It has a lot of frequency, but it is easy to produce a rwe condition in a frequency environment. The advantage of a serial bus is that it is suitable for ^ = e, and does not need to be controlled by the clock, but an analogy (anal 〇g) design. With the progress of the gate value, more and more components need to use the bus to transmit, and the transmission rate requirements are getting higher and higher. It is known that although the bandwidth of the parallel bus is large, the high frequency When the time and path of the data transfer wheel are different, the race condition will occur, which will cause errors in data transmission. Although the conventional serial bus has no problem in the race condition, it has to have fewer bits, so it must be used. Use high frequency In order to overcome the shortcomings mentioned above, the buses currently used on the market for high-frequency bandwidth use buses with a small number of bits and an analog circuit design of ultra-high frequency, such as USB 2 · 〇 , HTT, SATA, PCI Express, etc., but it is very difficult and costly to integrate analog circuits into the motherboard, and * not all products require such a complex design, so a digital

Page 5 1223750 V. Description of the invention (2) The circuit architecture, but it can be used for high-bandwidth but low-cost and easy-to-design parallel buses is urgently needed. 3. Summary of the Invention The present invention provides a parallel data bus group, a data system, and a method for contacting components. The parallel data bus group includes a first bus and a second bus connected between a first component and a second component for transmitting data and control signals. Among them, if the first component wants to actively perform data transmission with the second component (whether it is to output data to the second component or input data from the second component), the first component first transmits a first signal group to the second Element, and the second element responds to a second signal set to the first element in response to the first signal set transmitted by the first element. When the first signal group is transmitted from the first element to the second element, it is transmitted using the first bus. After the second component receives the first signal group, the second bus responds the second signal group to the first component. The first signal group includes at least a control signal group for requesting the bus and notifying the second component of the action to be performed. If data needs to be transmitted from the first component to the second component, the first signal group also includes a series of data signal groups of characters and lengths to be transmitted. When the first signal group is transmitted via the first bus of the present invention, all the pins simultaneously transmit the control signal group, and if necessary, the data signal group. The data system disclosed in the present invention includes at least a first element and a second element.

Page 6 1223750 V. Description of the invention (3), the first bus bar and the second bus bar. The first element and the second element have an input terminal and an output terminal, respectively. The first bus is a unidirectional parallel data bus, which is respectively connected to the output end of the first element and the input end of the second element. The second bus is also a unidirectional parallel data bus, which is connected to the output of the second component and the input of the first component, respectively.

The method for contacting components in this data system includes the following steps: When a piece of data needs to be transmitted from the first component to the second component, the first component transmits the control signal group to the second component via the first bus to inform the second component. The action the component should perform. If the second component needs to respond to its control signal group, when the control signal group is transmitted, a second response signal group is transmitted to the first component by using the second bus. When the first component transmits data through the first bus, if the second component needs to respond, when the data is transmitted, a second response signal group is transmitted to the first component by using the second bus. Similarly, when a piece of data needs to be transmitted from the second component to the first component, the second component transmits a control signal group to the first component via the second bus to inform the first component of the action to be performed. If the first element needs to respond to the control signal group, when the control signal group is transmitted, a third response signal group is transmitted to the second element by using the first bus. When the second component transmits data via the second bus, if the first component needs to respond, when the data is transmitted, a fourth response signal group is transmitted to the second component by using the first bus. 4. Embodiment The present invention provides a parallel data bus group connected between a first element and a second element for transmitting data. Among them, the first element

Page 7 V. Description of the invention (4) A first signal group transmission —— The first t f one piece transmitted by the component, and the second component is caused by the first piece. For example, the first group is the same as & _L, and responds to a second signal group to the first clock (clock), and the two brothers—the component and the second component have the same clock—the bus 1 and the first component. The parallel data bus group includes a bus 2 when it is sent to the second component. When the first signal group is transmitted from the first element, the first = σ 'f is transmitted using the first bus 1. After the second element group gives the first element f ^, 'the second bus 2 responds to the second signal,' and the second bus 1 and the second bus 2 are independent of each other. It is also mixed with the second component port | pull ^ I still wish 'when the first signal group begins to transmit, the transmission is complete, the second element, whether or not the first signal group has been grouped to the first component. Then, according to its message, immediately respond to the parallel signal to the second signal, '' the first bus 2 and the second bus 2 are single pieces, you must; you need to send 7k from the first component to The second element / segment is sent from the first source to the first element. If any signal needs to be transmitted from the second element, it must pass through A. In this description, a Brother II Bus 2. For the sake of explanation, the receiving law will require the transmitting end element to be regarded as the first element, and the u should be regarded as the first element. + ^ ^ ^. Leyi 7G. Iσ said that the group included at least k & informed the second surname e +, the control signal 'is used to request the bus and what ^ π pieces should be performed without A 4 + bu also includes an i-based action ^, right is necessary , Then the first signal group is familiar with the parallel *, ^ yu 疋 and its length data signals. Different from 1 when transmitting, Ding Ru's busbar 'and the first signal group pass through the first busbar signal of the present invention. For example, some of the pins first transmit control signals at the same time, and then the data is divided into four areas: Γ is not shown. For the convenience of explanation, the first signal group • Di 1 area 11, 2nd area 13, and 1st area Third district 15 and fourth district 17.

Page 8 1223750 V. Description of the invention (5) How many bits are the word or set value? When the first component transmits the first phase (request phase) to the second first bus 1, the second signal ^ is based on the first signal group There are different ways of combining requests, and the leave is not divided into two areas: the fifth area 21 and the sixth area 23. Among them, the first area 11, the second area 13 and the third area 15 are used for transmitting control signals, and the fourth area 17 is used for transmitting data signals or response messages relative to the sixth area 23 when needed. The number “0” in the first figure indicates that the first bus 1 or the second bus 2 is idle (1 d 1 e) 'No signal is transmitted; and the text “χ” indicates the first bus! Or, The second bus 2 is transmitting the first signal group or the second signal group. The text X should be a binary or hexadecimal bit, and has a different number of bits due to different systems. For the convenience of illustration and drawing, In the drawings of this specification, unless otherwise specified, regardless of the text in all sections in the drawing, they are represented by a single word or number. When a command is issued by a dagger, the first element passes the message in zone 11, and this section The first area 11 is a request for requesting the second component to accept the instruction requested by the first component. The set value of the request phase in the embodiment of the present invention is shown in the first table:

Idle (id 1 e) set value 0 bus request (bus reauest) 1 bus grant (bus grant) 2 interrupt 3 ping pong request (ping D〇ng REQ) 4 ping Dong ACK 5 9 pages 1223750

V. Description of the invention (6) 'Bing Ping retry (ping pong retry) 6 Information (m e s s a g e) 7 Bus reset (b u s r e s e t) E Hot plug F

After the message in the first zone 11 is transmitted, the first component transmits the message in the second zone 1 3. This second area 13 is a command phase, which is used to inform the second component of the action to be performed. The setting values of the command phase of this embodiment are shown in the second table:

The set value in the instruction phase is idle 0 I / O read 1 I / O write 2 1 memory read (memorv read) 3 memory write ) 4 memory read line 5 memory write line 6 configuration read 7 configuration write 8 configuration write 8

Page 10 V. Description of the invention (7) The message in the third area 15 is-to obtain data at the location or store the data at f 'to inform the second component of the data phase from which to pass. The fourth area 17 is the data phase transmission relative to the sixth area 23: should = data signal and its length or used to transmit the second area 13 while the first component 13: the message while the second component has been received The message of the first zone 11 can now send the message of the fifth zone 21 in response to the request stage of the first zone 11. In the embodiment of the present invention, the setting value of the fifth response message is the same as that of the first table. While the first component transmits the message in the fourth area 17, the second component has received the message in the third area 15 and the second component can transmit the relevant data signal and its length in the sixth area 23 (Such as when the first component requests to read operation), or send a response message in response to the third area 15 or the J19 area 17 (such as when the first component requests a write operation). In this example, the setting value of the response message in the fourth zone 17 or the sixth zone 2 3 is not as shown in the third table: Response message ___ weekly (idle) ___ A effect (val id) __ ir jJiCstop) ______ 4—

It error_________5__ 一 Table

1223750 V. Description of the invention (8) If the fourth zone 17 or the sixth zone 23 is a data signal and its length, all pins transmit the data length first and then the data signal. It is worth noting that according to the difference between the message in the first zone 11 and the message in the fifth zone 21, the result will affect the existence of the third zone 15, the fourth zone 17 and the sixth zone 23, and may even produce Other areas. That is to say, not all the areas in the second picture must exist, and it depends on the situation. According to the above setting values, the embodiments of the present invention define some basic transmission protocols, as follows:

I. Idle When the first component has no data to transmit, the first bus 1 is idle. As shown in the third figure, each bit of the first signal is π 0π (see the first table). Since the first component is idle and the second component does not need to respond to any message, each bit of the second signal is also π 0π. Bus requests / grants

When data needs to be transmitted to or received from the second component, as shown in the fourth figure, the first component first transmits a bus request setting value π Γ 'in the first area 11 (see the first table), The second component responds to a request from the bus and responds to a bus grant setting value π 2Π in the fifth area 21 (see the first table), informing the first component that the right to use the parallel data bus group has been granted and can continue Send a signal to the second element. If the second component is busy and cannot process the request of the first component or the second component does not exist (removed), as shown in the fifth figure, in the fifth area 2 1

Page 12 1223750 V. Description of the invention (9) In response to an idle set value " 0 " (that is, no response), the first component stops sending a message after receiving a response signal of π οπ. Among them, the other messages in the fourth and fifth pictures are temporarily represented by the text π χπ, and the description thereof will be supplemented later. Third, retry (retry) In response to a bus grant set value "2", due to some factors, such as busy and unable to process the request of the first component, the second component can request the first component to retransmit . As shown in the sixth figure, the second component responds in the sixth area 23 "0Π (representing that the second component cannot process any data), and the first component no longer transmits the signal in the fourth area 17, in an appropriate period of time After that, the first component will try to resend the message. Among them, the number ff 0 " in the 17th area of the fourth area indicates that the first component is in an idle state after it cannot get a response from the second component. When a component wants to perform an input / output write, a memory write, a memory write line, or a set write operation, the first component sends an input / output write, a memory write, The memory write line is either set to write the set value ff π 4 ”, π 6Π or π 8” (see the second table). Because the write operations are similar, the seventh figure and the following description are only based on the memory The body writing is taken as an example, the rest of the writing actions are not described here, and those who are familiar with this memory should be able to follow it. Then, the first component transmits the data signal to be written in the third area 15

1223750 V. Description of the invention (ίο) Address, the second component responds to the current acoustic capacity of the second component in the sixth area 23 (ie, the text "γ" in the sixth area 23 of the figure). If the size of the tributary signal to be written by the first component (ie, the text n L, in the fourth area of the figure 7) is smaller than the capacity of the first component that can be processed, the first component is convenient for the fourth component. Zone 17 transmits all data signals. If the size of the data message to be written by the first component is larger than the capacity that the second component can currently process, then the fourth area 17 = only the amount of data that the second component can currently process. When the first component is transmitting the data signal in the fourth area, if the second 70 = can process the input of the next clock, then the effective set value is transmitted "3" (see table ^), the first component is convenient The next clock continues to send information letters. If the second component cannot process the next-clock data, the idle setting is set to a value of 0, and the first component will not transmit data at the next clock. The component will not continue transmitting until the second component transmits a valid set value again. data. Spear V. Readout The parallel data bus group of the present invention is used to perform the readout of data. The first component can be in two->, input-output readout, memory readout, memory readout line j 疋 s again, buy a set value, r, " y or " 7 "(see The second S * actions are similar, so the eighth figure and the following description only take 5 己 f as an example to read out. Basing & As shown in the eighth figure, "the first component transmits the data to be read in the third area 15 1223750 5. The address of the invention description (11)" The second component responds to the information it can provide in the sixth area 23 Size (that is, the text "L" in the sixth area 23 in the figure). If the data capacity required by the first component γ (that is, the text "γ" in the fourth area 17 in the figure) is smaller than the first, the item can be provided The size of the first component can read the entire amount of data $. ^ The capacity of the data required by the first component is greater than the second component can provide = two right small, then the second component will only be transmitted in the sixth area 23 The number can be raised. Similarly, when the first component is transmitting the sixth, if the first component can process the next one, enter the 3 signal and the 2 signal setting value "3" (see After reading the third table h, if the first two rounds of the "then pass" function input, then the idle setting value " 0 " is transmitted. One clock will not transmit the idle setting and then re-transmit the effective setting value "3" before continuing. And the younger brother 70 wants to end the entire action or transmit the action early. When the first element Stop the set value, 4 ,, (refer to the third table) to pass 4 ~, when the yuan is completed, the stop order will be transmitted. 、 The second element ends the reference. 6. Error If an error value occurs when transmitting the data signal "5" (refer to the third table), request to repeat 3 new transmissions, can send out a wrong setting. As shown in the ninth figure, when the first component is operated-or the eye-catching action is set in the receiving area 23 When the data signal is read and read, a false set value π 5 "is falsely transmitted to inform the" "trick. After receiving the error message, the component in the third area 17 will be in" 70 transmission errors. " The second is idle, waiting for further instructions

The 15th stomach! 22375 05. Description of the invention (12) 7J > ο 7. Interruption After the first element completes something or some special situation occurs and the system needs to be notified to handle it, as shown in Figure 10 The first component can transmit an interrupt setting value "3" in the first area 1 1 (see the first table), and transmit an interrupt code (interrupt number) in the second area 13 to request the second component to receive the interrupt message. Among them, the interrupt code, 'N' is used to indicate which component this interrupt instruction is issued from. 8. Hot-swap As shown in Figure 11A, suppose the first component is a removable component, and When the system was turned on, the two components were not connected, that is, the first bus 1 in the first figure is divided into two parts: the first bus 1 a at the first component end and the first bus 1 at the second component end. Row 丨 b. The initial setting of the embodiment of the present invention is the first bus bar at the first element side 丨 a is connected to a high voltage level through a resistor with a small resistance value, and the first bus bar at the second element side 丨b is connected to a low voltage level through a resistor with a larger impedance value. The first bus line 2 and line 2 in the first figure are also divided into two parts: the second bus bar 2a at the first component side and the first bus line 2a. The second busbar% of the element side. The initial setting of the embodiment of the present invention is that the second busbar 2a of the first element side is connected through a larger impedance value = j, a low voltage level, and the second element side The second bus bar 2b is connected to a high voltage level through a resistor having a small impedance value. The state machine operation is continued, the first element and the second element with

Page 16 1223750

V. Description of Invention (13)

Connected, that is, the first bus bar 1 a at the first component end and the first bus bar 1 b at the second component end are connected to form a first bus bar i, as shown in FIG. 11B. At this time, the first bus bar 1 Generate a current flowing from the high voltage level to the low voltage level (as shown by the dashed arrow) 'Because of the result of the impedance division (the resistance value of a is small), a high voltage will be generated on the first bus Level. As shown in the twelfth figure, 'This result will generate a corresponding hot-swap setting value "F" in the eighth zone 2 5 (see the first table), and then the second component will cut off the first bus 1 The connection to the above-mentioned low voltage level, and a bus reset value '' επ (mai read the first table) is generated in the seventh area, and then the first component cuts off the first busbar and the above-mentioned high voltage. The connection of the voltage level enables the first bus 1 to be initialized to form the state shown in the first figure, and the data transmission can be performed. The hot plugging action of the second bus 2 and the first bus丨 No difference, so I won't go into details.

When the first component needs to send a message (such as a serious error, entering or leaving a sleep state, etc.) to all the components in the system or a specific component, as shown in Figure 13, the first component is in the first area Send a letter in n to the set value π 7Π (see the first table) to the second component, and send the address of the first component in the second area 3 to indicate that the message was sent from the first component, and finally in the third Area 1 5 transmits its information. This message contains the address of the destination component or a message representing all the components. The second component can pass on this information based on its address until the information reaches the destination component. § The first component uses information to notify all components in the system to go to sleep

1223750

V. Description of the invention (14) In the state, all of them automatically go to sleep and give a message to the state, so the second automatically wakes up. When responding, and in accordance with the meta status of this message. When the first element is the second element, but the element is in the fourth zone, the 21st element sends this method again to wake up the other pieces. When the message is transmitted, the system wants to wake up the system brother—the child piece does not need to respond at this time. element. After being handed out, it is also the first to be sleeping. The second element must be-the element must be X. Arbitration

Since both the first element and the second element can actively initiate a bus request action, assuming that the first element and the second element make a bus request at the same clock, the first element and the second element must have an arbitration action to determine Which component is to be qualified by the bus first, it is necessary to define the priority of data transmission between the components first. When two adjacent elements send a bus request at the same time, the element with a higher priority level can obtain the right to use the bus, so the priority level between adjacent rain elements must be different. In this embodiment, the number is defined, and the priority of 'Γ is greater than the number " 〇. As shown in FIG. 14, the priority of using the bus of the first element and the second element is that the second element is greater than the first. One element, so when

When the first component and the first component require the right to use the bus at the same time, the second component can get priority. XI. Bingbing Path As shown in the fourteenth figure, if the first component wants to access a material watch from the third component, the control signal and data signal need to be transmitted through the second component.

Page 18 1223750 V. Description of the invention (15)

The conventional method is: if the first component wants to write data to the third component, the second component can receive all the control signals and data signals sent by the first component and then send it to the third component. The first component does not need to wait. However, if the first component wants to read a piece of data from the third component, the second component can only receive the control signal sent by the first component, and use the retry command to respond to the first component, and then send the control signal to the first component. Three elements. Before the third component sends data back to the second component, the first component must continuously send requests to the second component, and the second component must continue to respond to the first component with the retry command until the second component The component receives data from the third component response. This will waste a lot of time on the first component, especially if the third component is far from the first component. In order to avoid this situation, you can use the ping-pong path to do the reading action to save the continuous retrying action in the middle.

When using the parallel data bus group of the present invention to perform the ping-pong path transmission, as shown in FIG. 14, the second element and the third element are connected by a third bus 3 and a fourth bus 4. The third bus 3 is used to transmit a third signal from the second element to the third element, and the fourth bus 4 is used to transmit a fourth signal from the third element to the second element. Take memory readout as an example. Assume that the first component needs to read a piece of data from the third component. As shown in Figure 15A, the first component sends a ping-pong request setting value π 4Π in the first area 11 (see The first table), a memory read setting value π 3π is transmitted in the second area 13 (refer to the second table), the address of the data to be read is transmitted in the third area 15 and the seventh is transmitted in the fourth area 17 The size of the data to be read. The second component receives the control signal and data transmitted by the first component

Page 19 1223750 V. Description of the invention (18)

Pieces. When the first component transmits data through the first bus, if the second component needs to respond, when the data is transmitted, a second response signal is transmitted to the first component by using the second bus. Similarly, when a piece of data needs to be transmitted from the second component to the first component, the second component transmits a control signal to the first component via the second bus to inform the first component of the action to be performed. The component needs to respond to the control signal. When the control signal is transmitted, a third response signal is transmitted to the second component by using the first bus. When the second component transmits data via the second bus, if the first component needs to respond, when the data is transmitted, a fourth response signal is transmitted to the second component by using the first bus.

In the drawings, the first area 11, the second area 13, the third area 15, the fourth area 17, the fifth area 21, the sixth area 23, the seventh area 19, and the eighth area 25 are all virtual. It is convenient to define and define intervals. In fact, there is no setting of these intervals during data transmission. In summary, the present invention provides a parallel data bus group to solve the disadvantage that the conventional parallel bus is not suitable for high frequencies. At the same time, based on such a parallel data bus group, the present invention also provides a data system and a method for connecting components in the system to speed up and simplify data transmission between components.

Page 23 1223750 Brief description of the diagram V. [Simplified illustration of the diagram] The first diagram is a schematic diagram of the parallel data bus group and data system of the present invention, the second diagram is a schematic diagram of the signal transmission sequence; the third diagram is the idle signal Schematic diagram; the fourth diagram is the diagram of the bus grant signal; the fifth diagram is the diagram of the bus no signal; the sixth diagram is the diagram of the retry signal; the seventh diagram is the diagram of the write signal;

Figure 8 is a schematic diagram of a read signal; Figure 9 is a schematic diagram of an error signal; Figure 10 is a schematic diagram of an interrupt signal; Figure 11A is an unintended intention of the parallel data bus group of the present invention that has not been connected, Figure B is a schematic diagram of the parallel data bus group initialization of the present invention, Figure 12 is a schematic diagram of a hot plug signal; Figure 13 is a schematic diagram of an information signal;

Figure 14 is a schematic diagram of the ping-pong path; Figure 15A is a schematic diagram of the ping-pong read signal sent by the first element; Figure 15B is a schematic diagram of the ping-pong read signal performed by the second element; Figure 15C is Schematic diagram of the second element responding to the ping-pong readout signal; Figure 16A is a diagram that has not been initialized when the system is turned on; Figure 16B is a diagram that the fourth element has completed initialization;

Page 23

Claims (1)

1223750 6. Scope of patent application, even 1 · A parallel data bus set (Para 1 1 e 1 databusset) # connected between a first element and a second element, the first element transmits a signal To the second element, the second element is in response to the first signal. · L A second signal is sent to the first element, and the parallel data bus is grouped. ≫# 杂 由 The first bus ( first bu s) for transmitting the first element to the second element; and > from the second bus (sec ο ndbus) for the second, ^ second The element is transmitted to the first element; > When the first signal is transmitted and before the ^ th signal is transmitted t%, the second signal is transmitted to the first bus via the second bus. A component 2. The parallel data bus group as described in item 1 of the scope of patent application. The first bus and the second bus are one-way parallel data pools 3 as described in item 2 of the scope of patent application. The parallel data bus group, the first signal includes a control signal Number to inform the second component of the action it should perform. # ^ 4. According to the parallel data bus group described in item 3 of the scope of patent application, the first signal in ^ further includes a data signal, which is a series of characters to be transmitted. When the first signal passes through the first When a bus is transmitted, the control signal is transmitted first, and then the data credential is transmitted. 5. The parallel data bus group as described in item 4 of the patent application scope, wherein the control signal includes: —request phase ), Including idle, bus request, interruPt, and soldier request η 1223750 VI. One of the instructions such as patent application scope (ping pong REQ), message (message), hot plug (hot plug); and a command phase (c 〇nun and P hase) 'Including idle, memory read One of the instructions is memory read, memory write, memory ^ * memory line, etc. 6. The parallel data bus group as described in item 5 of the scope of patent application, wherein the second signal includes one of the commands such as idle, bus grant, retry, error, ping-pong response, bus reset, etc. 7. A parallel data bus group connected between a first component and a second component, the first component sends a first signal to the second component, and the second component corresponds to the first signal, Sending a second signal to the first element, the first signal includes: a data signal, which is a series of characters to be transmitted; and a control signal 'for informing the second element of the action to be performed; the parallel data The bus group includes: a first bus, which is a unidirectional parallel data bus, for transmitting the first signal from the first element to the second element; and a second bus, which is a A unidirectional parallel data bus for transmitting the second signal from the second element to the first element; wherein when the first signal is transmitted through the first bus, the control signal is transmitted first and then transmitted. The data signal. 8 · The parallel data bus group according to item 7 of the scope of patent application, wherein when the first signal starts to be transmitted and before the first signal is transmitted, the second signal is transmitted to the second bus through The first element. / Page 26 1223750 6. Patent application scope 9. The parallel data bus group described in item 8 of the patent application scope, wherein the control signal includes: a request phase, including idle, bus request, interrupt, soldier request, One of the instructions such as information, hot swap, etc .; and an instruction phase, including one of the instructions such as idle, memory read, memory write, and memory write line. 10. The parallel data bus group according to item 9 of the scope of the patent application, wherein the second signal includes one of the instructions such as idle, bus grant, retry, error, ping-pong response, bus reset, and the like. 11. A parallel data bus group connected between a first component and a second component, the first component sends a first signal to the second component, and the second component sends a first signal in response to the first signal A second signal to the first element, the first signal includes: a data signal, which is a series of characters to be transmitted; and a control signal, which informs the second element of the action to be performed; the parallel data bus The set includes: a first bus, which is a unidirectional parallel data bus, used to transmit the first signal from the first element to the second element; and a second bus, which is a unidirectional A parallel data bus for transmitting the second signal from the second element to the first element; wherein when the first signal is transmitted through the first bus, the control signal is transmitted first, and then the data signal is transmitted And after the first signal starts to be transmitted, and before the first signal is transmitted, the second signal is transmitted to the first element via the second bus. 1223750 VI. Scope of patent application ^ A request phase, including one of the instructions of idle, bus request, interrupt, ping-pong request, information, hot plug, etc .; and an instruction phase, including idle, memory read, memory Write to memory, write line, etc. / ° ^ 1 6 · The data system as described in item 15 of the patent application scope, wherein the response signal includes idle, bus grant, retry, error, ping-pong response, One of the bus reset instructions. ^ 1 7 The data system described in item 16 of the scope of patent application 'wherein or when a component and the second component have not been connected by the first bus and the second bus, the first The output terminal of the component is connected to a high voltage level inside the first component, the output terminal of the second component is connected to the second voltage, an internal high voltage level, the input terminal of the first component It is connected to a low voltage level inside the first element, and the input of the second element is connected to a low voltage level of the second element. When the data system is powered on, and the first element and the When the second component is connected with the first bus and the second bus, the output terminal of the first component and the output terminal of the second component are cut off from the high voltage level, respectively. The input terminal of the first element and the input terminal of the second element respectively cut off the connection to the low voltage M level to complete the initialization of the first bus and the first bus. 18 · The data system as described in item 16 of the scope of patent application, wherein the data system further includes a third element having an input terminal and an output terminal. When the first το needs to pass through the second component, When transferring with the third element, the first element transmits the ping-pong request instruction to the second element in the control signal. 1223750 6. Scope of patent application. When the second element receives a response from the third element, the soldier's response command is transmitted in the response signal. 1 9. A method for contacting components in a system, the system comprising: a first component having an input terminal and an output terminal; a second component having an input terminal and an output terminal; a first bus bar, It is a unidirectional parallel data bus connected between the output of the first element and the input of the second component; and a second bus is a unidirectional parallel data bus connected to the The output terminal of the second component and the input terminal of the first component; the method includes the following steps: (a) when a piece of data needs to be transmitted from the first component to the second component, perform step (b) and step (C) when a piece of data needs to be transmitted from the second element to the first element, execute steps (d) and (e); (b) the first element transmits a control signal to the first bus via The second element is used to inform the second element of the action to be performed. If the second element needs to respond to the control signal, when the control signal is transmitted, use the second bus to send a first response signal to the second bus. First element; (c) the first The component transmits the data through the first bus, and if the second component needs to respond to the data, when the data is transmitted, the second bus is used to transmit a second response signal to the first component; (d) the The second component sends a control signal to the first component via the second bus to inform the first component of the action to be performed. If the first component needs to respond to the control signal, when the control signal is transmitted, Transmitting a third response signal to the second element using the first bus; and 1223750 眞 Stream, transfer the data, if the first data-the first component-the scope of the patent application (e) the second component via the _., ~ „A component needs to respond to the data, in the data transmission When using the first bus to transmit a fourth response signal 炱 ... ⑵ ^ ^ 2 0 · The method described in item 19 of the patent application scope, wherein the first element and the second element each have a priority Level, when step (a) is performed, if a piece of data needs to be transferred from the first component to the second component, and at the same time a piece of data needs to be transferred from the second component to the first component, the component with a higher priority level Can be transmitted first. 2 · The method as described in item 19 of the scope of patent application, wherein the control signal includes: ° & a request phase, including idle, bus request, interruption, soldiers' surname, information, heat One of the instructions, such as plugging and unplugging; and the instruction phase of Ming and Yi, including one of the instructions such as idle, memory read, memory write, memory write line, etc. -In, 2 2 The method described in item, wherein The first, second, third, and fourth response signals include one of the commands such as idle, bus grant, last error, ping-pong response, and bus reset. Wu, 2 3 · A data transmission method, using Meanwhile, the method includes providing a first unidirectional parallel bus to connect the first component and the #component 'to request, request, address, and data signals. A first component is transmitted by the first component; and a first component: a second unidirectional parallel bus is provided to connect the first component with the first component and the first component Page 31 A 'Patent application scope element, used to transmit request, instruction, address and data signal from the second element to the first element; the first element generates a first request, a first instruction, A first S signal is combined with a first signal of a first data signal and transmitted to the second component via the first to one-way parallel bus. The second component generates a second request and a second instruction. A second address and a second signal combination of a first data signal, and transmitted to the first component through the second unidirectional parallel bus; wherein the second signal combination in the second signal combination The request, the second instruction, the second address, and the second data signal correspond to the first request, the first instruction, the first address, and the first data signal in the first signal combination, respectively. 24. The method of claim 23, wherein the first element and the second element have a high priority and a low priority. 2 5 · The method described in item 23 of the scope of patent application, wherein the first request signal and the second request signal may be one of the following: an idle signal, a bus reQuest signal, a bus Bus grant signal, interrupt signal, ping pong REQ signal, Ping pong ACK signal, ping pong retry signal, message signal ;, Bus reset signal, hot plug signal | Tiger 〇26 • The method as described in item 23 of the scope of patent application, wherein the first command signal and the second command signal can be The following I / O read signal, I / O write signal 1223750 VI. Patent application scope: 3 tigers, s ++ meinory read signal, Lüji tenth write (memory write) signal, memory read line (memoryread 1 ine) signal, memory A memory write line (memorywrite 1 ine) signal, a configuration read signal (5), and a setup write (Configuratl0nwrite) signal. _ 2 7. The method / set described in item 23 of the scope of the patent application. Among them, the Haidi shell material signal and the second data signal may include column I ^ stop (st0, idle signal, valid ( valid) error signal. The method, in which the first data 28. As in the scope of the patent application No. 23 = yuan and data length bit. The signal and the second data signal include the capital position