TWI223402B - Whirlpool-like microstructure having spiral conductor layer and manufacturing method thereof - Google Patents

Abstract

The present invention provides a whirlpool-like microstructure having spiral conductor layer and manufacturing method thereof. The method comprises forming a 3D structure on the substrate; forming the required microstructure model of photoresist on the surface of the 3D structure; electroplating metal conductor layer on the surface of the 3D structure; and removing the microstructure model of photoresist, so as to form the floating and whirlpool-like microstructure having spiral conductor layer. The whirlpool-like microstructure having spiral conductor layer of the present invention is applied in the micro-inductor structure of microelectronic system.

Description

1223402

Correction _____ V. Description of the invention u) [Technical field to which the invention belongs] The present invention relates to a vortex-like microstructure with a spiral conductive layer and a method for manufacturing the same, and particularly to a microinductor structure applied to a microelectronic system The spiral microstructure with a spiral conductive layer and its manufacturing method 0 [Previous technology] Inductors are the most critical passive components in RF integrated circuits. At present, the most commonly used RF inductors are planar spiral inductors. Planar spiral inductors are prone to produce various clutter effects such as parasitic capacitance and eddy currents, making it impossible to improve the Quality Factor. Factors affecting the quality factor of the inductor include metal wire eddy current, metal wire DC resistance, substrate eddy current, and parasitic capacitance between the metal wire and the substrate. At the same time, the planar spiral inductor occupies a relatively large substrate area and limits the circuit density of the substrate. In order to improve its quality factor and reduce the area of the substrate occupied by the inductor, on the one hand, the contact area with the substrate can be reduced by levitation components to reduce the influence of the substrate eddy current and the parasitic capacitance between the metal wire and the substrate; Can be designed to change the knot to avoid various clutter effects and enhance mechanical strength. For example, the 3D Solenoid Inductor uses a floating solenoid inductor structure to isolate the substrate from the inductor and reduce clutter effects. However, because the magnetic field generated is parallel to the surface of the wafer, the adjacent electrical values of the same distance will be larger than the planar spiral inductance. Therefore, in order to reduce the mutual inductance, the distance between the three-dimensional solenoid inductance needs to be increased, resulting in a circuit area that can be used on the substrate. The eddy current of the metal wire with reduced planar spiral inductance is caused by the full current induced on the inner wire by the outer wire, which mainly occurs in the helix.

IH, page 6 i ^ J402 Number five, description of the invention (2) The smaller the diameter of the inner ring, the smaller the magnetic field, and the larger the magnetic field. At the same time, the solution is to reduce the plane screw method, which will increase the metal conduction. efficacy. [Summary of the Invention] The present invention is directed to the above-mentioned problem-like microstructure and a method for manufacturing the same, and senses the structure. The invention can be applied to the suspended microstructure of the conductive layer, which can improve its quality factor and reduce the vortex microstructure of the conductive layer disclosed in the present invention. The spiral conductive layer, the three-dimensional spiral vortex microstructure. According to the present invention, the three-dimensional spiral conductive layer can pass through the direct current resistance of a few metal wires, and because the three-dimensional spiral conductive helix metal wires are not in the same magnetic field as the inner coil wires, the clutter formed on the surface of the substrate is induced into clutter. Effect, such as substrate capacitance, and can increase the vortex-like microstructure of the conductive layer disclosed in accordance with the present invention. Because the linear DC resistance of the inner ring of the metal spiral inductor caused by the plane screw, The line eddy current is also larger; the metal line width is' but the inductance cannot be played, and the application of the inductance is provided to reduce the electrical inductance occupation technology. The conductive layer is included for micro-increase and will not be caused by the electrical layer being a plane. The technology of the shape of the micro-eddy current plate is based on the basic invention of spiral microelectronics due to its sense and basis: a base is formed in the spiral of the electronic system, which can increase the current in three dimensions; the structure is used for metal. In the method of the invention, the micro of the spin-shaped conductive layer subsystem provides a method for the clutter plate area of the three-dimensional plate. A thick metal wire with a plate and a micro-inductive conductive layer integrated on the surface of the substrate reduces the three-dimensional spiral suspension structure of the outer ring and the vortex electrons of the conductor and the substrate. A structure is formed to reduce the current, and the structure of the line to generate a conductive layer can reduce the area of the circuit. Provide a spiral with the following steps:

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A substrate is provided, and a groove of a desired shape is etched on the substrate. A spiral conductive layer is formed on the groove to form a vortex-like microstructure, and unnecessary portions of the plate are removed. [Earth Embodiment] The present invention provides a microstructure and a manufacturing method thereof, particularly a microinductor structure applied to a microelectronic system. The microinductor structure can exert the maximum effect by an effective structure. The present invention achieves the aforementioned object by forming a spiral conductive layer on the surface of the substrate and forming a vortex microstructure. The first embodiment of the present invention is a micro-inductive structure applied to a radio frequency integrated circuit (RF IC), which is a vortex-like microstructure having a spiral conductive layer. Such microstructures are not limited to microinductor structures, but also include microelectronic resonator structures, microelectronic inductive coupling microelectronic capacitor structures, microelectronic waveguide structures, micromechanical spring structures, microelectronic connector structures, microelectromagnetic valve structures, micro Electromechanical resistance micro-hole heater structure and micro magnetic levitation structure. In the microstructure of the present invention, the vortex center end of the vortex microstructure formed by the spiral conductive layer is directed toward the substrate or away from the substrate, and the present invention does not exclude the formation of an intermediate having other functions on the substrate. Layer, the spiral-shaped microstructure with a spiral conductive layer of the present invention, the length and width of the open end of which are 50 " 111 to 900 " 111, and the height of which is 50 " m to 600 " m. 1 to 9 are cross-sectional views and a top view of a series of processes of a micro-inductance structure according to the first embodiment of the present invention. Such a micro-inductance structure can be applied to a microelectronic architecture of a semiconductor integrated circuit. As shown in Figure 丨, this is a cross-sectional view of a semiconductor integrated circuit micro-inductive structure manufacturing process according to the first embodiment of the present invention, which includes the following steps. A silicon single crystal substrate is provided, and a first protection is formed on the bottom surface and the surface of the silicon single crystal substrate, respectively. Layer 11 and second protective layer, and then using photolithography technology

Page 8 1223402 Amendment No. 91108fiRn 5. Description of the invention (4) Definition of the surface of the silicon single crystal substrate The second protective layer forms the second protective layer a ', 12b'12c, among which' single single crystal substrate (whether or not ion-doped) It is a (100) silicon single crystal substrate, and the thickness of the silicon single crystal substrate is about 50 to 600 m. The first protective layer and the second protective layer 12a, 12b, 12c can be used as a protective layer material commonly used in the conventional technology of semiconductor integrated circuit microelectronic architecture. The material can be selected from silicon oxide, silicon nitride, and silicon oxynitride. Compounds, quality protection materials and photoresist protection materials. The first protective layer 11 and the second protective layers 12a, 12b, and 12c according to the embodiment of the present invention are all made of silicon nitride. The thickness of the material is 80 Angstroms to 10,000 Angstroms or more. Number! The adjacent second protective layers 12a, 12b, and 12c shown in the figure, the second protective layers 12a * 12b, and the second protective layers 12b and 12c are fixed with a same pitch, and this pitch is about 70 °. Claw to 70 0. To further illustrate Fig. 1, the distance between the adjacent second protective layers 12a, 12b, and 12c is used to define a pair of apertures of a single crystal silicon substrate. Fig. 2 is a cross-sectional view showing the manufacturing process of the micro-inductor structure of the semiconductor integrated circuit according to the first embodiment of the present invention, which is a subsequent process step of Fig. 丨, including the use of the second protective layer 12a of the single crystal silicon substrate, 12b and 12c are anisotropically etched and the first protective layer U is used as an etch stop layer to etch to form a single crystal silicon substrate 10a, 10b, .1 0C (as shown in FIG. 2), and then The regions surrounded by the monocrystalline silicon substrates 10a, 10b, and 10c define the grooves 16a and the grooves, that is, the grooves Ua and the grooves 16b of the inverted pyramid pyramid shape as shown in FIG. 2 . The monocrystalline silicon substrate of the first embodiment of the present invention uses a 25% to 35% by weight hydroxide off (K0H) solution as a money engraving agent, and maintains the etching temperature. Page 9 12234402 __case number 91108650_ _ 年月 日 条 正 _ V. Description of the invention (5) The degree is between 80 and 90 degrees Celsius. As shown in Figure 2, the single crystal silicon substrates 10a, 10b, and 10c have an inclined angle after etching. (54.7 degrees) wall structure, this inclination angle conforms to the crystal surface of (100) single crystal silicon substrate. The first embodiment of the present invention applies a non-isotropic etching method to etch the single crystal silicon substrate. The first embodiment of the present invention uses a conventional potassium hydroxide (KOH) solution to anisotropically etch a (100) monocrystalline silicon substrate, and the monocrystalline silicon substrate is etched with a tilt angle (54.7 degrees). Inverted pyramidal pyramidal groove on the wall. The single crystal silicon substrate used in the present invention can be applied to conductive substrates, semiconductor substrates, and dielectric substrates; the shape of the grooves of the present invention is not limited to an inverted pyramid pyramid shape, and may include a cone shape, an elliptical cone shape, an irregular cone shape, a triangle The shape of the conical 'rectangular cone' and the polygonal cone is a three-dimensional structure. FIG. 3 is a cross-sectional view showing the manufacturing process of the micro-inductor structure of the semiconductor integrated circuit according to the first embodiment of the present invention, and FIG. 3 shows the process steps subsequent to FIG. 2. Figure 3 shows the use of buffered hydrofluoric acid (β0E) to remove the second protective layer 12a, 12b, 12c and the first protective layer 11 of the single crystal silicon substrate; and then using a low pressure chemical vapor deposition method ( LPCVD) grows 2 // m high silicon content nitride nitride (S i NX) layer as a low stress layer, the ratio of nitride to nitrogen of the nitride nitride layer is about 3 to 4 (Si3N4) to 1 to 1 ( SiN). The thickness of the silicon nitride layer is about 1000 Angstroms to 5000 Angstroms. In addition, there are many methods that can be applied to grow low stress layers, such as plasma enhanced chemical vapor deposition (PECVD), radio frequency plasma chemical vapor deposition (RPCVD), microwave plasma chemical vapor deposition (MPCVD) )Wait. Fig. 4 is a plan view of a semiconductor integrated circuit micro-inductive structure manufacturing process according to the first embodiment of the present invention. Fig. 4 is a plan view of Fig. 3

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Figure 4 shows the inverted gold characters of the grooves 16a and 16b of the single crystal silicon substrate. FIG. 5 is a cross-sectional view of the semiconductor integrated circuit micro-inductance structure manufacturing process of the first embodiment of the present invention, and FIG. 5 shows the process steps of FIG. 3 ^ ^. Provide an adhesive layer to join the monocrystalline substrate and the complementary semiconductor integrated circuit wafer (CMosic Wafer) 22 to form a semiconductor integrated circuit. The man-made plate 20 'enables the grooves 16a and recesses of the early-crystal silicon substrate. The grooves 16b are respectively conductively bonded to the conductive layers 22a and #electric layers 22b of the complementary metal-oxide-semiconductor integrated circuit wafer 22; and then the adhesive at the bottom of the groove 16a and the groove 16b is removed by an oxygen plasma to expose the complementary metal-oxide semiconductor integrated circuit. The conductive layer 22a and the electrical layer 22b of the circuit wafer 22 are chemically polished (chemicai mechanicai ish, CMP) to remove the low stress layer on the surface of the single crystal silicon substrate, leaving only the stress layer 14a and the groove on the inner wall surface of the groove 16a. The stress layer Mb on the inner wall surface of 16b, and the material of the bonding layer can use conventional semiconductor materials, polymer bonding materials, polyamino polymer bonding materials, photoreactive polymer bonding materials, and photoresist bonding materials. First, the thickness of the subsequent layer is about 1 to 10 // m. ^ The semiconductor integrated circuit substrate 20 of the first embodiment of the present invention includes a silicon single crystal substrate and is formed inside and on the surface (except for the conductive layers 22a and 22b): (1) a plurality of microelectronic devices and (2 ) A plurality of additional layer structures (such as a dielectric layer and a dielectric structure and a conductive layer and a conductive structure); all microelectronic substrates used in the conventional technology can be used as the general circuit substrate of the present invention. Conservation Volume As shown in FIG. 5, it is a cross-sectional view of a semiconductor circuit micro-inductance structure manufacturing process according to a first embodiment of the present invention, with a recess 16 &

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= 2 Stomach 2 forms a semiconductor integrated circuit substrate 20, and the low-stress layer 14 covered by the surface of the single crystal silicon substrate is removed by chemical mechanical polishing, leaving only the stress layer 14a on the inner wall surface of the groove 16a and the inner wall surface of the groove 16b. The stress layer Ub and the adhesive at the bottom of the grooves 16 a and 16 b of the single crystal silicon substrate are exposed to expose the conductive layer 22 a and the conductive layer 22 b of the complementary metal-oxide semiconductor integrated circuit wafer 22. FIG. 6 is a plan view of FIG. 6. As shown in FIG. 6, a plan view of a microinductance structure manufacturing process of a semiconductor integrated circuit according to the first embodiment of the present invention is shown. A single crystal substrate is bonded to a complementary metal-oxide semiconductor integrated circuit chip. 22, the grooves 16a and 16b of the single crystal substrate are aligned with the conductive layers 22a and 2b of the metal oxide semiconductor integrated circuit wafer 22, and the resin at the bottom of the grooves 16a and 16b is exposed to conduct electricity The layer 22a and the conductive layer 22b, and the low-stress layer 14 covered by the surface of the single-crystal silicon substrate are ground away, and only the low-stress layer 14a on the inner wall surface of the groove 16a and the low-stress layer 14b on the inner wall surface of the groove 16b remain. FIG. 7 is a cross-sectional view showing the manufacturing process of the micro-inductor structure of the semiconductor integrated circuit according to the first embodiment of the present invention, and FIG. 7 is a process step subsequent to FIG. 5. A copper seed layer is vapor-deposited on the grooves 16a and 16b of the single crystal silicon substrate, and a uniform plating photoresist is plated on the surface of the copper seed layer; The photomask is aligned with the grooves and exposed to develop a photoresist microstructure model. The electroconductive layer is electroplated on the photoresist microstructure model and the unnecessary copper seed layer and photoresist are removed. As shown in Figure 7, the required spiral shape is formed. The conductive layer 26 is combined with the low stress layers 14a and 14b on the surface of the groove to form a vortex-like microstructure; the thickness of the spiral conductive layer 26 is about 0 Angstrom to 100,000 Angstrom and the line width is about 0 μm to 50 / zm. FIG. 8 is a top view of FIG. 7, and FIG. 8 is a top view of the semiconductor integrated circuit architecture process of the first embodiment of the present invention.

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Surfaces of grooves 16a and grooves 16b. Spiral conductive of the present invention. Top view of a second embodiment of the present invention. Although the grooves 16a and 16b of the present invention are shown in Table 2 6 'The present invention can cover the direction of the vortex-like microstructure with the electric layer in the first embodiment of the present invention' The present invention also includes a convex surface with a spiral conductive surface The spiral end point is formed to point away from the substrate square structure 0 to form a double-loop spiral conductive layer 2 6 in series. The layer also has a loop pattern as shown in Figure 9 of the semiconductor integrated circuit micro-inductance series loop pattern. Examples 8 and 9 show a spiral conductive layer having only two turns of a conductive wire on the surface, and a spiral conductive layer having 0 to 500 turns of a conductive wire. The spiral conductive layers shown in FIGS. 1 to 10 have a spiral shape. The end of the vortex-like microstructure is directed toward the substrate. The end of the vortex-like microstructure is directed toward the vortex-like microstructure away from the square layer of the substrate. The vortex-like microstructure can be formed when it protrudes from the conductive layer on the substrate surface. A vortex-shaped microjunction with a spiral conductive layer is shown in FIG. 10. This is a cross-sectional view of the semiconductor integrated circuit micro-inductance and fabrication process of the first embodiment of the present invention. Figure 7 follow-up, step, using etching The method removes the silicon single crystal substrate region and only retains the suspended structure formed by the low stress layer of the silicon single crystal substrate to complete the Twin-Tornado Inductor of the first embodiment of the present invention. For the other engraving methods, potassium hydroxide can be used. (KOH) solution for wet etching or dry etching with electropolymerization, as shown in Figure 10, a cross-sectional view of the semiconductor integrated circuit architecture process of the first embodiment of the present invention, low stress on a silicon single crystal substrate The layers 14a, 14b and the spiral conductive layer 26 form a suspension structure, and the complementary metal-oxide-semiconductor integrated circuit wafer 22 is bonded through the bonding layer 24. [Effect of the invention] According to the present invention, the spiral-shaped microstructure with a spiral conductive layer and its manufacture

Page 13 1223402 ------ Case No. 91108650_Year Month Date __ V. Description of the invention (9) Twin-Tornado Inductor completed by Fang 'can reduce the RF integrated circuit (RF IC) occupies an area on the surface of the substrate, and it can lift the circuit density to the surface of the substrate. At the same time, it can be manufactured separately from the complementary metal-oxide semiconductor integrated circuit (CMOS 1C) without interfering with each other to reduce the yield; it can also eliminate various clutter effects. Effective, the suspension structure design of the double tornado inductor can eliminate the parasitic capacitance and eddy current of the integrated circuit substrate; the three-dimensional vortex-like microstructure can also avoid the eddy current of the metal wire which is often generated by the planar spiral inductor, and the general planar spiral In order to avoid the eddy current of the metal wire, the inductance should not be too wide to make the resistance of the planar spiral inductor difficult to reduce. The three-dimensional spiral microstructure can reduce the resistance by increasing the thickness of the spiral conductive layer without increasing the line width. Therefore, the Twin-Tornado Inductor of the embodiment of the present invention can select an appropriate spiral conductive layer line width to reduce the eddy current effect, and can increase the thickness of the spiral conductive layer to reduce the resistance as much as possible. . The above are only the preferred embodiments of this creation, and are not intended to limit the scope of implementation of this creation; that is, all equivalent changes and modifications made in accordance with the scope of the patent application for this creation are covered by the scope of this creation patent .

1223402 _Case No. 91108650_ 年月 日 __ Brief Description of Drawings Figure 1 is a cross-sectional view of the microinductor structure manufacturing process of a semiconductor integrated circuit according to the first embodiment of the present invention; Figure 2 is a semiconductor device according to the first embodiment of the present invention Cross-sectional view of a micro-inductor structure manufacturing process of integrated circuit; FIG. 3 is a cross-sectional view of a micro-inductance structure manufacturing process of a semiconductor integrated circuit according to a first embodiment of the present invention; FIG. Top view of the manufacturing process of the inductor structure; FIG. 5 is a sectional view of the manufacturing process of the micro-inductance structure of the semiconductor integrated circuit according to the first embodiment of the present invention; and FIG. 6 is a plan view of the manufacturing process of the micro-inductance structure of the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view of a process of manufacturing a micro-inductance structure of a semiconductor integrated circuit according to a first embodiment of the present invention; FIG. 8 is a plan view of a process of manufacturing a micro-inductance structure of a semiconductor integrated circuit according to a first embodiment of the present invention; Top view of a parallel pattern of a micro-inductor for a semiconductor integrated circuit according to a second embodiment of the present invention; and FIG. 10 is a micro-inductor for a semiconductor integrated circuit according to the first embodiment of the present invention Cross-sectional view of the configuration process. [Symbol description] 10a single crystal chip substrate 10b premature chip chip substrate 10c premature chip chip substrate

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Brief description of the drawings 11 First protective layer 12a Second protective layer 12b Second protective layer 12c Second protective layer 14 Low stress layer 14a Low stress layer 14b Low stress layer 16a Groove 16b Slot 20 Semiconductor integrated circuit substrate 22 Complementary gold Oxygen semiconductor integrated circuit 22a conductive layer 22b conductive layer 24 next layer 26 spiral conductive layer sheet

Claims (1)

Ϊ223402 $ No. 91108650 The scope of the patent application is a microstructure, which includes: a substrate; and a three-dimensional spiral conductive layer; the spiral conductive layer is formed on the surface of the substrate to form a vortex microstructure, and the length and width of the open end are It is 50 / zm to 900 / zm, and the height is 50 / zm to 600 // Π1. The microstructure according to item 1 of the scope of patent application, wherein the vortex center end point of the vortex-shaped microstructure points toward the substrate. The microstructure according to item 1 of the scope of the patent application, wherein the vortex center end point of the vortex-like microstructure is directed away from the substrate. A microelectronic structure includes: a microelectronic substrate; and a three-dimensional spiral conductive layer; the spiral conductive layer is formed on the surface of the microelectronic substrate to form a vortex microstructure, and the length and width of the open end are 50 // m to 900 μπι, with a height of 50 // m to 6 0 0 β m. The microelectronic structure according to item 4 of the scope of patent application, wherein the spiral conductive layer is applied to a microinductor structure. The microelectronic structure according to item 4 of the scope of patent application, wherein the vortex center end point of the vortex-shaped microstructure is directed toward the substrate. 7. The microelectronic structure according to item 4 of the scope of the patent application, wherein the vortex center end point of the vortex-like microstructure is directed away from the substrate. 8 · A method for manufacturing a microstructure, comprising: providing a substrate, and engraving a groove in a desired shape on the substrate; and forming a spiral conductive layer on the groove to form a spiral six 4. 6. Month correction Page 17 "223402 Six case number 91108650 __ 务 月 日 修 矣 _ Patent application scope microstructure, the length and width of the open end of the vortex structure are 5 0 // in to 9 〇 0 // m, the height is 5 0 # m to 6 〇〇 # ffl. 9. The method for manufacturing a microstructure according to item 8 of the scope of the patent application, wherein the vortex center end point of the vortex-like microstructure is directed toward the substrate. 1 〇 · The manufacturing method of the microstructure as described in item 8 of the scope of the patent application, wherein the vortex center end point of the vortex-shaped microstructure points away from the substrate 0 A method for manufacturing a microelectronic structure 'includes A microelectronic substrate; and forming a spiral conductive layer on the microelectronic substrate to form a vortex microstructure, the length and width of the open end of the vortex structure are 50 # m to 900 " m, and the height is 50. Am to 600em. 1 2 · The method for manufacturing a microelectronic structure according to item 丨 丨 of the scope of patent application, wherein the spiral conductive layer is applied to a microinductor structure. 1 3 · The method for manufacturing a microelectronic structure as described in item 丨 丨 of the scope of patent application, wherein the spiral center end of the vortex-shaped microstructure is directed toward the substrate. 14 · The method of manufacturing a microelectronic structure as described in item 11 of the scope of the patent application, wherein the spiral center end of the vortex-like microstructure is directed away from the substrate. Page 18