TWI222722B - The method of fabricating multi-bit memory cells and their operations - Google Patents

Abstract

The present invention discloses a multi-bits memory cell device. Its manufacturing method is first to provide a semiconductor substrate on which a gate dielectric layer, a polysilicon layer and the first patterned photoresist layer have been formed. The first patterned photoresist is used as etching masks to etch away portions of the polysilicon layer and form the gate electrodes. After removing the dielectric portion on the substrate surface, a conformal oxide dielectric layer is formed onto the gates and substrate. Another conformal insulating layer is then formed on the oxide layer. The third layer of oxide dielectric layer is formed onto the insulating layer. The tri-layer spacers are formed at the side-walls of the gates with oxides after etching these oxide/insulator/oxide layers. The semiconductor substrate is then implanted to form the source and drain regions with the gates and tri-layer spacers as implantation masks on the substrate. Finally, the top portions of gates and source/drain regions are exposed and reacted with metals to form silicides after removing the oxides on the surface of the substrate.

Description

1222722

V. Description of the invention (l) Description of the invention: The technology of the present invention relates to a memory unit, and more particularly, to a method and a structure for manufacturing a memory unit having a memory cell. The manufacturing process of related parts is completely compatible, and it can increase the memory density per unit area, and can perform multi-bit memory. Earlier, the previous technology of electrical erasable programmable read-only memory (EE p RQ Μ) is a memory element widely used in today's information electronics πα, which originally had the disadvantages of erasing speed, '; large, costly, but with the Advances in process technology have recently produced EEPROMs, which are relatively fast. They are commonly referred to as flash memory (composed of Flash Kjf 'when writing data, applying high voltage to the control gate = = F〇wmdheiim The punch-through effect allows electrons to penetrate the dental emulsified layer from the drain region and reach the floating gate electrode to increase its critical voltage TZTrldrltag6):

= Source region 'makes the aforementioned implantation into the floating layer; the T layer flows into the source region or the substrate, and the gate electrode is broken. In the past ten years, the original critical voltage M has been reduced in the past ten years. In the field of non-volatile memory, how to use the method of storing electronic disks = :, 5 o'clock multi-technology is the function of research (erase), and high-capacity squares // + to repeat reading and writing And erase the goal of hard research and development. / Second consumption, volume, etc. are all in the middle of the industry, with a single record ", HfeJ (FIash Memory) ^, ^ -p 心 早 7 ^ ce1 1) as the unit bit of memory not only can use electronic Way to achieve the function of reading and writing, can even 1222722, invention description (2) erase a block of memory space (sector or page) at the same time / so fast > flash memory not only has faster reading speed The advantages of flash memory and the absolute advantage of low initial cost are, therefore, flash memory is one of the most important components in the current semiconductor industry. Please refer to Figure 1a, '1a' for details. Schematic diagram of the memory unit. When the conventional memory is to be programmed, it is connected to the control pole 105. ^ A voltage is applied, and the hot electrons are from the source 10 of the silicon substrate 10. The la passes through the gate oxide layer 102 and enters the floating gate 1 03. Please refer to FIG. lb and FIG. lb is a diagram showing the erasing of the conventional flash memory memory unit. When the conventional flash memory is desired When performing the erasing action, it is tied to the control pole ^ plus low voltage or zero The voltage is applied to the drain 101b of the Shixi substrate 101 = Γ electrons, that is, k $ the moving electrode 1G3 passes through the interlayer oxide layer 102 and returns to the source 1 0 1 a. From this we can know that the conventional knowledge is divided; Fast, which simplifies the layout because it can be used each time. If a memory unit can handle two individuals, it can be flashed for the entire flash memory at a time. § The memory can be flashed once. The unit plane performs data block erasure at the same time to reduce the number of memory cells in a memory unit that has one block to store or erase data. The number of memory cells that are programmed or erased. Divide the number of processed data sets by area and its cost. Data 'represents a record, so the flash memory processes the number of data sets, which is twice.

Page 8 rI222722 V. Description of the invention (3) In view of this, the number of bits of the manufacturing method is based on the above-mentioned method, including the lower dielectric layer, and conformity to the semiconductor base gate and the semiconducting layer. A gate electrode and a gap are formed on the oxide layer side to pass directly under the semiconductor and expose the surface. According to the above items: half of the conductive region, in which the dielectric layer and the side wall of the shape electrode, are in the source and drain region. Another embodiment of the present invention can be flashed in the south. The purpose of performing the dielectric layer at the bottom of this step is The invention of a floating gate memory provides: providing a semiconductor layer with an insulating layer formed on the surface of the substrate; a three-layered insulating layer / an insulating layer /; The gate and source of the channel formation surface; and a process of forming a source and a predetermined distance from providing a multi-bit memory cell and pole, and increasing the amount of data that can be processed. A multi-bit memory cell is manufactured on a square substrate. The semiconductor has a gate electrode and a gate electrode to remove compliance. Next, an oxide layer is etched on the conductive base and the drain region is separated. The insulating layer is formed by performing ions on the bottom of the three layers of the gate. The source is formed on the exposed surface. The present invention further provides a multi-bit memory substrate. A gate and a source-drain region are formed on the semiconductor substrate. A predetermined lateral distance is formed on the semiconductor substrate; a three-layer spacer is used to store electrons or charges; and a surface of metal silicon and a gate electrode. One purpose is to provide a multi-bit memory one-touch engraved mask, a dielectric layer; a layer; a gap wall outside the conformable electrode sidewall on the oxidation; an implantation step, an oxide layer between the pole region and the gate electrode; Metal silicidation-Zhuoya 'encapsulation and source extraction; a gate' is formed in the gate compound to form the electrical operation of the element

1222722 V. Description of the invention (4) Method for writing and erasing data. According to the above purpose, in the method of the present invention, on a multi-bit memory cell substrate, the gate electrode has a gap wall formed on the first side of the element, a second gap wall forms a second memory unit, and a first source> and The polar region includes a source-drain with a certain current, that is, the first write value is stored in the first source without storage. According to the above-mentioned operation method, the conductor substrate gap wall-shaped unit is a second source drain, and the first The following steps on the two sides: when a drain or zero potential is applied to the region, a memory cell is 1; and when a sub or charge is applied to the second drain region, the purpose is written for the sub or charge. The present invention, more In bit memory, the gate has a second gap-shaped memory unit formed on the first side, the second region, the second side

In addition to the multi-bit memory cell provided by the present invention, a write operation of the multi-bit memory cell has a gate formed on a semi-conductive first side and a second side, and a first gate. A first memory sheet is formed on the side wall of the electrode and a semiconductor substrate is formed on the side wall of the gate electrode on the second side as a side. A first semiconductor substrate is formed on the second side and a gate is applied to the gate. Write voltage; the first write voltage is applied to the second source-drain region and the first gap wall has a stored electron or charge write value of 0; if there is no stored electron or charge, the source-drain region applies a drain write Voltage, and constant current or zero potential, the write value of the second gap wall device or the second memory cell is 0, and the input value is 1. A multi-bit memory cell erasing unit is further provided with a gate, and the gate is formed on a side wall of the gate of the half of the first side and the second side to serve as a first memory on the second side. A second source is formed on a semiconductor substrate having a first edge formed on a semiconductor substrate having a side edge on a side wall of the edge gate.

Page 10 1222722 V. Description of the invention (5) The drain region includes the voltage drawn at the first source and at the second voltage, then the unidirectional anisotropic charges of the first and second memories are erased. According to the operation method of the above purpose, a 'gap wall' is formed in the unit on a multi-conductor substrate, a second is a second memory, a source region and a polar region, and the polar region includes a lower first source drain region plus a certain current, and a memory cell It is 1; "-" timing is applied to the second power electrode region, that is, the write value of the second record is 1; > and a low voltage or zero electricity is applied to the electrode region.

The following steps ... Apply a first erase power to the gate electrode region and apply a second erase source region to the gate electrode region. When the source drain region and the second source drain cell are neutralized with the writing process, the first The memory sheet is added with a gate erasing voltage; a current or a first erasing electric current or a second erasing the carrier current or the same direction as the first memory unit, respectively; / 丨 Children's reading of the memory element 70 memory sheet 70 has a gate, the gate is formed on a gate with a first side and a second side, a side wall of the gate of the first side The upper side is formed as a gap wall on the second side < n # ^ 〇〇〇〇4 遌 < the gate side wall is a unit, and the semiconductor substrate on the first side is formed with the semiconductor substrate on the second side The upper opening occupies ... A second source column step is formed on the Toe: applying a-idle write voltage on the closed electrode; ... a drain write voltage, and storing electrons in the second source drain region = the first gap wall Or charge, that is, the write value is G '. If there is no stored electron or charge, write to the volume and the pole. Walls having two or charge storing electronic, electrical or electronic storage without storage, and? No .: The factory idle electrode reads the electricity; At the second source: The pole: buy the electricity μ, and apply one to the _ source drain region, there is a conduction between the source source and the second source drain region:

1222722

m-th read-out value of the memory cell]; when the first-source drain region has no conduction current between the source and the source, the read-out value is 0; a drain-reading voltage is applied to the first source ^ electrode region And a voltage or zero potential is applied to the second source-drain region, and there is a conduction thunder between the first source-drain region and the second source-drain region within two days, that is, the reading value of the first 6-h cell is 1; When there is no conduction current between a source drain region and a second source drain, the read value of the second memory cell is 0. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following A preferred embodiment will be given in detail, in conjunction with the accompanying drawings, as follows: ° 5. Description of the invention (6)

Embodiments: Please refer to Figs. 2a-2h. Figs. 2a-2h are schematic cross-sectional views showing the formation of a multi-bit memory unit according to the present invention. First, referring to FIG. 2a, a gate dielectric layer 202, a conductive layer 203, and a patterned photoresist layer 213 are sequentially formed on a semiconductor substrate 201. Among them, the semiconductor substrate 201 is, for example, a silicon substrate; the material of the gate dielectric layer 202 is, for example, an oxide layer; and the material of the conductive layer 203 is, for example, a doped polycrystalline silicon layer or a doped epitaxial chip layer.

Referring to FIG. 2b, the patterned photoresist layer 213 is used as an etching mask, the conductive layer 203 is etched to form a gate electrode 203a, and then the patterned photoresist layer 去除 is removed. Please refer to Fig. 2c. Next, the exposed surface is divided to leave the open-electrode dielectric layer 2 under the closed-electrode 203a. ;: Electrical layer 2 ° 2 Please refer to Figure 2d. An oxide layer 2 0 4 is formed on the surface of the semiconductor substrate 201 and the gate 2 03a. The insulating layer 2 4 is, for example, silicon dioxide. (S 丨 〇2)

Page 12 1222722 5. Description of the invention (7) or oxide layer such as hafnium dioxide (Hf02). Next, "continuously form an insulating layer 205 on the surface of the oxide layer 204. The insulating layer 205 is, for example, a nitride layer, and the material choice of 2.05 can also be narrower than that of the insulating layer. Electrical material (E nergygap · 3 ~ 6 e V). Please refer to Figure 2e to form an oxide layer 2 0 6 on the insulating layer 2 0 5 '. The material choice of 2 4 and 2 6 can also be a dielectric material with a larger energy gap than the insulating layer ( Energy gap: 5 ~ 9eV). w Refer to 苐 2f figure 'to perform anisotropic lapping on the two layers to form a three-layer barrier wall composed of an oxide layer 204a / insulating layer 20 5a / oxide layer 206a on the side wall of the gate electrode 20 03a. Among them, the method of anisotropic etching is, for example, reactive ion etching (RIE) or plasma etching. Next, using the gate electrode 2 03a and the spacer 204a / 2 05a / 206a as a mask, a doping step is performed on the semiconductor substrate 201 to form a source on the semiconductor substrate 201 on the side of the gate electrode 203a> and The polar region 201a'SOltKSouirce / DrairO is shown in Figure 2g. Please refer to FIG. 2h, and then perform a self-aligned petrification step on the semiconductor substrate 201 to form a metal silicide on the surfaces of the gate electrode 203a and the source-drain regions 201a and 201b 2 0 7 a / 2 0 7 b / 2 0 7 c, for the purpose of turning on the source / drain and gate; “Metalite” 207a / 207b / 207c is, for example, TiSi2 or “SiSi2” Record (CoSi2) or Shi Xihua record (NiSi). Please refer to Figs. 3a-3b. Figs. 3a-3b are schematic cross-sectional views of the present invention for writing a multi-bit memory cell using a bias voltage and a current source. Please refer to Fig. 3a. First, apply the metal oxide 207c on the gate electrode 203a.

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Add 1 to 10 Volts ® Α Φ NET, 17 -L ^ ^ > 1 .. ^ 20 ^? &Quot; ^ ^ ^ ^ ^ ^ ^ 201a v, ,, +% + 1 to 1 A write voltage of 10 volts drain-ΓΑΐΓΛ two source metal oxides on the source region 201b strikes the applied electrode '2101' current source 1sp. At gate 203a and the first source

Two == 6a will appear in the semiconductor substrate 201, ^ ,,, and hungry, because the channel between the source drain region and the gate is maintained: ^ 5, the carrier will be injected and stored to the first Between the source and drain sides 20a ',': f. Therefore, it can be seen that the function of the spacer 2 0 5 a formed by using an oxide layer / insulating layer / nitride layer composed of an oxide layer is similar to the conventional flash. The floating gate of the memory can store the carriers from the source; therefore, first, the spacer wall 20a on the side of the source drain region 201a will be defined as a code of 1 '', and + is not stored. After the second source drain region 2 0 丨 b side of the spacer wall 2 0 5 b will be interpreted as "〇". In this way, the group memory unit π χ Π is written into π XI " Or "χ〇". Refer to Figure 3b, the same principle, when the memory cell is to be written, 1 γ π 7 'is the same as the metal oxide 2 0 7 c at the gate 2 3 a. Apply a gate write voltage Vgp of 1 to 10 volts, and apply a drain write voltage Vdp of 1 to 10 volts to the metal silicide 20 7b in the second source drain region 20 lb, A constant current source Isp of InA to 1 mA is applied to the metal silicide 207a of the first source-drain region 20 la. Below the gap 20 6b between the gate 203a and the second source-drain region 201b A channel of hot carrier current will appear in the semiconductor substrate 201, and the source region and the electrode region have a predetermined distance from the channel directly below the gate, so the hot carrier will be injected and stored to the second source drain electrode 2 0 1 b side of the partition wall 2 0 5 b.

Page 14 1227222 V. Description of the invention (9) Therefore, as long as the position of the source-drain region applied by the drain write voltage Vdp and the source constant current source I sp is controlled, the multi-bit memory cell can be easily determined "χγ " The code to be defined is “〇〇” or “0 丨”, or “1〇” or 11 1 Γ; and, if the definition of a multi-bit memory unit is coded as “丨 丨,”, only the drain The write voltage Vdp and the source constant current source Isp are sequentially applied to the source-drain regions 2 〇 1 a and 2 0 1 b on both sides of the gate 203a. Μ Refer to Figure 3c'3c Shows a schematic cross-sectional view of erasing a multi-bit memory cell using a bias and a current source according to the present invention. Please refer to FIG. 3c, and apply a 10 to 0 volt gate wiper to the metal silicide 207c of the gate 203a. Divide the voltage Vge, and apply a constant current source 1 (16 or 1 to 10 volts of erase voltage) of 11 ^ to 1011 ^ amps on the Month lithium oxide 207 & of the first source drain region 201a. ¥ (16, and apply a constant current source of 1 ^ or 1011 amps 1 ^ or 1 to 10 volts on the second source drain region 20 lb of metal stone = compound 2071) Divide the voltage Vse. 间隙 The second source drain regions 20ia and 20b side of the spacers 205a and 205b will 1 = be written again, which is different from those previously stored in the spacers 205a and 205b. Heterosexually written carriers will be neutralized by the heterosexual carriers, or will be attracted to the carriers stored in the spacers 205a, 20 ”; in this way, the first night: the source drain region 2 〇la, 20lb side partitions 20 5a, 20 5b will be erased. Κϊ: Rong can make the multi-bit memory unit provided by the present invention and production, horse, /, The type of data to be written is determined by controlling the write voltage and constant voltage and constant ^ f applied by the source drain region, and the erased data can be erased by applying an erase current source. In addition to effectively increasing the unit Time

1222722 V. In addition to the amount of data processed in the invention, it can be easily coded to achieve the purpose of effectively reducing costs. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouches without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be determined by the scope of the attached patent application.

Page 16 1222722 Brief description of the diagram Does Huang Uj say: The stylized illustration of the flash memory memory unit Figure 1a shows the conventional diagram. Figure 1b is a schematic diagram showing the erasing of the 2% K ° body memory unit in the conventional physical reading. The figure is a sectional view showing the formation of a multi-bit memory cell according to the present invention. = Yan ib_ The figure is a schematic view of the cross-section of the present invention using a bias and a current source to write multi-bit memories. Brother 3c is a diagram showing the use of bias voltage and current source to erase multi-bit memory. RSJUS: S / D ~ source region; S ~ source region; d ~ drain region;

VgP ~, write voltage between poles; Vdp ~ write voltage without poles;% Ide ~ constant current source; Vge ~ gate erase voltage

We ~ drain wiper voltage; Vse ~ source wipes the silicon substrate; 10a ~ source; n 101b ~ drain; 102; 104 ~ oxide layer; 103 ~ floating gate丨 〇5 ~ control gate; 201 ~ half 〃conductor substrate; 02, 2 02a ~ gate dielectric layer; 2 0 1 a ~ first source drain; 2 〇1 b ~ second source drain · 122722 The diagram briefly explains 203 ~ conductive layer; 2 0 3a ~ gate; 213 ~ patterned photoresist layer; 204, 205, 206 ~ insulation layer; 204a, 20 5a, 2 0 6a ~ barrier wall; 207a, 20 7b, 20 7c ~ metal silicide; 208 ~ Charge trapping storage area.

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Claims (1)

1222722 6. Application for Patent Scope Application_Please Special Purpose 彳 Scope 1 ·· 1 · A method for manufacturing a multi-bit memory cell, which includes γ Γ 歹 丨] provides a semiconductor substrate with a dielectric layer on the semiconductor ^: A closed electrode is formed on the layer; and the far dielectric is engraved with a titanium mask on the semiconductor substrate, and the semiconductor substrate is decorated and exposed to expose the dielectric layer on the surface; / 'Nano to the gate and the semiconductor substrate The conformation on the surface forms a gasification layer on the oxide layer and the conformation forms an insulation layer 'connector, and then forms an oxide layer on the insulation 2' compliance, and performs an etching step on the three layers. An oxide layer / insulating layer / 枭 2 is formed on the outer side of the oxide layer on the electrode side wall, and a three-layer gap wall is formed in the layer. The gate electrode and the gap wall are used as a mask, and an ion implantation step is performed on the semiconductor substrate to A source-drain region is formed on the semiconductor substrate, wherein the source-drain region forms a predetermined distance from a channel directly below the gate; a person "is formed on the surface of the gate and the source-drain region exposed on the surface A gold compound. '2 ^ The method of manufacturing a multi-bit memory cell described in item 1 of the scope of the patent application-the dielectric layer is a gate oxide layer. 3. If an application for true brake # _ is applied, as many as described in item 1 The manufacturing of bit memory cells is extremely doped with polycrystalline stone layers or doped stupid stone layers. No. 19 1 1222722 6. Scope of patent application 4. The method for manufacturing a multi-bit memory cell as described in item 1 of the scope of patent application, wherein the etching step is anisotropic etching. 5. The method for manufacturing a multi-bit memory cell as described in item 4 of the scope of patent application, wherein the anisotropic etching is an ion-reactive etching or a plasma etching. 6. The method for manufacturing a multi-bit memory cell according to item 1 of the scope of the patent application, wherein the oxide layer is a stone dioxide layer or a dielectric material having an energy gap greater than that of the insulating layer. 7. The method for manufacturing a multi-bit memory cell as described in item 1 of the scope of patent application, wherein the insulating layer is a nitride layer or a dielectric material having a smaller energy gap than an oxide layer. 8. The method for manufacturing a multi-bit memory cell according to item 1 of the scope of the patent application, wherein the metal silicide is titanium disilicide, cobalt disilicide, or nickel silicide. 9. A multi-bit memory cell, comprising: a semiconductor substrate on which a gate and a source drain region are formed, wherein the gate and the source drain region have a predetermined lateral distance; a gate dielectric An electrical layer is formed on the semiconductor substrate; a gap wall is formed on the sidewall of the gate with an oxide layer / insulating layer / oxide layer to store electrons or charges; and a metal silicide is formed on the source drain Pole area and the surface of the gate. Page 20 1222722 6. Scope of patent application W · The multi-bit memory cell as described in item 9 of the scope of patent application, in which the σ-interlayer " electric layer is a gate oxide layer. ^ The multi-bit memory cell according to item 9 of the patent application scope, wherein the gate is doped with a polycrystalline silicon layer or an epitaxial silicon layer. ~ 3 doors :: ΐ The multi-bit memory cell described in item 9 of the Scope of Lithium, in which the intermediate insulating layer of the two spacers is a nitride layer or the energy gap is less than the reading ^ Φ 13. Such as the metal 14. The unit has a One side of the gap wall memorizes the single drain region of the polar region, and the gate is formed on the first side of the gate for multiple silicided species of the application, and the gate is formed on the first side. : Fan: The multi-bit memory cell described in Item 9, which is -second titanium or cobalt disilicide or nickel silicide. : Write operation method of the memory cell, the multi-bit memory unit and the 1-pole shape "on the base of the body, the poles" ^ the first side, a brother-spacer is formed in the first On the wall as a first memory unit, a second :: side of the semiconductor substrate is formed on the semiconductor substrate; = side of the semiconductor substrate is formed with a row of steps: add a pole Write voltage; Yu Yu adds a drain write voltage and draws the second source on page 2112222 6. When a certain current is applied to the polar region of the patent application range, when the first / gap wall has stored electrons or charges, that is, the write value of the first memory cell is 0, and the write value is 1 if there is no cast stored electron bite charge. ; And applying the drain write voltage to the second source drain region, and applying a certain current to the first source drain region, the second gap wall has stored electrons or charges. The cell write value is 0. If there is no stored electron or charge, the write value is 1. 1 5 · Write of multi-bit memory cell as described in item 14 of the scope of patent application The operation method further includes a step of erasing the multi-bit memory unit by ultraviolet rays. The write operation method of the multi-bit memory cell according to item 14 of the scope of the patent application, wherein the gate write voltage is greater than the boundary voltage of the multi-bit memory cell. 1J. A method for erasing a multi-bit memory cell, the multi-bit memory premature element has a gate, the gate is formed on a semiconductor substrate, the gate has a first side and a second On the side, a first gap wall is formed on the side wall of the gate on the first side as a first memory unit, and a second gap wall is formed on the side wall of the gate on the second side to As a second memory cell, a first source and a pole region are formed on the semiconductor substrate on the first side, and a second source and drain region are formed on the semiconductor substrate on the second side. The method includes the following steps: Page 22 1227222 6. Application scope of patent application on the gate-gate erase voltage is applied to the first source and drain region of a first house, and the second source and drain region is applied-纟 ϋ-第- When erasing the voltage, the first source erases the current or the second erasing unit and the second erasing unit: There is:: load and "" and the first-that the-memory unit and When the second memory sheet or charge is: 1 8 · A read unit of a multi-bit memory cell has a -gate, which is formed at ::: 美 = bit memory has -first-side and a second On the bottom of the side: the side wall of the gate on one side of the closed electrode is regarded as a first self-made product, f is formed on the second gap wall, formed on the second side, and a second drain electrode is formed. Region, the first: side =; = = a -th-source region is formed on the bottom, including the following steps: / A second source is formed on the substrate to draw a gate write voltage on the gate; =: add 3 = 施 ;;: =; :: With and in the second slave Γ is the -memory unit 丄 ::. The wall is written with a value of 1;…, stores electrons or electricity in the first source The pole region applies the drain write voltage, and the pole region applies a certain current, so that the first source is drawn from the second memory cell: 0 wall ^ why the write value is 1; ..., stored electrons OR Electricity Page 23 1227222 6. Scope of patent application: Apply a gate read voltage to the gate; apply a drain read voltage to the first source drain region, and apply a certain amount to the second source drain region Voltage; when there is a conduction current between the first source source and the second source region and the second source source; that is, the read value of the first memory cell is 1; the first source drain region and the second source drain When there is no conduction current between the electrodes, the read value is 0; the drain read voltage is applied to the second source drain region, and a certain voltage is applied to the first source drain region; the first source drain region When there is a conduction current between the second source and drain, that is, the read value of the second memory cell is 1; and the drain read voltage is applied to the second source and drain region, and the first source and drain are drained. When a certain voltage is applied to the electrode region, and there is no conduction current between the first source electrodeless region and the second source electrodeless region, the second memory is Read element of the read value of 0. 19. The method of operating the first patentable scope as many as 18-bit memory, such as application units, wherein the gate voltage is greater than the threshold voltage write multi-bit memory cell of. Page 24