JP2710194B2 - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly to a nonvolatile semiconductor memory device having a floating gate electrode and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a writable / erasable nonvolatile memory element, a floating gate electrode is provided via a first gate insulating film on a region between a source region and a drain region on the surface of a semiconductor substrate. Further, a field effect transistor (EPROM) in which a control gate electrode capacitively coupled to a floating gate electrode via a second gate insulating film is further formed thereon is known. In this storage element, a difference in threshold voltage due to a difference in charge storage state of the floating gate electrode is stored as data “0” or “1”.

When information is written to this storage element,
The control gate electrode is set to a positive high potential to form a channel on the substrate surface, and a positive voltage is applied to the drain region. At this time, electrons traveling in the channel receive energy due to the high electric field generated on the channel and are injected into the floating gate electrode beyond the potential barrier formed by the first gate insulating film. In this writing operation in which the state where electrons are injected into the floating gate electrode is a writing state, it is extremely important to lower the writing voltage. For example, in the flash memory market where writing is performed electrically and all bits are collectively erased electrically, the current 1
There is a strong demand for the transition from 2V / 5V dual power supply to 5V single power supply or 3V single power supply, but for that purpose, a lower voltage is required in the write operation.

Conventionally, a floating gate type field effect transistor having an offset region between a source region and a portion immediately below a gate electrode has been proposed as a semiconductor memory device for realizing such low voltage writing. About this element, IDM Technical Digest magazine (IEDM Technical Digest),
584-587, 1986, IEE Electron Device Letters (IEEE)
Electron Device Letters),
EDL-7, pages 540-542, IEDM Technical Digest (IEDM T
technical Digest), p. 315-p.
18, 1991, IEEE Electron Device Letters (IEEE Electron)
Device Letters), Volume 13, 46
5 to 467, 1992, etc., the operation of which causes the SEEPROM (source side
Injection (Source-Side Inje)
ction EPROM)).

FIG. 11 is a sectional view showing the structure of a SEEPROM. Drain region 10 through the P-type silicon substrate 1 of the drain region 10 _D and a source region 10 _S and the surface of the floating gate electrode 4b of the portion sandwiched between in the first gate insulating film 3
_D , and at a position having an offset area (L _OFF ) with respect to the source area 10 _S ,
The control gate electrode 6a is formed on the floating gate electrode 4b via the second gate insulating film 5. In this device, since the offset region (L _OFF) is a high resistance, the control gate electrode 6a, even when the voltage applied to the drain region 10 _D is relatively low, occurs a strong electric field concentration in the channel region on the source side, this Hot electrons obtained energy by the high electric field can be injected into the floating gate electrode 4b.
Note that erasing is performed by discharging electrons from the floating gate electrode by the FN tunnel current.

This SEEPROM was prototyped, and the relationship between the writing time and the threshold voltage (writing characteristics) was actually measured.

On the surface of a P-type silicon substrate 1, a film thickness of 10 nm
Gate insulating film 3 made of a silicon oxynitride film, a floating gate electrode 4b having a thickness of 150 nm, a second gate insulating film 5 made of a silicon oxide film having a thickness of 20 nm, and a film thickness of 200 n
After forming the control gate electrode 6a of m
0 _S, the drain region 10 _D of the acceleration voltage 70 keV, after implanting arsenic at an implantation density of ^{3 × 10 15 cm -2, 900} ℃,
It was formed by thermal diffusion for 30 minutes. This ion implantation is performed by providing an ion implantation mask having an offset length L _OFF between the gate electrode and the source on the drain side in a self-aligned manner with the gate electrode, and performing a SIEPRO.
An M structure was formed.

FIG. 12 shows a gate length of 0.1 m.
9 is a graph showing actually measured write characteristics of a SEEPROM having a gate width of 6 μm and a gate width of 0.8 μm. Offset length L
_The writing speed increases with an increase in _OFF .

Next, the results of breaking a SEEPROM by a two-dimensional device simulator will be described.

[0010] Figure 13 (a), (b), each gate length 0.5 [mu] _m, for SIEPROM of L OFF = 0.2 [mu] m, and the channel direction electric field strength _{E X} in potential φ and the channel surface in a write operation initial calculated respectively The result. As voltages during the write operation, the potential V _CG of the control gate electrode is 12 V, and the drain voltage V _D is 3
V, the source voltage _{V S} is 0V, the substrate voltage _{V B} is 0V. The potential V _FG of the floating gate electrode at the beginning of the writing operation is 6.6V. Now, as shown in FIG. 13 (b), the channel direction electric field strength E _X has a sharp peak E _m at the end of the source side. Similarly, SEEP of L _OFF = 0 to 0.2 μm, obtained by a two-dimensional device simulator
The value of _{E m} for ROM shown in FIG. 14. Here, as is apparent, the electric field on the channel that occurs during a write operation in SIEPROM is determined by the offset length _{L OFF,} the maximum electric field strength _{E m} on the channel increases with increasing _{L OFF.}

According to the Lucky Electron Model, for example, IEE Transaction on Electron Devices (IEEE Tr)
action on Electron Dev
ices) Volume ED-31, Page 1116-1125
P. 1982),

I _g = I _d ∫exp (−φ _b / qEmλ) P (Eox) dx ≒ CI _d exp (−φ _b / qEmλ)

## EQU1 ##

[0014] Here, I _d is the drain current during a write operation, phi _b silicon - potential barrier between the silicon oxide film, lambda is higher scattering mean free path of electrons, P (E _OX) is a silicon - silicon oxide film The probability that electrons injected into the silicon oxide film at the interface flow into the silicon oxide film, C is a constant. According to the above equation, the gate current I at the time of writing is
To increase the _g is effective increase in E _m. FIG.
Considering the calculation results shown in Fig. 4, L _OFF is increased and E
By increasing _m , the writing speed of the SEEPROM can be improved. This agrees with the measurement result shown in FIG.

[0015]

As described above,
The electric field on the channel during the write operation in the SEEPROM is determined by the physical offset length. To lower the write voltage, the offset length L _OFF
And the electric field strength on the channel needs to be increased. However, an increase in the offset length L _OFF decreases the read current of the element and increases the element area,
This is an obstacle in designing a fine element capable of high-speed reading. Further, in order to suppress variations in element performance, it is required to precisely control the offset length L _OFF .
When the manufacturing process technology is the same, the yield is reduced as compared with a normal EPROM having no offset forming step.

[0016]

SUMMARY OF THE INVENTION A nonvolatile semiconductor memory device according to the present invention comprises an N-type drain region and a source region selectively formed in a P-type region on the surface of a semiconductor substrate; A floating gate electrode selectively covering the surface of the P-type region sandwiched between the first and second regions through a first gate insulating film, and a control gate attached to the surface of the floating gate electrode through a second gate insulating film And a three-terminal field effect having an offset region between the source region and immediately below the floating gate electrode.
In a nonvolatile semiconductor memory element composed of a transistor ,
A P ⁺ -type region having a higher concentration than the P-type region is provided in the offset region.

Further, according to the method of manufacturing a nonvolatile semiconductor memory element of the present invention, a step of forming an element isolation structure on a semiconductor substrate having a P-type region on a surface portion to partition an element formation area; Forming a first gate insulating film by covering the surface of the semiconductor substrate, depositing a first conductor film, and patterning the first conductor film while leaving the first conductor film on the element formation region and the vicinity thereof to form a floating gate conductor. Forming a film;
Forming a second gate insulating film by covering the floating gate conductive film, depositing a second conductive film, and then forming the second conductive film;
Patterning a second gate insulating film and a conductive film for a floating gate to form a stacked gate structure crossing a central portion of the device forming region; and forming a stacked gate structure not provided with the stacked gate structure in the device forming region. On the other hand, a step of injecting predetermined ions into a certain source forming region to form a P ⁺ type region, and a step of forming a spacer on a side surface of the stacked gate structure on the side of the source forming region to perform ion implantation to perform an N type source Forming a region and a drain region.

[0018]

According to the above-mentioned means, even if the offset length is constant, the resistance value of the offset region can be set by the impurity concentration of the P ⁺ type region. It can be performed more widely and freely than when it is set. As a result, it is possible to obtain the maximum value E _m for large channel direction electric field strength by the write operation, it is possible to increase the write speed.
That is, it is possible to lower the write voltage without increasing the offset length.

Further, in the prior art, the writing characteristic is determined by the offset length determined by film formation and dry etching in the manufacturing process. However, according to the above-described means, P ⁺ determined by ion implantation and thermal diffusion. The offset length can be selected according to the impurity concentration of the mold region,
The degree of freedom in process design is increased, and an element having uniform write characteristics can be manufactured.

[0020]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention.

In this embodiment, the boron concentration is 2 × 10 ¹⁵ c
An M- ³ P-type silicon substrate 1 (or a P ^- type silicon substrate having a P-well formed thereon,
At a concentration of the surface portion of the well and the drain region 10 _D and the source region 10 _S of N type selectively formed in a surface portion of 2 × ¹⁰ 15 ^{cm -3),} a drain region 10 _D and a source region 10 _S A floating gate electrode 4b for selectively covering the surface of the sandwiched P-type silicon substrate region via a first gate insulating film 3 (a silicon oxide film having a thickness of 10 nm) and a second gate insulating film on the surface of the floating gate electrode 4b 5 (20n thickness
m, a control gate electrode 6a which is applied to the source region 10S and the floating gate electrode 4
b, the offset area (offset length L
_OFF ), a P ⁺ -type region 13 having a higher concentration than the P-type silicon substrate 1 is provided in the aforementioned offset region.

Incidentally, for example, L _OFF = 0.1 μm to 0.1 μm.
13 μm, source / drain region at accelerating voltage 70 ke
V, after the ion implantation of arsenic with an implantation density ^{3 × 10 15 cm -2, 900} ℃, formed by thermal diffusion of 30 minutes, accelerating voltage 70keV a ^{P +} -type region, injection density 4 × ¹⁰ 13 cm
After injecting boron at ^-2, it was formed by thermal diffusion at 900 ° C. for 30 minutes.

FIG. 2A shows a SIEPRO according to this embodiment.
9 is a graph showing the write characteristics of M. Gate length 0.6
μm, a gate width of 0.8 μm, and L _OFF = 0.13 μm, V _CG = 12 V, V _D = 3 V, V _S = V _B = 0
Threshold voltage V when writing is performed under the condition of V
The measured value of _TM change is shown.

Further, FIG. 2 (b) is a diagram showing the relationship between the boron implantation of SIEPROM and write voltage _{V DW} and write current _{I DW.} Where V _DW and I
_DW is the minimum drain voltage and current necessary for injecting hot electrons into the floating gate electrode at the write start voltage and current.

It can be seen that the larger the boron (B) implantation amount, the higher the writing efficiency. Alternatively, a smaller offset length is required to make the writing efficiency the same.

FIGS. 3A and 3B show the SEEP of this embodiment.
Is a graph showing the simulation result of the distribution and the channel direction electric field strength E _X potential φ in the write operation early ROM. E _X is the value of the channel surface (at a depth 1.10μm in FIG. 3 (a)), the gate length 0.5
[mu] _m, L OFF = 0.1 [mu] m, the voltage of the write operation, the potential _{V CG} is 12V of the control gate electrode, the drain voltage _{V D} is 3V, the source voltage _{V S} is 0V, the substrate voltage _{V B} is 0V.

[0028] As is apparent from FIG. 3 (b), the channel direction electric field strength E _X on the channel, with a sharp peak E _m at the end of the source side. This peak intensity _Em is shown in FIG.
Conventional SIE with L _OFF = 0.2 μm shown in (b)
It is almost the same as that of the PROM. That is, a small offset length L _OFF, it is possible to obtain a large channel direction maximum field strength E _m.

Next, a second embodiment of the present invention will be described.

FIG. 4 is a sectional view of a semiconductor chip showing a second embodiment.

[0031] This example N coupled to the source region 10s in the surface portion of the ^{P +} -type regions 13a ^- -type source region 14 are al provided. Others are the same as in the first embodiment. The conditions for forming the P ⁺ type region 13a are the same as those in the first embodiment, and N ⁻
The mold source region has an acceleration voltage of 40 keV and an injection density of 4 × 10
After phosphorus is implanted at ¹³ cm ⁻² , thermal diffusion is performed at 400 ° C. for 30 minutes.

[0032] Figure 5 is the N ^- -type source region of an impurity (phosphorus)
5 is a graph showing a relationship between an ion implantation concentration, a read current, and a write time. Here, the read current is V
_{When CG} = 12 V, V _D = 1 V, and V _S = V _B = 0 V, the drain current value ( _IDS ) and the writing time are V _CG =
_12V, V _{D = 3V,} when performing write at V _{S =} V B ₌ 0V, the time required for the threshold voltage is changed to 6V from 1V. It can be seen that by increasing the impurity concentration of the N ⁻ type source region, it is possible to increase the read current without significantly reducing the writing speed. This is very important for high-speed reading of cells. Thus, increasing the read current at the same time, can be kept large although the writing speed inferior first embodiment, although the resistance value of the offset region becomes smaller N ^- type source region and the P ^{Since the} impurity profile is steep around the intersection with the ⁺ type region (point A in FIG. 4), a large E _m is required during writing.
Is obtained.

Next, the manufacturing method of the second embodiment will be described.

First, as shown in FIG. 6A, a P-type silicon substrate 1 having an impurity concentration of 2 × 10 ¹⁵ cm ⁻³ (or a P ^- type silicon substrate having a P-well formed thereon) may be prepared. Then, a trench or a field oxide film 2 is formed as an element isolation structure to divide an element formation region, and a first gate insulating film 1 and a first conductor film 4 are sequentially grown on the element formation region. For example, the first gate insulating film 1 has a thickness of 10n.
As the silicon oxynitride film and the first conductor film 4, a 150 nm-thick polysilicon film doped with impurities can be used.

Next, as shown in FIG. 6B, the first conductive film 4 is patterned to form a floating gate conductive film 4a covering the element forming region and its vicinity, and then the second gate insulating film 5 is formed. Then, the second conductive film 6 is grown. Here, as the second gate insulating film 5, for example, a thickness of 20
nm ONO trilayer film (silicon oxide film / silicon nitride film / silicon oxide film), and as the second conductor film 6,
A 200-nm-thick tungsten polycide film (tungsten silicide film / polysilicon film) can be used.

Next, as shown in FIG. 7A, the second conductive film 6, the second gate insulating film 5, and the floating gate conductive film 4a
Are sequentially patterned by anisotropic dry etching to form a stacked gate structure including the floating gate electrode 4b, the second gate insulating film 5, and the control gate electrode 6a. The stacked gate structure traverses the central portion of the element forming region, and the control gate electrode is usually processed so as to be connected to the control gate electrode wiring.

Next, as shown in FIG. 7B, after a photosensitive resist film is applied to the entire surface of the substrate, holes are formed in the source forming region 16 by photolithography, and boron ions (B ⁺ ) are accelerated by the acceleration energy. 70 keV, density 4 × 10
Rotational ion implantation is performed at ¹³ cm ⁻² and a tilt angle of 60 °.
Further, phosphorus ions (P ⁺ ) are accelerated at an energy of 40 ke.
V, ions are implanted at a density of 4 × 10 ¹³ cm ⁻² .

Next, after the photosensitive resist film 15 is peeled off, a heat treatment is performed in a nitrogen atmosphere at 900 ° C. for 30 minutes.
Activating boron and phosphorus implanted, FIG.
As shown in (a), a P ⁺ type region 13a and an N ⁻ type source region 17 are formed on the surface thereof.

Next, as shown in FIG.
The nm-thick silicon oxide film 7 and the 120-nm-thick polysilicon film are sequentially formed by, for example, a chemical vapor deposition method (hereinafter abbreviated as CVD) having good step coverage.

Next, as shown in FIG. 9 (a), by etching by anisotropic dry etching selectivity by mixed gas of the polysilicon film 8, for example Cl ₂ and HBr, the stacked gate structure Silicon oxide film 7 on side wall
A spacer 8a made of polysilicon is formed through the step.

Next, as shown in FIG. 9B, after a photosensitive resist film 9 is applied on the entire surface, a hole is formed on the drain formation region 18 by photolithography, and isotropic dry etching or wet etching is performed. Then, the polysilicon spacer 8a formed on the drain side is removed. At this time, for etching the polysilicon, SF ₆ or the like having a high etching selectivity with respect to the silicon oxide film 7 serving as a base is used.

Next, after the photosensitive resist film 9 is peeled off,
As shown in FIG. 10, arsenic ions (As ⁺ ) are implanted at an acceleration energy of 70 keV and a density of 3 × 10 ¹⁵ cm ⁻² , and then heat-treated at 900 ° C. for 30 minutes in a nitrogen atmosphere to form a source region 10 _S Then, a drain region _10D is formed.

Thus, the source region 10 _s , N ⁻
A source pocket structure in which the type source region is wrapped by the P ⁺ type region 13a can be realized.

Next, the polysilicon spacer 8a formed on the source side is removed, and as shown in FIG. 4, an interlayer insulating film 11 is formed, and the control gate electrode 6a and the source region 10a are formed.
_S, to the drain region 10 on the _D and a contact hole, forming a metal wiring _{12 CG,} 12 S, 12 _D.

According to this manufacturing method, the physical offset length L _OFF is determined by the width of the polysilicon spacer 8 a formed on the source side, that is, the thickness of the polysilicon film 8. The size and concentration of the impurity diffusion region on the source side are determined by the thickness of the polysilicon film and the ion implantation conditions and heat treatment conditions for forming the P ⁺ type region and the N ⁻ type source region in the manufacturing process. This is because, in the conventional example, the resistance value of the offset region is determined only by the offset length determined by the thickness of the polysilicon film 8, so that the degree of freedom of design is increased and the variation in characteristics can be reduced. Becomes

In order to manufacture the first embodiment, the second embodiment
The implantation of phosphorus ions in the manufacturing method of the embodiment may be omitted. It is not necessary to perform oblique ion implantation for boron ion implantation (in the first embodiment, implantation is performed from the vertical direction).

[0047]

As described above, according to the present invention, in a nonvolatile semiconductor memory device having a floating gate electrode, a drain region is provided partially adjacent to a floating gate and a source region is provided adjacent to the floating gate. An offset region is provided so as not to overlap with the electrode, and a high-concentration P ⁺ -type region is provided under the offset region. Therefore, the resistance value under the offset region can be freely set freely without increasing the offset length. This has the effect that the write voltage can be reduced. Further, the resistance under the offset region can be set by ion implantation and thermal diffusion, so that process design can be facilitated and stable production can be performed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a graph (FIG. 2A) showing a relationship between a writing time and a threshold voltage in the first embodiment (FIG. 2A) and a diagram showing a relationship between a boron implantation amount and a writing start voltage and a current (FIG. 2);
(B)).

FIG. 3 is a graph showing a potential distribution (FIG. 3A) and a graph showing a channel direction electric field intensity (FIG. 3B) in the first embodiment.

FIG. 4 is a sectional view showing a second embodiment of the present invention.

FIG. 5 is a graph showing a relationship between a phosphorus implantation amount, a read current, and a write time in a second embodiment.

FIGS. 6A and 6B are diagrams for explaining a manufacturing method according to a second embodiment;
It is a process order sectional view divided and shown to (b).

FIGS. 7A and 7B are sectional views in the order of steps shown in FIGS. 7A and 7B for explaining a step next to the step corresponding to FIG.

FIGS. 8A and 8B are sectional views in the order of steps shown in FIGS. 7A and 7B for explaining a step next to the step corresponding to FIG.

9 is a sectional view in the order of steps shown in FIGS. 9A and 9B for explaining a step next to the step corresponding to FIG. 8;

10 is a cross-sectional view for describing a step subsequent to the step corresponding to FIG.

FIG. 11 is a sectional view showing a conventional example.

FIG. 12 is a graph showing a relationship between a writing time and a threshold voltage in a conventional example.

13 is a graph showing a potential distribution in a conventional example (FIG. 1)
3 (a)) and a graph (FIG. 13 (b)) showing the electric field strength in the channel direction.

14 is a graph showing the relationship between the maximum value E _m and the offset length L _OFF of the channel direction electric field strength in the conventional example.

[Explanation of symbols]

Reference Signs List 1 P type silicon substrate 2 Field oxide film 3 First gate insulating film 4 First conductive film 4 a Floating gate conductor film 5 Second gate insulating film 6 Second conductor film 6 a Control gate electrode 7 Silicon oxide film 8 Polysilicon film 8a spacer 9 photosensitive resist film 10 _D drain region 10 _S source region 11 interlayer insulating film _{12 CG,} 12 D, 12 _S metal wiring 13, 13a P ⁺ -type region 14 N ^- -type source region 15 photosensitive resist film 16 source Forming region 17 N ^- type source region 18 Drain forming region

Claims (4)

(57) [Claims] 1. An N-type drain region and a source region selectively formed in a P-type region of a surface portion of a semiconductor substrate, and a surface of the P-type region sandwiched between the drain region and the source region. A floating gate electrode selectively covered with one gate insulating film, and a control gate electrode deposited on the surface of the floating gate electrode via a second gate insulating film, the source region and the floating gate electrode Three-terminal field-effect transistor with an offset area between
A nonvolatile semiconductor memory device comprising a transistor , wherein a P ⁺ -type region having a higher concentration than the P-type region is provided in the offset region. Wherein said P ⁺ type regions lightly doped source region coupled to the source region in a surface part of the are provided and the P ⁺
2. The nonvolatile semiconductor memory device according to claim 1, wherein the mold region has a source pocket structure. 3. A step of forming an element isolation structure on a semiconductor substrate having a P-type region on a surface portion to partition an element formation area, and covering a surface of the semiconductor substrate in the element formation area with a first gate insulating layer. Forming a film, depositing a first conductor film, and patterning the first conductor film while leaving the first conductor film near the element formation region to form a floating gate conductor film; and , A second gate insulating film is formed, a second conductive film is deposited, and then the second conductive film, the second gate insulating film and the floating gate conductive film are patterned to form a central portion of the element forming region. Forming a stacked gate structure that traverses the region, and implanting predetermined ions into a source forming region that is one of the element forming regions where the stacked gate structure is not provided to form a P ⁺ -type region And the laminated layer Method of manufacturing a nonvolatile semiconductor memory device characterized by a step of forming a source region and a drain region of said spacer is formed on the side surface of the source forming region side N-type ion implantation is performed while bets structure. 4. The method according to claim 1, wherein instead of the step of forming the P ⁺ -type formation region, N-type impurity ions are implanted into the source formation region, P-type impurity ions are introduced by a rotary ion implantation method, and heat treatment is performed. ^{4. The} method for manufacturing a nonvolatile semiconductor memory device according to claim 3, further comprising a step of forming a low-concentration source region in the ⁺ type region and a surface portion thereof.