JPH0794609A - Nonvolatile semiconductor memory element and fabrication thereof - Google Patents

Abstract

PURPOSE:To provide a floating gate nonvolatile memory in which hot electrons can be injected efficiently by generating a high field region at the end of source and low voltage (<=3V) writing is realized. CONSTITUTION:N-type source/drain regions 10S, 10D are formed on a P-type silicon substrate 1 and a first gate insulation film 3, a floating gate 4b, a second gate insulation film 5, and a control gate electrode 6a are then formed on a channel region between the source/drain regions 10S, 10D. In this regard, an offset region (LOFF) is formed such that the drain region 10D and the floating gate 4b are overlapped contiguously but the source region 10S and the floating gate 4b are not overlapped. A P<+>-type region 13 is formed in the offset region in order to cause concentration of field at the time of writing operation thus effecting generation and injection of hot electron efficiently.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device and a manufacturing method thereof, and more particularly to a non-volatile semiconductor memory device having a floating gate electrode and a manufacturing method thereof.

[0002]

2. Description of the Related Art As a writable / erasable nonvolatile memory element, a floating gate electrode is provided on a region between a source region and a drain region on a surface of a semiconductor substrate with a first gate insulating film interposed therebetween. Further, there is known a field effect transistor (EPROM) in which a control gate electrode capacitively coupled to a floating gate electrode is further formed on the control gate electrode via a second gate insulating film. In this storage element, the difference in threshold voltage due to the difference in charge storage state of the floating gate electrode is stored as data "0" and "1".

When writing information to this storage element,
The control gate electrode is set to a positive high potential to form a channel on the substrate surface, and a positive voltage is applied to the drain region. At this time, the electrons traveling in the channel receive energy due to the high electric field generated on the channel and are injected into the floating gate electrode beyond the potential barrier of the first gate insulating film. In this writing operation in which the state in which electrons are injected into the floating gate electrode is set as the writing state, it is extremely important to reduce the writing voltage. For example, in the market of flash memories that electrically write and electrically erase all bits collectively, the current 1
There is a strong demand for the transition from the 2V / 5V dual power source to the 5V single power source or the 3V single power source, but for that purpose, it is necessary to lower the voltage in the write operation.

Conventionally, a floating gate field effect transistor having an offset region between a source region and a portion directly under a gate electrode has been proposed as a semiconductor memory element for realizing such low voltage writing. About this element, IDM Technical Digest magazine (IEDM Technical Digest),
Pp. 584-587, 1986, IEEE Electronic Device Letters (IEEE)
Electron Device Letters),
EDL-7, 540-542, IEDM Technical Digest (IEDM T
technical Digest), pp. 315-third
P. 18, 1991, IEEE Electron Devices Letters (IEEE Electron
Device Letters), Volume 13, 46
5th page-467th page, introduced in 1992, etc.
Injection (Source-Side Inje)
This is referred to as the action EPROM)).

FIG. 11 is a sectional view showing the structure of a SIEPROM. Drain region 10 through the P-type silicon substrate 1 of the drain region 10 _D and a source region 10 _S and the surface of the floating gate electrode 4b of the portion sandwiched between in the first gate insulating film 3
_Is formed at a position overlapping _D and having an offset region (L _OFF ) with respect to the source region 10 _S ,
A control gate electrode 6a is formed on the floating gate electrode 4b via a second gate insulating film 5. In this element, since the offset region (L _OFF ) has high resistance, strong electric field concentration occurs in the channel portion on the source side even if the voltage applied to the control gate electrode 6a and the drain region 10 _D is relatively low. Hot electrons having energy obtained by the high electric field can be injected into the floating gate electrode 4b.
Note that erasing is performed by emitting electrons from the floating gate electrode by an FN tunnel current.

A prototype of this SEEPROM was manufactured and the relationship between the programming time and the threshold voltage (writing characteristics) was measured.

A film thickness of 10 nm is formed on the surface of the P-type silicon substrate 1.
First gate insulating film 3 made of a silicon oxynitride film, a floating gate electrode 4b having a film thickness of 150 nm, a second gate insulating film 5 made of a silicon oxide film having a film thickness of 20 nm, a film thickness of 200 n
After forming the control gate electrode 6a of m, the source region 1
After arsenic is implanted into the drain region 10 _D at 0 _{S at} an acceleration voltage of 70 keV and an implantation density of 3 × 10 ¹⁵ cm ⁻² , 900 ° C.
It was formed by thermal diffusion for 30 minutes. This ion implantation is performed by providing an ion implantation mask having an offset length L _OFF between the drain side in a self-aligned manner with the gate electrode and the source side between the gate electrode and the source.
An M structure was formed.

FIG. 12 shows a gate length of 0.
6 is a graph showing measured values of write characteristics of a SIEPROM having a gate width of 6 μm and a gate width of 0.8 μm. Offset length L
_The writing speed increases with the increase of _OFF .

Next, the result of the SIE PROM analysis by the two-dimensional device simulator will be described.

[0010] Figure 13 (a), (b), each gate length 0.5 [mu] _m, for SIEPROM of L OFF = 0.2 [mu] m, and the channel direction electric field strength _{E X} in potential φ and the channel surface in a write operation initial calculated respectively The result. As the voltage of the write operation, the potential _{V CG} is 12V of the control gate electrode, the drain voltage _{V D} is 3
V, the source voltage _{V S} is 0V, the substrate voltage _{V B} is 0V. The potential V _FG of the floating gate electrode at the beginning of the writing operation is 6.6V. Now, as shown in FIG. 13 (b), the channel direction electric field strength E _X has a sharp peak E _m at the end of the source side. Similarly, SIEP of L _OFF = 0 to 0.2 μm obtained by a two-dimensional device simulator
The value of _{E m} for ROM shown in FIG. 14. As is clear here, in the SIEPROM, the electric field on the channel generated during the write operation is determined by the offset length L _OFF , and the maximum electric field strength E _m on the channel increases as L _OFF increases.

According to the Lucky Electron model, for example, IE Transaction on Electron Devices (IEEE Tr)
action on Electron Dev
ices) Volume ED-31, pages 1116- 1125
P., 1982),

I _g = I _d ∫ exp (−φ _b / qEmλ) P (Eox) dx ≈CI _d exp (−φ _b / qEmλ)

It is expressed as follows.

Where I _d is the drain current during the write operation, φ _b is the potential barrier between the silicon-silicon oxide film, λ is the electron scattering mean free process, and P (E _OX ) is the silicon-silicon oxide film interface. The probability that the electrons injected into the silicon oxide film at the time of flowing into the silicon oxide film, C
Is a constant. According to the above equation, in order to increase the gate current I _g at the time of writing it is effective increase in E _m. Given the calculation results shown in FIG. _14, to increase the _{L OFF,} by increasing the _{E m,} it is possible to improve the writing speed of SIEPROM. This agrees with the measurement result shown in FIG.

[0015]

As described above,
The electric field on the channel during the write operation in this SEEPROM is determined by the physical offset length. To reduce the write voltage, the offset length L _OFF
Should be long and the electric field strength on the channel should be large. However, increasing the offset length L _OFF reduces the read current of the device and increases the device area,
This becomes an obstacle in designing a fine element capable of high-speed reading. Further, in order to suppress variations in element performance, it is required to precisely control the offset length L _OFF .
If the manufacturing process technology is the same, the yield will be lower than that of a normal EPROM without an offset forming step.

[0016]

A nonvolatile semiconductor memory device according to the present invention includes an N-type drain region and a source region selectively formed in a P-type region on a surface portion of a semiconductor substrate, the drain region and the source, respectively. The P sandwiched by the area
A floating gate electrode selectively covering the surface of the mold region via a first gate insulating film, and a control gate electrode deposited on the floating gate electrode surface via a second gate insulating film, In a nonvolatile semiconductor memory device in which an offset region is provided between a region and a portion immediately below the floating gate electrode, a P ⁺ -type region having a higher concentration than the P-type region is provided in the offset region. is there.

Further, the method for manufacturing a nonvolatile semiconductor memory device according to the present invention comprises a step of forming an element isolation structure on a semiconductor substrate having a P-type region on its surface to partition the element formation region, and the element formation region. Forming a first gate insulating film to cover the surface of the semiconductor substrate, depositing a first conductor film, and patterning by leaving the first conductor film on and in the vicinity of the element forming region to form a floating gate conductor. A step of forming a film,
A second gate insulating film is formed by covering the floating gate conductor film, the second conductor film is deposited, and then the second conductor film;
Patterning the second gate insulating film and the floating gate conductor film to form a stacked gate structure crossing the central portion of the device forming region; and forming the stacked gate structure in the device forming region where the stacked gate structure is not provided. On the other hand, a step of implanting predetermined ions into a certain source formation region to form a P ⁺ -type region, and a spacer is formed on a side surface of the stacked gate structure on the side of the source formation region to perform ion implantation to perform N-type source. A region and a drain region are formed.

[0018]

According to the above-mentioned means, even if the offset length is constant, the resistance value of the offset region can be set by the impurity concentration of the P ⁺ type region. Compared to the case where it was set, it can be performed more widely and freely. As a result, a larger maximum value E _m of the electric field strength in the channel direction can be obtained during the writing operation, and the writing speed can be increased.
That is, the write voltage can be lowered without increasing the offset length.

Further, in the manufacturing process, in the prior art, the writing characteristic was determined by the offset length determined by film formation and dry etching, but according to the above-described means, P ⁺ determined by ion implantation and thermal diffusion. Offset length can be selected according to the impurity concentration of the mold region,
The degree of freedom in process design is increased, and it is possible to manufacture devices having uniform writing characteristics.

[0020]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention.

In this embodiment, the boron concentration is 2 × 10 ¹⁵ c
m ⁻³ P-type silicon substrate 1 (or a P ⁻ -type silicon substrate having a P well formed therein, in which case P
The N-type drain region 10 _D and the source region 10 _S selectively formed on the surface of the well having a concentration of 2 × 10 ¹⁵ cm ⁻³ ), the drain region 10 _D and the source region 10 _S A floating gate electrode 4b for selectively covering the surface of the sandwiched P-type silicon substrate region with a first gate insulating film 3 (a silicon oxide film having a thickness of 10 nm) and a second gate insulating film on the surface of the floating gate electrode 4b. 5 (20n thick
control gate electrode 6a deposited via a silicon oxide film of m), the source region 10S and the floating gate electrode 4
Offset area (offset length L
_In the non-volatile semiconductor memory device provided with ( _OFF ), the P ⁺ type region 13 having a higher concentration than the P type silicon substrate 1 is provided in the above-mentioned offset region.

For example, L _OFF = 0.1 μm to 0.
13 μm, acceleration voltage of source / drain region 70 ke
After arsenic is ion-implanted at V with an implantation density of 3 × 10 ¹⁵ cm ⁻² , thermal diffusion is performed at 900 ° C. for 30 minutes to form a P ⁺ -type region with an acceleration voltage of 70 keV and an implantation density of 4 × 10 ¹³ cm.
After the boron was injected at ⁻² , the film was formed by thermal diffusion at 900 ° C. for 30 minutes.

FIG. 2A shows a SIEPRO according to this embodiment.
7 is a graph showing the write characteristics of M. Gate length 0.6
μC, gate width 0.8 μm, L _OFF = 0.13 μm, V _CG = 12 V, V _D = 3 V, V _S = V _B = 0
Threshold voltage V when writing is performed under the condition of V
The measured value of the change in _TM is shown.

FIG. 2 (b) is a diagram showing the relationship between the boron implantation amount, the write voltage V _DW and the write current I _DW of this SIEPROM. Where V _DW and I
_DW is the minimum drain voltage and current required to inject hot electrons into the floating gate electrode by the write start voltage and current.

It can be seen that the writing efficiency improves as the amount of boron (B) injected increases. Alternatively, a smaller offset length will suffice for the same writing efficiency.

3A and 3B show the SIEP of this embodiment.
Is a graph showing the simulation result of the distribution and the channel direction electric field strength E _X potential φ in the write operation early ROM. E _X is the value of the channel surface (at a depth 1.10μm in FIG. 3 (a)), the gate length 0.5
μm, L _OFF = 0.1 μm, and the voltage during the write operation is 12 V for the potential V _CG of the control gate electrode, 3 V for the drain voltage V _D , 0 V for the source voltage V _S , and 0 V for the substrate voltage V _B.

[0028] As is apparent from FIG. 3 (b), the channel direction electric field strength E _X on the channel, with a sharp peak E _m at the end of the source side. This peak intensity E _m is shown in FIG.
Conventional SIE of L _OFF = 0.2 μm shown in (b)
It is about the same as in the case of PROM. That is, a small offset length L _OFF, it is possible to obtain a large channel direction maximum field strength E _m.

Next, a second embodiment of the present invention will be described.

FIG. 4 is a sectional view of a semiconductor chip showing a second embodiment.

In this embodiment, an N ⁻ type source region 14 is provided on the surface of the P ⁺ type region 13a so as to be connected to the source region 10s. Others are the same as those in the first embodiment. The formation conditions of the P ⁺ type region 13a are the same as those in the first embodiment, and N ⁻
The mold source region has an acceleration voltage of 40 keV and an implantation density of 4 × 10.
It is formed by injecting phosphorus at ¹³ cm ⁻² and then performing thermal diffusion at 400 ° C. for 30 minutes.

FIG. 5 shows impurities (phosphorus) in the N ^-- type source region.
7 is a graph showing the relationship between the ion implantation concentration and the read current and write time. Here, the read current is V
The drain current value (I _DS ) when _CG = 12 V, V _D = 1 V, V _S = V _B = 0 V, and the writing time is V _CG =
This is the time required for the threshold voltage to change from 1 V to 6 V when writing is performed with 12 V, V _D = 3 V, V _S = V _B = 0 V. It can be seen that by increasing the impurity concentration in the N ⁻ type source region, the read current can be increased without significantly reducing the writing speed. This is extremely important for high speed reading of cells. Thus, increasing the read current at the same time, can be kept large although the writing speed inferior first embodiment, although the resistance value of the offset region becomes smaller N ^- type source region and the P ⁺ for -type region is steep impurity profile in per (a point in FIG. 4) intersecting, Note, Do Oki when writing E _m
Because you can get

Next, the manufacturing method of the second embodiment will be described.

First, as shown in FIG. 6A, a P-type silicon substrate 1 having an impurity concentration of 2 × 10 ¹⁵ cm ⁻³ (or a P ⁻ -type silicon substrate on which a P well is formed) may be prepared. A trench or a field oxide film 2 is formed as an element isolation structure to partition an element formation region, and a first gate insulating film 1 and a first conductor film 4 are sequentially grown on the element formation region. For example, the first gate insulating film 1 has a thickness of 10n.
As the silicon oxynitride film of m and the first conductor film 4, a polysilicon film having a thickness of 150 nm doped with impurities can be used.

Next, as shown in FIG. 6B, after patterning the first conductor film 4 to form the floating gate conductor film 4a covering the element formation region and its vicinity, the second gate insulating film 5 is formed. And then the second conductor film 6 is grown. Here, the second gate insulating film 5 has, for example, a thickness of 20.
nm ONO three-layer film (silicon oxide film / silicon nitride film / silicon oxide film) is used, and as the second conductor film 6,
A tungsten polycide film (tungsten silicide film / polysilicon film) having a thickness of 200 nm can be used.

Next, as shown in FIG. 7A, the second conductor film 6, the second gate insulating film 5, and the floating gate conductor film 4a.
Is sequentially patterned by anisotropic dry etching to form a laminated gate structure including the floating gate electrode 4b, the second gate insulating film 5 and the control gate electrode 6a. This stacked gate structure generally crosses the central portion of the element formation region, and the control gate electrode is usually processed to be connected to the control gate electrode wiring.

Next, as shown in FIG. 7B, a photosensitive resist film is applied to the entire surface of the substrate, and then a hole is formed on the source forming region 16 by photolithography, and boron ions (B ⁺ ) are accelerated with energy. 70 keV, density 4 × 10
Rotational ion implantation is performed at ¹³ cm ⁻² and an inclination angle of 60 °.
Further, phosphorus ions (P ⁺ ) are accelerated with energy of 40 ke.
Ion implantation is performed at V and a density of 4 × 10 ¹³ cm ⁻² .

Next, after peeling off the photosensitive resist film 15, a heat treatment is carried out at 900 ° C. for 30 minutes in a nitrogen atmosphere,
Activated ion-implanted boron and phosphorus, and FIG.
As shown in (a), an N ⁻ type source region 17 is formed on the P ⁺ type region 13a and its surface portion.

Next, as shown in FIG. 8B, the thickness 50
nm silicon oxide film 7 and a polysilicon film having a thickness of 120 nm are sequentially formed by, for example, a chemical vapor deposition method (hereinafter abbreviated as CVD) having good step coverage.

Next, as shown in FIG. 9A, the polysilicon film 8 is etched by selective anisotropic dry etching using, for example, a mixed gas of Cl ₂ and HBr to form a stacked gate structure. Silicon oxide film 7 on the side wall
A spacer 8a made of polysilicon is formed through.

Next, as shown in FIG. 9B, after a photosensitive resist film 9 is applied on the entire surface, a hole is formed on the drain formation region 18 by photolithography, and isotropic dry etching or wet etching is performed. The polysilicon spacer 8a formed on the drain side is removed. At this time, for etching the polysilicon, SF ₆ or the like having a high etching selection ratio with respect to the underlying silicon oxide film 7 is used.

Next, after peeling off the photosensitive resist film 9,
As shown in FIG. 10, arsenic ions (As ⁺ ) are ion-implanted at an acceleration energy of 70 keV and a density of 3 × 10 ¹⁵ cm ⁻² , and then heat treatment is performed in a nitrogen atmosphere at 900 ° C. for 30 minutes to form the source region 10 _S. , The drain region 10 _D is formed.

In this way, the source regions 10 _S , N ⁻
A source pocket structure in which the mold source region is wrapped with the P ⁺ type region 17 can be realized.

Next, the polysilicon spacer 8a formed on the source side is removed, an interlayer insulating film 11 is formed as shown in FIG. 4, and the control gate electrode 6a and the source region 10 are formed.
_S, to the drain region 10 on the _D and a contact hole, forming a metal wiring _{12 CG,} 12 S, 12 _D.

According to this manufacturing method, the physical offset length L _OFF is determined by the width of the polysilicon spacer 8a formed on the source side, that is, the film thickness of the polysilicon film 8. The size and concentration of the impurity diffusion region on the source side are determined by the film thickness of the polysilicon film and the ion implantation conditions and heat treatment conditions for forming the P ⁺ type region and the N ⁻ type source region in the manufacturing process. This is because in the conventional example, the resistance value of the offset region is determined only by the offset length determined by the film thickness of the polysilicon film 8, so that the degree of freedom in design is increased and variation in characteristics can be reduced. Becomes

In order to manufacture the first embodiment, the second
The phosphorus ion implantation in the manufacturing method according to the embodiment may be omitted. Further, it is not necessary to perform oblique ion implantation for boron ion implantation (the first embodiment is based on vertical implantation).

[0047]

As described above, according to the present invention, in the nonvolatile semiconductor memory element having the floating gate electrode, the drain region is provided adjacent to the floating gate so as to partially overlap with the floating gate, and the source region is the floating gate. Since the offset region is provided so as not to overlap the electrode and the high-concentration P ⁺ type region is provided under the offset region, the resistance value under the offset region can be widely set freely without increasing the offset length. Moreover, it has an effect that the write voltage can be lowered. Further, the resistance under the offset region can be set by ion implantation and thermal diffusion, so that the process design can be facilitated and stable manufacturing can be performed.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a graph showing the relationship between the write time and the threshold voltage of the first embodiment (FIG. 2A) and the relationship between the boron implantation amount and the write start voltage and the current (FIG. 2).
(B)).

FIG. 3 is a graph showing a potential distribution (FIG. 3A) and a graph showing electric field strength in a channel direction (FIG. 3B) in the first embodiment.

FIG. 4 is a sectional view showing a second embodiment of the present invention.

FIG. 5 is a graph showing a relationship between a phosphorus injection amount and a read current and a write time in the second embodiment.

FIG. 6 (a) for explaining the manufacturing method of the second embodiment,
It is a process order sectional view divided and shown in (b).

7A and 7B are cross-sectional views in order of the processes, which are illustrated by dividing into FIGS.

8A to 8C are cross-sectional views in order of the processes, which are illustrated by dividing them into FIGS.

9A and 9B are sectional views in order of the processes, which are illustrated by dividing into FIGS. 8A and 8B for explaining the process subsequent to the process corresponding to FIG.

FIG. 10 is a cross-sectional view for explaining a next process of the process corresponding to FIG.

FIG. 11 is a cross-sectional view showing a conventional example.

FIG. 12 is a graph showing the relationship between the write time and the threshold voltage in the conventional example.

FIG. 13 is a graph showing a potential distribution in a conventional example (see FIG.
3 (a)) and a graph showing electric field strength in the channel direction (FIG. 13 (b)).

FIG. 14 is a graph showing the relationship between the maximum value E _{m of the} electric field strength in the channel direction and the offset length L _OFF in the conventional example.

[Explanation of symbols]

1 P-type silicon substrate 2 Field oxide film 3 First gate insulating film 4 First conductive film 4a Floating gate conductor film 5 Second gate insulating film 6 Second conductor film 6a Control gate electrode 7 Silicon oxide film 8 Polysilicon Film 8a Spacer 9 Photosensitive resist film 10 _D Drain region 10 _S Source region 11 Interlayer insulating film 12 _CG , 12 _D , 12 _S Metal wiring 13, 13a P ⁺ type region 14 N ⁻ type source region 15 Photosensitive resist film 16 Source Formation region 17 N ⁻ type source region 18 Drain formation region

Claims (4)

[Claims] 1. An N-type drain region and a source region selectively formed in a P-type region of a semiconductor substrate surface portion, and a surface of the P-type region sandwiched between the drain region and the source region, respectively. 1 a floating gate electrode selectively covering via a gate insulating film and a control gate electrode deposited on the surface of the floating gate electrode via a second gate insulating film, the source region and the floating gate electrode In a nonvolatile semiconductor memory device having an offset region provided directly below it, a P ⁺ -type region having a higher concentration than the P-type region is provided in the offset region. . Wherein said P ⁺ type regions lightly doped source region coupled to the source region in a surface part of the are provided and the P ⁺
The nonvolatile semiconductor memory device according to claim 1, wherein the mold region has a source pocket structure. 3. A step of forming an element isolation structure on a semiconductor substrate having a P-type region on its surface to partition the element formation region, and covering the surface of the semiconductor substrate of the element formation region with a first gate insulation. Forming a film, depositing a first conductor film, and patterning the first conductor film leaving the first conductor film in the vicinity of the element formation region to form a conductor film for a floating gate; and the conductor film for a floating gate. To form a second gate insulating film, deposit the second conductor film, and then pattern the second conductor film, the second gate insulating film, and the floating gate conductor film to form a central portion of the element forming region. Forming a P ⁺ -type region by implanting predetermined ions into a source formation region, which is one of the element formation regions where the laminated gate structure is not provided, and forming a P ⁺ -type region. And the laminated Method of manufacturing a nonvolatile semiconductor memory device characterized by a step of forming a source region and a drain region of said spacer is formed on the side surface of the source forming region side N-type ion implantation is performed while bets structure. 4. Instead of the step of forming the P ⁺ -type formation region, N-type impurity ions are implanted into the source formation region, P-type impurity ions are introduced by a rotary ion implantation method, and heat treatment is performed to form the P-type formation region. ^{4. The} method for manufacturing a nonvolatile semiconductor memory element according to claim 3, further comprising the step of forming a low concentration source region on the ⁺ type region and a surface portion thereof.