TWI222702B - Method of fabricating contact structures on a semiconductor chip - Google Patents

Abstract

A method of fabricating contact structures on a semiconductor chip is provided. A dielectric layer is filled into the inter-gate spacing of two gates. The dielectric layer is polished to have a surface coplanar with the gates. A second mask layer is deposited. Then the second mask layer is etched to form a bit line opening in a array area, a gate opening, and a substrate opening in a periphery area. A portion of the dielectric layer is removed through the bit line opening and the substrate opening to form a bit line contact and a substrate contact. A metal layer is filled into the bit line contact and the substrate contact. The first mask layer is etched through the gate opening to form a gate contact.

Description

1222702 V. Description of the invention (l) Technical field of the invention The present invention provides a method for making contact holes on a semiconductor wafer, especially an array of wafers (& 1 ^ 8ā) that can be simultaneously used on a wafer using a single photomask. Area and surrounding (1 ^]: ^ 1) | 161 ^) area to make character contact holes (1 ^ 1: 'line contact (CB), substrate contact holes (CS), and gate contact holes (gate contact, cg). Prior art

Dynamic random access memory (DRAM) is a key component indispensable in many electronic products. DRAM has a large number of memory cells (memory cel 1) gathered into an array area for storing data, and another peripheral area for peripheral control "circuits (or read-write circuits). Regardless of the array area Or peripheral area, each memory cell and control circuit is composed of at least one metal, oxide semiconductor (me ta 1 ox i de s em i conduc t or, M0S) transistor, and other electronics such as capacitors (capac it or) The components are connected in series-and each M0S transistor and capacitor are electrically connected with several word lines and bit lines to determine the address of each memory cell. Its The electrical connection method is to make contact holes between different material layers in the manufacturing process of the M0S 电 晶 # body, and fill conductive materials in them to enable the M0S to actually operate.

Page 5 1222702 V. Description of the Invention (2) Please refer to FIGS. 1 to 3, which are schematic diagrams of a method for making a contact hole on a semiconductor wafer 10, which is conventionally known. As shown in FIG. 1, the semiconductor wafer 10 includes a substrate 12 on which an array region 14 and a peripheral region 16 are defined. The array area 14 is used to set all the memory cells of the DRAM, and there are gates 18 and 20 therein, and the peripheral area 16 is used to set the peripheral control circuit of DR A M, which includes a gate 22. The gate electrodes 18, 20, and 22 each include an oxide layer (not shown) and a conductive layer

24. A silicide layer 26, a mask layer 28, and a spacer 30. When making a contact hole, a dielectric layer 32 is deposited on the gate electrodes 18, 20, and 22, so that the dielectric layer 32 covers the gate electrode 18,

On 20 and 22, a doped polycrystalline silicon layer 34 is then deposited as a hard mask for the subsequent etching process. Then, as shown in FIG. 2, a photoresist layer (not shown) is deposited on the doped polycrystalline silicon layer 34, and a first photomask CT ′ is used for the lithography process and the money engraving process to remove a part of the doped polycrystalline silicon layer 3. 4 and the dielectric layer 3 2, a one-bit line contact hole (c ο ntacth ο 1 e) 3 6 ′ is formed in the array area 14 at the same time, a gate opening (〇pening) 3 8 and a Base contact hole 40. Next, as shown in FIG. 3, a second photomask CK is used to perform a photolithography and etching process to remove the mask layer 28 exposed on the gate 22 through the gate opening 38 to form a gate contact. Hole 4 2. After that, an adhesive layer (g 1 ue 1 ayer, not shown) and a metal layer (not shown) are sequentially deposited, and an etchback process is performed to make the bit line contact the hole 3 6, the gate The pole contact holes 38 and the base contact holes 40 are filled with a conductive metal layer, so that these contact holes can be used in subsequent fabrication.

Page 6 1222702 V. Description of the invention (3) The components or wires on it are electrically connected. For line contact, it must also be time-consuming and hard masking. Because the dopant and the gate are large, the defective unit product material does not affect the product. 36. Use two-plus lithography. In addition, a photoresist layer is formed on the side wall of the heteropolycrystal. In addition, the concentration is easier to complete the completion of the photomask CT process in the peripheral area of the yield. Because the inter-subspaces on which the silicon layer 34 is deposited remain in the gate, the contact is filled in the contact, but the array is made in the conventional method. The location element contact hole 4 2 and the substrate contact hole 4 o t CK require more than two mask costs f and time, which complicates the entire fabrication process and uses a doped polycrystalline silicon layer 34 as the resist layer. When performing mask pattern transfer, the light reflection properties are also strong, and the aspect ratio of the contact hole (that is, the aspect ratio) is higher than that in the gap between the extreme side walls. Improving memory, as a result, will cause subsequent holes' causing holes (v 0 id), seriously affecting the content of the invention

Therefore, the main object of the present invention is to provide a method for forming a character contact hole, a substrate contact hole, and a gate contact hole in an array area and a peripheral area at the same time using a single photomask CT with a small aspect ratio. To solve the above-mentioned conventional method for making a contact hole: following the scope of the patent application according to the present invention, a method for making a contact hole on a semiconductor wafer is disclosed. The semiconductor wafer includes a substrate

Page 71222702 V. Description of the invention (4) The bottom is defined on its surface to be used to produce a d R μ peripheral control array. The area η contains at least the "gate-gate circuit". Array two gates' π j are provided on each of these gates. The method package :: = Inter-gate spacing is filled with _entering sound '乂 = Inter-pole 2f1Shing) The dielectric layer stops on the surface of the n layer of the first mask and the surface of the gates approximately Leveling, then depositing a ^ mask layer, etching a bit line opening in the second mask layer in the array area, and etching a gate in the second mask layer in the peripheral area Two pole openings and a substrate opening, the dielectric layer is etched through the bit line opening and the substrate opening until an exposed portion of the substrate is formed, thereby forming a bit line contact hole and a substrate contact hole, and then The word line contact hole and the base contact hole are filled with a metal layer, and finally the first mask layer is etched through the gate opening to form a gate contact hole of the second gate.

Because the present invention only uses a single photomask and one lithography process, the pattern of bit line contact holes, gate contact holes, and substrate contact holes can be defined at the same time, so the cost required for the entire process can be greatly reduced, including the photomask. Cost, time and materials used for the second lithography and etching process. On the other hand, the height and width produced by the method for making a contact hole according to the present invention are relatively small, which can effectively avoid the occurrence of voids and improve the product yield. In order to make your inspection committee better understand the characteristics of the present invention

Page 8 1222702

V. Description of the invention (5) and technical content, please refer to the following detailed drawings of the present invention. However, the drawings are for reference and auxiliary explanation only. ^ Old description and attached invention are limited. It is not used to implement the embodiment.

Please refer to FIGS. 4 to 9. FIGS. 1 to 9 are schematic diagrams of a method for making a contact hole on a semiconductor wafer 50.豕 Not invented in the first embodiment, the semiconductor wafer 50 includes a substrate 52, its surface 1 = the listed area 54 and a peripheral area 56, where the array areas 5, 4 are all memory cells of the ^: = array DRAM, The peripheral area 56 is used as a peripheral control circuit. The surface of the substrate 52 includes -oxygen), a conductive layer 58, a metal oxide layer 60, and a first ^ 62, wherein the oxide layer is made of silicon dioxide ("11 (: 〇11 (11 〇Heart, said S i 0 2) constitutes the 'conductive layer as the gate oxide layer or ion implantation process' conductive layer ^ 8 is made of doped polycrystalline silicon (doped p0 1 ysii ± coon) material The composition of the mask layer 62 can be composed of nitrided nitride (SiN), carbide (SiC) or oxynitride (SiON). Regarding the oxide layer, conductive layer 5 8, metal The manufacturing methods of the stone oxidant layer 60 and the first masking layer 62 are well known to those skilled in the art, so they will not be repeated here.

First, as shown in Figure 5, before making the contact holes, first make the gates of each memory cell in the array area 54 and the gates of the peripheral control circuit in the peripheral area 56. The method is as follows: Touch engraving

Page 91222702 V. Description of the invention (6), remove part of the first mask layer 6 2, metal silicide layer 60 and conductive layer 58 to form a structure of two gates 64 and 66 in the array region 54 at the same time And a gate electrode 68 is formed in the peripheral region 56. Next, a silicon nitride compound is deposited on the surface of the semiconductor wafer 50, and an anisotropic etching (an i sot rop ice tch i ng) process is used to etch back some of the ammonium sulphide compounds to the gate 6 respectively. The side walls around 4, 6, 6, and 6 8 form side walls 70. Then an ion implantation process (丨 on 丨 mp 1 anf at 丨 on) and a thermal tempering process are performed to form a source and a drain (not shown) on both sides of the gate electrodes 6, 4, 6, 6, and 3 to complete the process. Fabrication of gates 64, 66, 68. As shown in FIG. 6, a Borophos-phosilicate glass (BPSG) layer is then deposited on the surface of the semiconductor wafer 50, and the BPSG layer is chemically and mechanically polished, and stopped at the first mask layer 62, so that The surface of the BPSG layer and the surfaces of the gate electrodes 64, 66, and 68 are approximately flat, and the BPSG layer is used as an inter-layer dielectric layer (inter layer dielectric layer, ilD layer) 72 between gates (inter-gat: espacing). In another embodiment of the present invention, the interlayer dielectric layer 72 may also be composed of silicon dioxide. As shown in FIG. 7, a silicon nitride layer is then deposited on the taste surface of the semiconductor wafer as the second mask layer 74. The thickness of the second mask layer 74 may be greater than or approximately equal to that of the first mask layer 62. Thickness, and a photoresist layer (not shown) is deposited thereon, and a photoresist CT is used to perform a yellow light process to transfer the pattern of the bit π line contact hole, the substrate contact hole, and the gate contact hole to

1222702 The first display of the invention, description of the invention (7) Photoresistor ja μ $ it Second cover! Reuse the rice carving process to remove the uncovered photoresist layer) ,,,, and layer 74 ′ form an array 54 in the array area 54 The bit line opening (not shown), a base opening (not shown) is formed in the peripheral area 56, and a gate eight is passed through the bit line opening and the base opening remaining layer Erzhi 72 'Until the exposed part of the substrate, thereby forming a bit L also touch' with 78 and a substrate contact hole 80. This makes the second mask layer silicon. It can be replaced by other non-conductive materials, such as silicon carbide or nitrogen Oxidation

— As shown in FIG. 8, an adhesive layer (not shown) is then deposited in sequence, and a metal layer 82, such as metal tungsten, is used to fill the gold extension layer 82 into the bit line contact 178 and a base contact hole 80. A metal-mechanical polishing process or a back-etching process is performed to remove the metal layer 8 2 and the adhesive layer on the second mask layer 74. Then use the second mask layer 74 as a hard mask or an etching mask to etch the first mask layer 62 to remove the first mask layer 62 that is not covered by the second mask layer 74 to complete the gate electrode. Making of contact holes 8 4 Among them, the adhesive layer is used to promote the adhesion of the gold lip layer 82, and is composed of a titanium nitride layer and a titanium metal layer (TiN / Ti). It is worth noting that when the first mask layer 62 and the second mask layer 74 are made of the same material, the first mask layer 62 and the second mask layer 74 will be removed at this moment. However, the purpose of this #engraving process is to remove the first mask layer 62 whose surface of the gate electrode 68 is not covered by the second mask layer 74, so when the thickness of the second mask layer 74 is greater than or equal to the first mask layer This can be achieved when the mask layer 62 is used. Although the second mask layer 74 will also be removed during the etching, it will not hurt the pole.

1222702 Five 64 Invention Description (8), 66 The first mask layer 62 on the surface. In another example, the first mask layer 62 and the second mask chip ^ ^ 夂 In another embodiment, in this etching process, it is possible to: The first covering ratio of 74, the selection ratio of f liquid, removes the covering layer 74. The first-masking layer 62 leaves a second covering as shown in FIG. Grinding and breast-feeding 'layer 2 shows 2 engraving J processes, and defines a bit line on the oxide layer 暨 lithography and ί; Γ makes the metal layer material fill the bit line pattern ΐ ΐ μ metal layer Etching or chemical mechanical polishing is stopped, and the layer is stopped to complete the production of bit lines 86. Compared with the conventional technology, the present invention is fabricated on a semiconductor wafer. = Using a single photomask CT It is possible to define patterns of contact holes such as substrates and lines in the manufacturing process, which can not only reduce the cost, but also save process time and material costs. In addition, the contact holes produced by the method of the invention have a smaller height. Aspect ratio, energy ratio = knowing that the photoresist layer remains in the contact hole in the technology, and the subsequent process In further problems such as voids, i IF iron to make only the preferred embodiment of the present invention, where the application under this invention facilitate% insult range of modifications and alterations made, also belong to the present invention patent

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Claims (1)

1222702 A method for making a contact hole on a semiconductor wafer. The semiconductor wafer includes a substrate, and an array area is defined on the surface of the semiconductor wafer. The method is used to make a dynamic random access mem 〇ry, DRAM ^ all binary, the array area contains at least a first gate; ^ hidden early a peripheral area 'for the peripheral control circuit of the dynamic random memory, the peripheral area Contains at least-笛 _ $ 兄 极 ； Wherein, a first mask layer is provided on the first and the second gate, and a sidewall is provided on the sidewall of the first and the second gate. The method includes: The following steps ... A dielectric layer, chemical mechanical polishing (P 01 ishing) is filled in the inter-gate spacing, and θθ) is coated on the mask layer to make the dielectric The surface of the electrical layer is approximately flat with the first and the first gate-gate surfaces; a second shield layer is deposited, and etched out in the second mask layer in the array area is jjZ * ( bit 1 ine) opening, and at the same time, a gate opening and a base opening are engraved in the cover of the surrounding area ~ Yongdi Erqin. The dielectric layer is etched through the bit line opening and the substrate opening until an exposed portion of the Lo substrate is refined to form a bit line contact: the same and a substrate contact hole ^ ^ ^ ^ ^ ^ / for the character A line contact hole and the base contact hole filling-metal layer; and 1222702 6. Scope of patent application The first mask layer is etched through the gate opening. 2. The method according to item 1 of the patent application, wherein the first and second gates each include a conductive layer and a metal oxide (s i 1 i c i d e) layer. 3. The method according to item 2 of the scope of patent application, wherein the conductive layer is composed of doped polysilicon. 4. The method according to item 2 of the scope of patent application, wherein a gate oxide layer is provided below the first and second gates. 5. The method as described in item 4 of the scope of patent application, wherein the gate oxide layer is composed of stone dioxide (s i 1 i c ο n d i ο X i d e, S i 0 2). 6. The method according to item 1 of the scope of patent application, wherein an adhesive layer (g 1 ue 1 ay er) is formed before filling the metal layer. 7. The method according to item 6 of the scope of the patent application, wherein the adhesive layer is composed of a TiN, TiN and Ti metal layer. 8. The method according to item 1 of the scope of patent application, wherein the first and second masking layers are oxidized by silicon nitride (S i N), silicon carbide (S i C) or nitrogen Page 16 1222702 6. Scope of Patent Application Shi Xi (Si 0N). 9. The method as described in item 1 of the scope of the patent application, wherein the dielectric layer is composed of stone dioxide. 10. The method as described in item 1 of the scope of the patent application, wherein the dielectric layer is composed of Borophos-phosilicate glass (BPSG). 11. The method according to item 1 of the scope of patent application, wherein the thickness of the second mask layer is greater than or approximately equal to the thickness of the first mask layer. 12. —A method for making a contact hole on a semiconductor wafer, the semiconductor wafer including a substrate, the surface of which is defined by: an array area, used to make all memory cells of a dynamic random access memory; and a periphery Area for making peripheral control circuits of the dynamic random access memory; the surface of the substrate includes an oxide layer, a conductive layer, a metal oxide layer, and a first mask layer. The manufacturing method includes the following steps: : Removing part of the first mask layer, the metal silicide layer, and the conductive layer, so that at least one first gate electrode is formed in the array region, and at least one second gate electrode is formed in the peripheral region; Page 17 1222702 6. The scope of the patent application is the first and the first and the second gate and a drai η; a layer of 1 ayer (ILD) is filled between the gates; the interlayer is ground The surface of the dielectric layer mask layer is approximately flat; the side walls of the two gates respectively form a side wall; a source (s urce: inter dielectric) is formed on both sides of the poles, so that the surface of the interlayer dielectric layer and the The first sink is approximately equal to the mouth, the same mouth, and the layer is in contact with the layer; a second mask layer is deposited on the gate, and the thickness of the second mask layer is greater than or equal to the thickness; defined in the two mask layers A bit line is opened in the second mask layer, and a gate is defined to open the first mask layer in the first time in a base area of the peripheral area; the bit line is opened until exposed to the array A one-layer contact hole is formed by the layer, the hole, and a substrate connected to the word line contact hole and the gate opening formed by the gate contact, a gate contact, and a portion of the layer from which the substrate opening is removed; and The substrate contacts A metal is etched to etch the first masking layer to the second hole 0 1 3. The method as described in item 12 of the patent application scope, wherein an adhesive layer is formed before the metal layer is filled. 14 The method according to item 13 of the scope of patent application, wherein the adhesive layer Page 18 ^ 22702 consists of a patented titanium nitride layer and a titanium metal layer 15 consists of the method selected in item 12 of the patent scope, wherein the oxide layer is made of silicon carbide. H. The method described in item 12 of the scope of patent application, wherein the conductive layer 糸 is composed of doped polycrystalline silicon. f. The method according to item 2 of the scope of the patent application, wherein the first covering layer is composed of nitrided nitride, carbonized carbide or hard oxynitride. ^ 8. The method as described in item 12 of the scope of the patent application, wherein the second mask layer is composed of silicon nitride, carbide, or oxynitride. H The method as described in item 2 of the patent application scope, wherein the interlayer dielectric layer is composed of silicon dioxide. The method described in item 2 of the patent application, wherein the interlayer dielectric layer is composed of borophosphosilicate glass. Page 19