TWI222226B - Manufacturing method of thin-film transistor - Google Patents

Abstract

A manufacturing method of thin-film transistor is disclosed, which comprises: forming a gate lead structure on a substrate by a first exposing/developing/etching process; forming a source, drain and semiconductor channel by a second exposing/developing/etching process; forming an island-like transistor structure by a third exposing/developing/etching process; forming a passivation layer having a contact hole by a fourth exposing/developing/etching process; and forming a pixel electrode connected to the contact hole by a fifth exposing/developing/etching process.

Description

1222226 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a thin film transistor, and more particularly, to a method for manufacturing a thin film transistor with five photomask processes. '' [Prior art]

A general liquid crystal display device includes two substrates facing each other, which are separated from each other with a liquid crystal layer sandwiched between the two substrates. Each substrate has a ^^ electrode, and these two electrodes also face each other. When a voltage is applied to the two electrodes, an electric field will be generated between the two electrodes. The direction and direction of the liquid crystal molecules will change with the change in the strength and direction of the electric field. The change in the orientation of the liquid crystal molecules will cause the light penetration. With this change, therefore, by using this principle, the penetration of light is controlled so that the liquid crystal display device can display various patterns; the following first illustrates a conventional liquid crystal display device with a drawing.

As shown in FIG. 1, it is a perspective view of a conventional liquid crystal display device. A conventional liquid crystal display device includes an upper substrate 5 and a lower substrate 22, which face each other and are separated from each other, and are separated by a liquid crystal layer 5 in the middle. The upper substrate includes a black matrix 6, a color filter layer 7, and a common electrode 9 inside. The black matrix line 6 has a grid-like opening, which just fits the size of the color filter layer 7, including the two primary color red, green, and blue color filter layers. The common electrode 9 is on the color filter layer and is transparent. On the surface of the lower substrate 22, there are a gate line 1 and a data line 34. The gate and data lines cross each other to define the day zone p. The thin film transistor τ is a conversion element and exists in a region where the gate line 12 and the data line 34 intersect. The thin film transistor is composed of a gate electrode, a source electrode, and a non-electrode 'arranged in a matrix manner. The pixel electrode 56 is connected to the thin film transistor T and is formed in the pixel region p. The day element electrode 56 is made of a transparent conductive

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The film is composed of a material (indium-tin-oxide, ITO) that has a better ability to penetrate light, and the pixel electrode is corresponding to the oxide film. The lower substrate 22 includes a thin film, a thin film, and an attached color filter. The main symbol is D, the lead j is an anode, and the dendrite electrode 56 is arranged in a matrix. Liquid crystal display device array substrate. When the scan pulse is applied to the gate electrode of the thin film transistor through the gate line 12, a data signal is generated and reaches the thin film transistor electrode through the data line 34.

Liquid crystal display devices are driven by the photoelectric properties possessed by liquid crystals. ^ Crystal is a dielectric anisotropic material with spontaneous polarization. When a voltage is applied to it, it spontaneously polarizes to form a dipole, so the molecules will be aligned by the electric field. By the arrangement of liquid crystal molecules, the liquid crystal with optical properties can adjust the penetration of light, and the image of the liquid crystal display device is produced by the penetrating property of the light. As shown in Figures 2A to 2F, it is a cross-sectional view of a thin-film transistor, showing a conventional thin-film transistor manufacturing process with five mask processes.

As shown in FIG. 2A, the first metal layer is deposited on a substrate 100 by a physical vapor deposition method. The metal layer may be selected from one of aluminum, chromium, and molybdenum, and the substrate 100 is insulated. It is composed of alkali-free glass, and then a first photoresist layer (not shown) is formed on the first metal layer, and then developed with a first photomask under a first exposure and then engraved with a dry or wet surname. Unnecessary, a gate wire structure 101 is formed on the substrate 100 after the first metal layer, and then the first photoresist layer (not shown in the figure) after the gate wire structure 101 is exposed is removed. ). °, as shown in Figure 2B, sequential chemical vapor deposition method

Page 7 1222226 V. Description of the invention (3) Plating a gate insulating layer 102, a 104 and a second photoresist soil V V "03 and an ohmic contact layer with 筮 —— ,， I (Not shown) in the gate wire structure 1 η] said 1: 1: the hood is developed after the second exposure and then dried, and can not be divided into the '= area, and then the second exposure after the exposure is removed The crystal is not issued), in which the ohmic contact layer 10 ^^ type highly doped S (Figure gate insulation layer 102 can be nitrided n oxide @. — 日 ', and as shown in Figure 2C', the physical vapor phase The deposition method is plated with 28 m on the substrate containing a predetermined area of the island-shaped transistor to form a photoresist layer (not shown in the figure) on the second metal layer 105. After the third exposure and development of the three photomasks, dry etching or wet etching is used to form a spear, and a source 105a and a drain i05b are formed on a predetermined area of the island-shaped transistor. The source and the drain are The gap is not connected, and the gap exposes the ohmic contact layer 104 ′. The second metal layer 105 may be selected from one of aluminum, chromium, and molybdenum. As shown in FIG. 2D, the source 105a and the second photoresist layer (not shown) on the drain electrode 1051 as a mask, and the third electrode on the source electrode 105a and the electrode 105b is removed by dry etching. The photoresist layer (not shown) covers the ohmic contact layer 104, and the semiconductor layer 103 is exposed to form a semiconductor channel 106 located between the side source electrode 105a and the terminal 0.15b, It is a back channel etching (BCE) process, and the third photoresist layer (not shown) is finally removed after exposure thereon. As shown in FIG. 2E, 'plasma enhanced chemical vapor phase Deposition method: A protective layer 107 is formed on the substrate 100 including the island-shaped transistor region, and a fourth photoresist layer (not shown) is formed on the protective layer 107 with a fourth light.

1222226 V. Description of the invention (4) ^ After the mask is developed by the fourth exposure, the protective layer is dry-etched to have a contact hole 108 on the drain 105b, and finally the fourth photoresist layer after the exposure is removed ( (Not shown in the figure) 'wherein the protective layer 107 may be composed of a nitride stone or a dioxide stone.

As shown in FIG. 2F, a daylight electrode 1109 is plated on the protective layer 107 by means of physical vapor deposition to form a fifth photoresist layer (not shown) on the daylight electrode 109. 'And the fifth photomask is developed by the fifth exposure, and then the wet-etching process is used to' pattern the pixel electrode 109 so that it is connected to the drain electrode 105b via the contact hole 1o. 'Finally The fifth photoresist layer (not shown) is removed, and the pixel electrode 109 may be indium tin oxide metal. As shown in FIG. 3, it is a top view of a conventional thin film transistor. The disadvantage of the conventional technique is that when the semiconductor layer 10 is etched, the photoresist (not shown) above the semiconductor layer may be The attack of the plasma fades away and exposes the semiconductor layer 103a near the island. The exposed semiconductor layer 103 & will interact with oxygen to generate stone dioxide and will block the ohmic contact layer (not shown in the figure) ), There will be an ohmic contact layer (not shown in the figure) left next to the channel structure, so that when the thin film transistor is turned off, a leakage current will be generated, causing cross talk, flicker, and bright spot defects. ° [Inventive Content]

The main purpose of the present invention is to provide a method for manufacturing thin film crystals to solve or reduce the problems and disadvantages of the conventional techniques. The manufacturing method of the transistor is to avoid crosstalk. Another object of the present invention is to provide a thin film so that the thin film transistor does not have leakage current (c r 〇 s s t a 1 k), flicker, and bright spots.

1222226 V. Description of the invention (5), go, and the other-in order to provide a thin film transistor manufacturer does not change the mask pattern and the number of cases does not increase = mm increase the yield of the display device, you can greatly reduce V production Cost, increase profit. Each of the eight u's: Kang 4's purpose of Maoming and in order to achieve the above-mentioned advantages, # the formation of a closed-lead wire structure in a relatively high process ^: exposure first _ engraving process to form one of the-contact holes: the first : Exposure and development surname engraving system # 一 金 · # · + J to protect the 4 layers, and use the fifth exposure to develop the etching coat so that once the prime electrode is connected to the contact hole. Youjin 2: t: Ming: Mesh =, structural features, functions and manufacturing process have been improved, detailed description of the pattern matching diagram is shown in [Embodiment] As shown in Figures 4A to 4F, this power crystal is displayed Manufacturing process. ^ As shown in FIG. 4A, the masking film of the first cover is plated with a metal layer by physical vapor deposition :: --- the photoresist layer (not shown) on the first layer: With ί: Ϊ ί Ϊ After the first-exposure development, then wet etching or dry touch engraving 201 on-substrate 2. . The structure of the substrate 200 is insulated alkali-free glass (namely, not shown), Ming, Chromium, and other types. … The brother-metal layer can be selected from the method shown in FIG. 4B, which is sequentially plasma-enhanced chemical vapor deposition 1222226 V. Description of the invention (6) On-shovel-inter-electrode insulation layer 202, a semiconductor layer 2 3 204 is on the interconductor wire structure 201: the second contact layer, the first layer of the mongolian layer, the second layer of photoresistance (not shown in the figure) on the eight layer, and a second photomask-virtual k After the exposure and development of the younger brother Meng Yale, the dry etching process or the etching process is performed to remove the unnecessary 笫 -eight times, ^ ^ a metal layer to form a Mae 榀 205a and a drain electrode 205b in The ohmic contact island 9n ′ and the drain electrode 2 05b touch each other with an empty P: ^ 2 on: the source electrode is connected to the & 9nA Ganshi—A worker 丨 bearing & open '5 Hai gap exposed portion Part of the ohmic contact layer 204, the "middle consumption contact layer" and the other type of insulating layer 202 can be silicon nitride—Tong / θ / Zhagui Ziming, Cr, In Selection: Two public pictures: No 'Exposure on the source Mb and the drain 205b: "The 90 ohm layer (not shown) is used as a mask, and is not covered by the source 8 ^ / 急 " 5b cover The 204 area of the ohmic contact layer was removed by dry etching to form a 'semiconductor @ .π C ^ chan — etchlng' force ', /: channel reclamation process (back barrier layer ⑶ is not shown), to remove the exposure The finished second light is shown in Fig. 4D, the flying iridium-, 丨. Ρ The semiconductor channel 206 and the current shape of this mo-mo butterfly (not shown in the figure) are included in the complex two it # € π a ~ island shape + the substrate 20 in a predetermined area of the moon bean, fate: f Ε β = two exposure and development, and a dry etching process is performed to form an island: & domain. The three photoresist layers (not shown in the figure) are shown in Figure 4E, and the middle-protective layer 207 is formed to form a coating: Λ chemical vapor deposition method is applied on 0 7 to 筮 ... A photoresist layer (not shown in the figure) is subjected to a dry etching process after being developed by a fourth exposure mask of the protective layer.

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1222226 Brief description of the drawings. Figure 1 is a perspective view of a conventional liquid crystal display. Figures 2A to 2F are cross-sectional views of five mask film transistors of the conventional technology, showing the manufacturing process. Figure 3 is the conventional technology. Plan views of five photomask film transistors; and FIGS. 4A to 4F are cross-sectional views of five photomask film transistors of the present invention, showing the manufacturing process thereof. [Illustration of Symbols] 5 upper substrate 6 black matrix 7 color filter layer 9 common electrode 12 gate line 15 liquid crystal layer 22 lower substrate 34 data line 5 6 day electrode 100 substrate 101 gate wire structure 102 gate insulation layer 103 Semiconductor layer 103a exposed semiconductor layer 104 ohmic contact layer 105 second metal layer 1 0 5 a source

Page 13 1222226 Brief description of the diagram 105b Drain 106 Semiconductor channel 107 Protective layer 108 Contact hole 109 Day electrode 200 Substrate 201 Gate wire structure 202 Gate insulation layer 203 Semiconductor layer 204 Ohm contact layer 2 0 5a Source 20 5b Pole electrode 206 Semiconductor channel 207 Protective layer 208 Contact hole 209 Day electrode

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Claims (1)

1222226 6. Scope of patent application 1. A method for manufacturing a thin film transistor, which includes the following steps: sequentially forming a first metal layer and a first photoresist layer on a substrate; and exposing it with a first photomask After development, the first photoresist layer is patterned, a gate wire structure is formed on the substrate by etching, and the first photoresist layer is removed after exposure; a gate insulation layer, a semiconductor layer, and an ohm are sequentially formed. The contact layer, a second metal layer, and a second photoresist layer are patterned on the gate wire structure after exposure and development with a second photomask. The second photoresist layer is etched to form a semiconductor source and drain electrode. On the ohmic contact layer, a track is formed between the source electrode and the drain electrode, and the second photoresist layer is removed after exposure; a third photoresist layer is formed including the source electrode, the drain electrode, and the semiconductor. On the substrate of the channel and the semiconductor layer, a third photomask is used to pattern the third photoresist layer after exposure and development, and an island-shaped transistor region is formed by etching, and the third photoresist layer is removed after exposure. ; Forming a protection in sequence Layer and a fourth photoresist layer on the substrate including the island-like transistor region. The fourth photoresist layer is patterned after exposure and development with a fourth photomask, and is formed by etching to have a contact hole for protection Layer, and removing the fourth photoresist layer after exposure; sequentially forming a day element electrode and a fifth photoresist layer on the protective layer; and Page 15 1222226 6. The scope of the application for a patent uses a fifth photomask to pattern the fifth photoresist layer after exposure and development, to form a daylight electrode through the contact hole and the drain electrode after etching, and to remove the exposed photoresist. The fifth photoresist layer. 2. The method for manufacturing a thin film transistor according to item 1 of the scope of patent application, wherein the first metal layer is one selected from the group consisting of aluminum, chromium and molybdenum. 3. The method for manufacturing a thin film transistor according to item 1 of the scope of patent application, wherein the second metal layer is one selected from the group consisting of aluminum, chromium and molybdenum. 4. The method for manufacturing a thin film transistor according to item 1 of the scope of patent application, wherein the composition of the protective layer may be silicon nitride or silicon dioxide. 5. The method for manufacturing a thin-film transistor according to item 1 of the scope of the patent application, wherein the day electrode is composed of transparent indium tin oxide. 6. The thin-film transistor manufacturing method according to item 1 of the scope of the patent application, wherein the semiconductor channel uses the second photoresist layer exposed on the source and the drain as a mask, and is subjected to a channel etching process. (Back channel etching, BCE) formation. 7. The thin-film transistor manufacturing method according to item 1 of the scope of patent application, wherein the gate wire structure is formed on the substrate by dry etching or wet etching the first metal layer. 8. The method for manufacturing a thin film transistor according to item 1 of the scope of patent application, wherein the source electrode and the drain electrode are formed on the ohmic contact layer by dry etching or wet etching, and the source electrode and the drain electrode are formed on the ohmic contact layer. The drain electrodes are separated by a gap, and the gap exposes part of the ohmic contact layer. Page 16 1222226 6. Scope of patent application 9. If the application is for the half mask and the semiconductor is dry-etched 10. If the application is for the insurance and the drain is exposed 11. If the application is for the day > and the pole connection 12 13. If applying for the half of 13. Applying for the thin film transistor manufacturing method described in item 1 of the Orly range, the formation of the conductor channel includes using the second photomask as a mask to expose the exposed ohmic contact layer. , The semiconductor channel is exposed. The method for manufacturing a thin film transistor according to the first item of the invention, wherein the contact hole of the protective layer is formed by dry etching, and the contact hole is formed. The conductive layer is formed by wet etching, and through the contact hole and the thin film transistor manufacturing method described in item 1 of the above-mentioned range. The method for manufacturing a thin film transistor according to the first item of the invention, wherein the contact layer is an N-type highly doped chip layer. Page 17