TWI222083B - Data output circuit in combined SDR/DDR semiconductor memory device - Google Patents

Abstract

A data output circuit includes first, second, third, and fourth data latches, and first and second data output drivers. The first, second, third, and fourth latches generate first pull-up signals, second pull-up signals, first pull-down signals, and second pull-down signals, respectively. In DDR mode, first and third latches latch even data in response to an even clock, while second and fourth latches latch odd data in response to an odd clock. In SDR mode, first and third latches latch first data in response to a data output clock, while second and fourth latches latch second data in response to the data output clock. The first and second data output drivers drive a first and second output pad, respectively, to predetermined voltages in response to the pull-up signals and the pull-down signals. The data output circuit reduces the number of data buffers, reducing the size of a semiconductor memory device.

Description

发明 Description of the invention: Cross-reference to related applications This application claims the priority of Korean Patent Application No. 2002-57454, which was filed with the Korean Intellectual Property Office on September 19, 2002. This case is fully incorporated by reference for all purposes. Included in this article. [Technical field to which the invention belongs] The present disclosure relates to a semiconductor memory device, and more specifically, to a combined single data rate / double data rate (Smgle data rate / double data rate; SDR / DDR) synchronous semiconductor memory A data output circuit in the body device. [Prior Art] Generally, a synchronous semiconductor memory device operates in a single data rate mode, in which one bit of data is input / output for each data input / output pin during a clock cycle. However, in order to improve a data input / output rate, a semiconductor memory device operating in a dual data rate mode has been used in which two-bit data is input / output for each data input / output pin during a clock cycle. A semiconductor memory device includes a number of data output circuits, each of which is referred to as a $ _ 卜 — / shell pin and includes a data output buffer and a data output driver. The internal data read by the memory unit is output to the outside. It is said that, in the semiconductor memory device with no data rate and dual data rate, the data output buffers of L, Z, and Kelvin can be used as the combined single data rate / dual data ^ punch. The number of buffers increases, and the efficiency of the output buffer is 87976 degraded. Fig. 1 is a block diagram of a lean output circuit in a conventional combined single-data-rate / dual-data-rate half-memory device. 1 Consider Figure 1. "Data output includes-data output buffer 100 and-lean output driver 200. Here, the data output buffer 100 includes four data latches ⑴ to 114 and two drivers. 121 and 122. It is assumed that the semiconductor memory device operates in a dual data rate mode. In this case, the first and third data latches ⑴ and ⑴ latch an even number in response to an even clock CLK-E. Data D-E, and the level of the latched data is converted to output the data. Therefore, the first and third data latches ⑴ and 113 latch data to be output on the rising edge of the clock, The second and fourth latches 112 and 114 latch the data to be output at the falling edge of the clock. The drivers 121 and 122 drive the data received from the data latches 丨 丨 丨 丨 14 to output a The pull-up control signal PB and the pull-down control signal Nβ. The shell material output driver 200 includes a pull-up transistor pM and a pull-down transistor NM1. Here, the pull-up transistor PM1 is formed of a PMOS transistor, The pull-down transistor NM1 is a NM0S transistor. The pull-up transistor p M j and the pull-down transistor NM1 are gated to respond to the pull-up control signal PB and the pull-down control signal NB output from the data output buffer 100 respectively. When the pull-up control signal PB is at a low level On time, the pull-up transistor pM1 is turned on to output a high-level output data DQ. When the pull-up control signal nb is at a high level, the pull-down transistor NM1 is turned on to output a low-level output 87976 1222083 data dq. Meanwhile, it is assumed that the semiconductor memory device operates in a single data rate mode. In this case, the second and fourth data latches 2 and ji 4 are not used. In other words, the first and third latches Π1 and 113 latch data D1 at the rising edge of the data output clock CLKDQ and switch the level of the latched data to output the data. Drivers 121 and 122 drive the data received from data latches 111 to! 14 'To output the pull-up control signal PB and pull-down control signal nb, as in the case of the dual data rate mode. The data output driver 200 outputs the output data DQ to the outside in order to return to the pull-up control. No. PB and pull-down control signal NB. As described above, the traditional data output buffer 100 latches and outputs one bit of data in single data rate mode, and latches and outputs two bits in dual data rate mode data.

Rush for. When Wei Semiconductor's memory device operates in χ8 dual data rate mode

87976 In other words, in addition to the combined single-chip semiconductor device 1222083 of FIG. 1, a dedicated single-data-rate data output circuit is also required. FIG. 2 is a circuit diagram of a conventional early-lean data rate / dual data rate semiconductor memory combined single data rate / dual data rate data output circuit, and a conventional single data rate / dual data rate half-d data rate data output circuit. The following will explain the traditional data output circuit by comparing the data output circuits of ===. Therefore, the 'data transfer rate / dual data rate of the semiconductor memory device', the number of U punches is equal to the number of data input / output pins, and the single data rate of Erfeng's lean input and output punches The data output buffer is crying and cannot be used in dual data rate mode.具体 Specific embodiments of the present invention address these and other disadvantages of conventional techniques. [Summary of the Invention] ^ A specific embodiment of the present invention provides a data output circuit, which combines buffering materials in a single data rate / dual data rate (sdr / ddr) semiconductor memory device to provide a buffer benefit, and It is possible to reduce the number of data output buffers and to reduce the size of the chip. [Embodiment] The present invention will now be described in detail with reference to the drawings showing preferred embodiments of the present invention. FIG. 4 is a block diagram of a data output circuit in a combined single data rate / dual data rate (SDR / DDR) semiconductor memory device according to a specific embodiment of the present invention. According to FIG. 4, the lean output output path includes a data output buffer 300 and first and second data output drivers 410 and 420. Here, the data output buffer 300 includes first to fourth lean latches 311 to 314, first to 87976 I2220B3 four drivers 321 to 324, and a plurality of switches SW1 to SW4. The younger one ‘the fake foot semiconductor device operates in a single data rate mode. In this case, the first and third switches SW1 and SW3 are turned off, and the second and fourth switches SW2 and SW4 are turned on. The first to fourth data latches 311 to 314 respectively latch the first data 〇1 or the second lean material D2 ′ in response to a data output clock CLKDQ and switch the locked data.

Save the raw materials to export the lean materials. Here, the data output clock ClkdQ is a clock signal generated in response to a rising edge or a falling edge of a clock. In this case, it is assumed that the rising edge of the clock will respond to the data output clock CLKDQ. The first and third data latches 311 and 313 latch the first data di, and the first data D1 is output to a first data input / output pin (not shown) via the first data output driver 410. The second and fourth 3H latches are: No. 2, No .: No. from No. :: Data output. The driver 420 outputs to a second data input / output pin (not shown). The first to fourth drivers 321 to 324 pre-drive the data output from the first to fourth data latches 311 to 314, respectively, to turn out the first and second pull-up control signals and cut PB2 and the first and second. Pull down the control signal and give it away. The data-output driver 410 responds to the first-pull-up control signal and the second-pull-down control signal to drive—the first round out of the contact area (not shown) to output a bit-bit at the rising edge of the clock. Rotate the data kiss, which is a single data rate data. In addition, the second data output driver is driven by the second pull-up control letter 2 and the second pull-down control signal—the second output contact area (not shown) to output another bit at the rising edge of the clock 87076 -10-1222083 output data DQ2, which is single data rate data. As a result, the "real material round-out buffer 300" latches and outputs two-bit data, which will output to two data input / round-out pins at the same time in the single lean rate mode. The structure of the first data output driver 410 will now be described in detail. The first data output driver 410 includes a pull-up transistor pMΓ & -pull-down transistor NM1. Here, the pull-up transistor ρμι is formed by a PMOS transistor, and the pull-down transistor NM1 is formed by an NMOS transistor. The pull-up transistor PM1 is formed between an external source voltage and the output contact area, and the pull-down transistor NM1 is formed between ground and the output contact area. The structure of the second data output driver 420 is the same as the structure of the first data output driver 41o, and therefore the description of the structure of the second data output driver 42o will not be repeated. Meanwhile, it is assumed that the semiconductor memory device operates in a dual data rate mode. In this case, the first and third switches SW1 and SW3 are turned on, and the second and fourth switches SW2 and SW4 are turned off. The first and third data latches 31 and 313 respond to an even-numbered clock CLK-E to latch even-numbered data D-E, and convert the level of the latched data to output the data. The second and fourth data latches 312 and 314 latch the odd data D-0 in response to an odd clock CLK-0, and convert the level of the latched data to output the data. Here, the 'even-numbered clock CLK_E is a clock signal generated in response to the rising edge of the clock, and the odd-numbered clock CLK_0 is a clock signal generated in response to the falling edge of the clock. □ Because the first and fourth switches SW2 and SW4 are in the off state, the first and fourth drives 322 and 324 do not operate. The first driver 321 receives data output from the first 87976-11-1222083 and the second data latches 311 and 312 to output the first pull-up control signal PB1. The third driver 323 receives data output from the third and fourth data latches 3 1 3 and 3 14 to output a first pull-down control signal NB j. Therefore, the rising edge and the falling edge of the clock generate the first pull-up control signal PB 1 and the first pull-down control signal nb 1 respectively. The first lean output driver 4 1 〇 drives the first output contact area (not output) in response to the first pull-up control signal pB 丨 and the first pull-down control signal NB 1 to output two bits during a clock cycle Data, which is a pair of data rate data. Here, waiting for one yuan poor material includes one yuan data on the rising edge of the clock and one yuan data on the falling edge of the clock. In the block diagram of FIG. 4, in response to the dual data rate mode or the single data rate mode, the switches SWiSSWA are used to enable the outputs of the first to fourth data latches 311 to 314 to be input to an appropriate data output driver. Alternatively, other types of interconnections can be used instead of using switches as mutual f. For example, in the dual data rate mode, a metal circuit is formed to connect the outputs of the second and fourth shell latches 312 and 314 to the first data output driver 4 through the first and third drivers 321 and 323. In addition, a metal line is formed in the single data a mode to connect the second and fourth data latches 3, 2 and 2 to the second data output driver 420 through the second and fourth drivers 322 and 3. "According to the present invention, the combined single data rate / dual data rate semiconductor memory is two and the circuit diagram of the data output circuit used in the dual lean rate mode. Change the ° H graph to merge the single data rate / dual data rate output circuit. The material output rate type is lean output circuit. With reference to Figures 4 and 5, the data input 87976 -12-1222083 output buffer 300 includes the first to fourth data latches 31 1 to 314, the first to fourth The data latches 311 to 314 include data latching devices 331 to 34, level conversion units 341 to 344, and buffers 351 to 354. Furthermore, because the data output circuit of FIG. 5 is dedicated to the dual data rate mode, Therefore, the first data output driver 410 is connected to the data output buffer 300 through the first and third drivers 321 and 323; however, the second data output driver 420 is not connected to the data output buffer 300. * More specific In other words, the first data latch 3 1 1 includes a first data latch device 331, a first level conversion unit 341, and a first buffer 351. The first data latch device 33 1 receives an even buffer control signal PTRST_E, even clock CLK_ E and even data D_E. Here, the even buffer control signal PTRST_E controls the output of the even data D_E. In other words, when the even buffer control signal PTRST_E is actuated to a predetermined level (that is, one of the present invention) High level), it will respond to the even-numbered clock CLK_E and output valid even-numbered data 1) _. More specifically, the first data latching device 331 is composed of inverter IV1, phase-inverter IV2, and NAND gate NANDI. , NOR gate NOR1 and NOR gate N0R2. Inverter IV2 inverts the even buffer control signal PTRST_E 〇 NOR gate NOR2 pairs of even data D-Ξ inversion data and even buffer control signal? The 8-to-3 reversal signal performs a NOR operation. The NAND gate NAND1 performs a NAND operation on the output of the even clock CLK_E and the output of the NOR gate N0R2 to output a first output signal OT1. NOR gate NOR1 Perform a NOR operation on the inversion signal of the even clock CLK-E and the output of the NOR gate NOR2 to output a second output signal 87976 -13-1222083 OT2. The first level conversion unit 34 1 converts the first output signal 〇T 1 internal voltage level is converted to external voltage More specifically, the first level conversion unit 341 is formed by an inverter INV and cross-coupled PMOS transistors PT1, PT2 and NMOS transistors NT1, NT2. When the first output signal Τ1 is at a At a high level, the NMOS transistor NT1 is turned on, and the PMOS transistor PT2 can be turned on, so the level of the signal input to the gate of the PMOS transistor PT3, which is one of the first buffers 351, becomes high. When the first output signal OT1 is at a low level, the NMOS transistor NT2 is turned on, so the level of the signal input to the gate of the NMOS transistor NT3, which is one of the first buffers 351, becomes low. The second data latch 312 also includes a second data latch device 332, a second level conversion unit 342, and a second buffer 352. Because the structures of the second data latching device 332, the second level conversion unit 342, and the second buffer 352 are the same as those of the first data latching device 331, the first level conversion unit 341, and the first buffer 3 5 The structure of 1 is the same, so it will not be repeated here. Here, the second data latching device 332 receives an odd-numbered buffer control signal "PTRS Ding-0, an odd-numbered clock CLK-0, and an odd-numbered data D-0. The odd-numbered buffer control signal PTRST-0 controls the odd-numbered data. D_〇 output. In other words, only when the odd buffer control signal PTRST_0 is actuated to a high level, it responds to the odd clock CLK — 0 and outputs valid odd data D — 0. The third data latch 313 includes the first The three data latching device 333, the third level conversion unit 343, and the third buffer 3 53. Because the structures of the third level conversion unit 343 and the third buffer 353 are the same as the first level conversion unit 341 87976- 14-1222083 and the first buffer miscellaneous 3 51, so they will not be repeated here. The difference between the structure of the third data latch device 333 and the first data latch device 331 is that the second material latch 333 includes a NANE ^ pole NAND2, instead of inverter IV2 and NOR gate no2, which are set to 33 1 instead of the first material latch. The fourth data latch 3i4 includes a fourth data latch device 334 and a fourth level. Conversion unit 344 and fourth buffer 354. Because the fourth data The structures of the 34th, fourth level conversion unit 344, and the fourth buffer are the same as those of the third data latching device 333, the third level conversion unit 343, and the third buffer 353. The operation is repeated. The operation of the data output circuit of FIG. 5 will now be described. First, it is assumed that even buffer control signals PTRST_E and odd buffer control signals PTRST-0 are both activated to a high level. Even-numbered clock CLK_E is at the rising edge or high on-time Even-numbered data D-E is at a high level, the first data latching device 331 outputs a low-level bluff, and the second lean latching device 3 3 3 outputs a low-level Therefore, the PMOS transistors of the first and third buffers 351 and 353 are turned on, and the voltage levels of the first and second nodes N1 and N2 become high. The first to fourth drivers 321 to 324 is formed by an inverter type. Therefore, the outputs of the first and third buffers 351 and 353 are inverted to become the first pull-up control signal PB 1 and the first pull-down control signal NB 丨. Therefore, Pull-up control signal PB 1 according to a low level And the pull-up transistor PM1 is turned on so as to output the data DQ of one level to the outside. If the even-numbered clock CLK-E is at the rising edge or the high-level even-numbered data DE is at a low level, then the first data latching device 33 1 outputs a high level signal 87976 -15-1222083, and the third data latching device 33 3 outputs a high level signal. Therefore, the NMOS transistors of the first and third buffers 351 and 353 are turned on, and the first And the voltage levels of the second nodes N1 and N2 become lower. As a result, the pull-down transistor NM1 is turned on according to a high-level first pull-down control signal NB1 so as to output a low-level data DQ to the outside. When the even clock CLK_E is at a rising edge or high level, the odd clock CLK_O is at a falling edge or low level. When the odd clock CLK-0 is at a falling edge or low level, a high level signal and a low level signal are input to the PMOS transistor and the NMOS transistor in the second buffer 352, respectively. The same signal is input to the fourth buffer 354. Therefore, when the even clock CLK_E is at a rising edge or high level, the second and fourth buffers 352 and 354 are in a closed state. When the odd-numbered clock CLK_0 is at a rising edge or high level, the states of the first and second nodes N1 and N2 are determined according to the odd-numbered data D-0, thereby determining the output data. When the odd-numbered data D_〇 is at a high level, it will output a high-level output data DQ to the outside, and when the odd-numbered data 0_0 is at _ a low level, it will output a low-level output data DQ to the outside. When the odd-numbered clock CLK_0 is at a rising edge or high level, the even-numbered clock CLK_E is at a falling edge or low level, so the first and third buffers 3 5 1 and 3 5 3 are in a closed state. When the even buffer control signal PTRST_E & the odd buffer control signal PTRST_0 is disabled to a low level, the data output circuit operates as follows. When the even buffer control signal is at a low level, the NOR gate NOR2 of the first data latching device 331 outputs a low level signal. 87976 -16-

Therefore, the NAND gate NAND1 outputs a high-level signal to turn off the PMOS transistor PT3 of the first buffer 351. The level of the signal input to the NMOS transistor NT3 of the first buffer 351 is determined based on the even clock CLK-E. When odd buffer control signal? Ding 118 Ding_〇 At a low level, the PMOS transistor of the second buffer 352 is turned off, and the level of the signal input to the N M 0 S transistor of the second buffer 3 52 is based on the odd time Pulse CLK-0 is determined as in the case of the first data latch device 331. · Therefore, the NMOS transistor NT3 of the first buffer 351 or the NMOS transistor of the second buffer 352 is turned on according to the switching of the even clock CLK_E and the odd clock CLK-0, and the bit of the first node N1 is promoted. The quasi becomes low. Therefore, the first pull-up transistor PM1 is turned off. When the even-numbered buffer control signal PTRST_E is at a low level, the NAND gate NAND2 of the third data latch device 332 outputs a high-level signal. Therefore, the NOR gate NOR 1 outputs a low-level signal, and the NMOS transistor of the third buffer 353 is turned off. The level of the signal input to the PMOS transistor of the third buffer 353 is determined according to the even clock CLK_E. When the spring odd buffer control signal PTRST — 0 is at a low level, the NMOS transistor of the fourth buffer 354 is turned off, and the NMOS transistor of the fourth buffer 354 is turned off, just like the third data latching device 333 The situation is average. In addition, the level of the PMOS transistor of the fourth buffer 354 is determined based on the odd clock CLK_0. Therefore, the PMOS transistor of the third buffer 353 or the PMOS transistor of the fourth buffer 354 is turned on according to the switching of the even clock CLK_E or the odd clock CLK-0, so as to promote the level of the second node N2. Becomes high. In addition, the first 87976 -17-1222083 pull transistor NM1 was turned off. Therefore, when the even buffer control signal T_E and the odd buffer control signal PTRST_0 are disabled to the low level, the first pull-up transistor PM1 and the first pull-down transistor NM1 are turned off, causing the first —Data output driver 4 10 outputs high impedance data. As described above, the data output buffer according to the present invention is used in a dual data rate mode—the data input pin latches and outputs odd data D 0 and even data 0 — £. —,

FIG. 6 is a circuit diagram of a shell material output circuit for a single data rate mode according to a specific embodiment of the present invention. In other words, the circuit of FIG. 6 is formed as follows: the combined single data rate / dual data rate data output circuit of FIG. 4 is set as a data output circuit for a single data rate mode. The structure of the data output circuit of FIG. 6 is the same as the structure of the data output circuit of FIG. Therefore, the structure of the data output circuit of FIG. 6 will not be repeatedly described here. The difference between the data output circuit of FIG. 6 and the data output circuit of FIG. 5 is as follows.

Because the data output circuit of FIG. 6 is dedicated to the single data rate mode, the first data output driver 410 is connected to the first and third data latches 311 of the data output buffer 300 through the first and third drivers 321 and 323. And 313, and the second data output driver 420 is the second and fourth data latches 312 and 314 connected to the data output buffer 300 through the second and fourth drivers 322 and 324. The operation of the data output circuit of Fig. 6 will now be explained. First, the pseudo-football brothers 1 and 2 buffer control signals PTRST 1 and PTRST ~ 2 are all activated to a high level. Here, the first and second buffers 87976 -18-1222083 control signals PTRST_1 and PTRST_2 control the output of the first and second data D1 and D2, respectively. In other words, when the first and second buffer signals PTRST_1 and PTRST-2 are both actuated at a predetermined level (ie, the high level of the present invention), they will respond to a data output clock CLKDQ and output valid first and second Two data D1 and D2. When the data output clock CLKDQ is at the rising edge or high level, the first and third data latching devices 3 11 and 333 receive the first data D 1 and the output signal to control the first and third buffers 351 and 353, respectively. PMOS transistor and NMOS transistor. In addition, the second and fourth latch devices 332 and 334 receive the second data D2 and the output signal to control the PMOS transistor and the NMOS transistor of the second and fourth buffers 352 and 354, respectively. When the first data D1 is at a high level, the first data latching device 331 outputs a low level signal, and the third data latching device 333 outputs a low level signal. Therefore, the PMOS transistors of the first and third buffers 351 and 353 are turned on, and the voltage levels of the first and third nodes N1 and N3 become high. Therefore, the first pull-up transistor PM1_ is turned on by a low-level first pull-up control signal PB1. As a result, a high-level first output data DQ1 is output to the outside. When the first data D1 is at a low level, the first data latching device 331 outputs a high-level signal, and the third data latching device 333 outputs a high-level signal. Therefore, the NMOS transistors of the first and third buffers 351 and 353 are turned on, and the voltage levels of the first and third nodes N1 and N3 become low. Accordingly, the first pull-down transistor NM1 is turned on by a high-level first pull-down control signal NB1. As a result, a low-level first output data DQ 1 is output to -19-87976 1222083. When the second data D2 is at a high level, the second data latching device 332 outputs a low level signal, and the fourth data latching device 334 outputs a low level signal. Therefore, the PMOS transistors of the second and fourth buffers 352 and 354 are turned on, and the voltage levels of the second and fourth nodes N2 and N4 become high. Therefore, the second pull-up transistor PM2 is turned on by a low-level second pull-up control signal PB2. As a result, a high-level second output data DQ2 is output to the outside. When the second data D2 is at a low level, the second data latching device 332 outputs a high-level signal, and the fourth data latching device 334 outputs a high-level signal. Therefore, the NMOS transistors of the second and fourth buffers 352 and 354 are turned on, and the voltage levels of the second and fourth nodes N2 and N4 become low. Accordingly, the second pull-down transistor NM2 is turned on by a high-level second pull-down control signal NB2. As a result, a low-level second output data DQ2 is output to the outside. When the first and second buffer control signals PTRST_1 and PTRST_2 are disabled to a low level, the operation of the data output circuit of FIG. 6 is similar to that of the data output circuit of FIG. 5. In this case, the even buffer control The signal PTRST_E & odd buffer control signal PTRST_0 is disabled to a low level. Therefore, when the first and second buffer control signals PTRST_1 and PTRST_2 are disabled to a low level, the first and second pull-up transistors PM1 and PM2 and the first and second pull-down transistors NM1 and NM2 are turned off. The first and second data output drivers 4 1 0 and 420 are caused to output high-impedance data. 87976 -20-As described above, the stubby Baco output buffer according to the present invention uses two data input magic outputs to latch and output two-bit data in the single data rate mode. As shown in Figures 5 and 6, the structure of the asset output circuit used for 雔 雔, 4 ^ ^.,, 楱 rate and single data rate mode is the same. N data in the data input path; ^ output in dual data rate mode ^ The output driver 42 is connected to the data for Γ, and the second data output driver 420 is connected to the data output of :: early = mode The data in the circuit is input E ^ :, where the Nd ~ I knife used to latch and output the first data D1 and output the first data D1 is used to make the odd data D 〇 part is used for electricity, and the child Used in the circuit for latching and input. The knife, the latch and the output of the second data D2, because the data output data output according to the present invention ^ pin knows the power; each does not need a dedicated single data rate read state, so the data output buffer can be improved. effectiveness. ^ The present invention and the conventional data output circuit of Figs. 2 and 3 make the effect of the present invention clearer. f Figure 1 and Figure 2 and Figure 5. In addition to Figure 2 including the second data output driver Cry 42, the traditional merger of single-funded operations "the use of the version of the invention," ~ Keyangbeike for the same circuit The data output circuit according to M (for the double lean rate) is the same as the data output circuits in Figures 2 and 5. The bit rate is different from the rate mode, in the single data rate grip, no Phases η and Λ ^ will be used. In Fig. 2 (the data output circuit is related to the odd-numbered data 1), say, m 丄 丨-out of the private road. More specifically / in the early shell material rate mode, use For receiving odd-numbered data D n * Buffer control operation _ | Lu Lu, —, countable a # refers to ST-0 and odd-numbered clock CLK-0. The terminals are grounded 87976 -21 1222083 and fixed at -low level. In addition, the data ^ Lkdq (replaces even-numbered clock CLK), 帛 -data D1 (replaces even-numbered data D- £), and buffer control signal PTRST (replaces even-numbered buffer control signal pTRsT e) are input at the output, which causes the data output of FIG. 2 The circuit operates in single data rate mode. Therefore, 'only the first and third data latching devices ⑶ and (3) The first and third level conversion units 141 and ⑷ and the first and third buffers 151 and 153, however, the second and fourth data latching devices η] and η *,

The second and fourth level conversion units 142 and 144 and the second and fourth buffers 152 and 154. Therefore, the traditional data output circuit of FIG. 2 requires a dedicated single data rate data output circuit, as shown in FIG. 2: The data output circuit according to a specific embodiment of the present invention can be set as shown in Figure $ for dual data paint < seeding bucket, ...,, and branch sheep type, and set as shown in Figure 6 for single The data rate fork type s < according to the specific embodiment of the present invention, the data output circuit can be used in A double @ material rate mode and single data rate mode. Traditional: The material output circuit also needs the data output circuit of Figures 2 and 3. Here, Fig. 2 (the material output circuit can be used in the dual data rate mode and the single data rate mode; however, Fig. 3 > κκ 土人 &&; page and output circuit are only used in the single data rate mode. Therefore, the required data buffer age θ ^, ′ increases, and the size of the semiconductor memory device increases. In contrast, the specific embodiment of Dn, _ & month reduces the required data. The buffer W reduces the size of the semiconductor memory device. According to the invention, the data output of the semiconductor memory device according to other specific embodiments of the present invention is two-amplified, each of the < million blocks. According to the present invention Another embodiment of the semiconductor memory memory class-UL's lean output circuit includes a data output buffer 87976 -22-1222083 punched to 5 0 0 first shell output driver 610 and a second data output driver (Not shown). The structure of the data output buffer 500 of FIG. 7 is similar to the structure of the data output buffer 300 of FIG. 3 except that switches SW5 to SW8 are further included. The drivers 321 to 324 drive the slave latch 311. To 314 received To output pull-up control signals PB1 — 1 and PB2 — 丨 and pull-down control signals nbi j and, NB2 — 1. When the switches SW5 to SW8 are on, generate and pull-up control signals PB1 -1 and PB2 -1, Pull-down control signals NB1 — 1 & NB2 — The same pull-up control numbers PB1-2 and PB2-2 and pull-down control signals NB1-2 and NB2 2. The first data output driver 61 of FIG. 8 includes two pull-up control signals. The pull-up transistors PMl-1 and PMl-2 and the two pull-down transistors NM1-1 and NM1-2. The pull-up transistors pMl — 丨 are turned on in response to the pull-up control signals PB1 -1 and ρΒ1-2, respectively.

PM1-2 to output a high-level output data DQ. In response to the pull-down control signals NB1-1 and NB1-2, the pull-down transistors NM1-1 & NM1 2 are turned on to output a low-level output data DQ. In another embodiment of the present invention shown in FIG. 8, a data output driver 610 includes two pull-up transistors PM1-_1 & pM1-2 and two pull-down transistors NM1-1-1 and NM1-2. However, the number of pull-up transistors and pull-down transistors can be changed. According to a specific embodiment of the present invention, the number of data buffers required can be reduced by merging the data output buffers in the combined single data rate / dual data rate semiconductor memory device. Therefore, the size of the semiconductor memory device can be reduced. In addition, by reducing the number of data buffers, skew between signals driving 87976 -23-1222083 moving data output drives can be reduced. Specific embodiments of the invention will now be described in a non-limiting manner. According to an aspect of the present invention, a data output circuit is provided in a combined single data rate / dual data rate semiconductor memory device. The data output circuit includes a first and a third data latches at a double data rate. In the mode, the first and third data latches latch even data in response to an even clock, and generate a first pull-up control signal and a first pull-down control signal, respectively, in a single data In the rate mode, the first and third data latches latch the first data in response to a φ data output clock, and generate the first pull-up signal and the first pull-down signal respectively; the second and fourth Data latches. In a dual data rate mode, the second and fourth data latches respond to an odd clock to latch odd data, and generate the first pull-up control signal and the first down respectively. Pull control signal, in a single data rate mode, the second and fourth data latches latch the second data in response to the data output clock, and generate a second pull-up control signal and a second Pull-down control signal; a first data Output driver, which drives the first output contact area to a predetermined voltage level in response to the first pull-up control signal and the first pull-down control signal; and a second data output driver, which returns A second pull-up control signal and the second pull-down control signal are used to drive a second output contact area to a predetermined voltage level. According to a specific embodiment of the present invention, the second data output driver can be electrically connected to the second and fourth data latches in a single data rate mode, and can be connected with the first and second data rates in a dual data rate mode. The second and fourth data latches are separated. 87976 -24- Another data output circuit in a combined single data rate / dual data rate semiconductor memory device according to another aspect of the present invention includes: a data output buffer for latching and outputting data from a memory cell Output data; and a plurality of data output drivers that generate output data in response to an output signal of the data output buffer, wherein the data output buffer includes an even data output buffer unit and a pair of data In the rate mode, the even data output buffer unit latches and outputs even data in response to an even clock. The data will be output to a first data pin. In a single data rate mode, the even data is output. The buffer unit responds to a data output clock to latch and output the first data, and the data will be output to the first data pin; and an odd data output buffer unit, in a double data rate mode, the The odd data output buffer unit latches and outputs the odd data in response to an odd clock. The data will be output to the first data pin and respond to the data. The output clock is used to latch and output the second data. This data will be output to a second data pin. A specific embodiment of the present invention may further include: a first data output driver, in a dual data rate mode, the first data output driver is electrically connected to the even data output buffer unit and the odd data output buffer A single data rate driver, and in a single data rate mode, the first data output driver is connected to the even data output buffer unit and separated from the odd data output unit; and a second data output driver at a single data rate It is electrically connected to the odd data output buffer unit in mode. According to another aspect of the present invention, a data output circuit in a combined single data rate / dual data rate semiconductor memory device includes: a data output buffer 87976-25-'which latches and outputs the data from _ 第-数据 在 Φ B fe 'unit outputs the information, and the first and the M respond to an output k of the asset output buffer to drive the first and the first-to know the contact area to a predetermined voltage level, Jt in the middle of the poor output buffer crying ^…, Qianju ... 叩 ——brother-a poor output buffer crying list 亓 3 ::!: Output; punch unit, "in, expected :: Temple brother and brother -The lean material output buffer unit is electrically connected to the first data = driver and latches the Omega which will be rotated out to the first output contact area: and countable lean material to return to shore-^ ^ heart clock The rising edge and falling edge of the signal are blunt, and in a single data rate mode, a sirloin, like 0 strong β 罘 Beco output buffer unit pen is connected to the first data output, bamboo pull out to drive fast, And latch the data that will be output to the first-output contact area, so that when you return to shore, you may click on the rising edge or the bottom edge And electrically connect the second data output buffer unit to the second data output driver and latch the data to be output to the second output contact area in response to the rising edge or falling edge of the clock mark. The data output circuit may further include: a first clock buffer, which responds to the rising clock of the clock; and the m buffer 'in the dual data rate mode', the second clock buffer responds to the falling of the clock The odd clock is generated at the edge, in the single data rate mode, 'the first clock buffer is used to generate the data output clock. Although the present invention has been specifically shown and explained with reference to its preferred embodiment' However, those skilled in the art should know the form and details of various changes without departing from the spirit of the present invention 2 as defined by the scope of the attached patent application. 87976 -26-1222083 [Simplified illustration of the drawing] By detailed explanation Exemplary embodiments of the present invention and the above aspects and advantages of the specific embodiments of the present invention can be more clearly understood with reference to the accompanying drawings. FIG. 1 shows a conventional combined single data rate / Data rate (SDr / ddr) block diagram of data output circuit in semiconductor memory device. Figure 2 is the traditional combined single data rate / dual data rate semiconductor memory device port, and single data rate / double lean data output The circuit diagram of the circuit. Fig. 3 is a circuit diagram of the output circuit of the dedicated single-data-computing and single-data output device in the conventional combined single-data-rate / dual-data-rate semiconductor memory device. Figure 4 is a circuit diagram according to the present invention. ， '… /, A block diagram of the combined single data rate / dual data rate semiconductor memory, with & 1 centered data output circuit with the sister example. Figure 5 is based on the present invention + half Daoqing 1-touch "Combined single data rate / dual data rate thousand inch bile of the planting example ^ Jiyi body suit, > ^ ^ Data output circuit for dual data rate mode Figure 6 shows the output circuit according to this dream material ... , Fa embodiment of the single data rate mode of funding, circuit diagram. Block diagram description of pen-out path] Figures 7 and 8 are based on the data wheel in the device. [Schematic symbols 100 111 121 112, 113, 114 122 131, 133 Data output buffer data latch driver No. 1 and No. Three data latch devices 87976 -27- 1222083 141, 143 15 and 153 132, 134 142, 144 152, 154 200 300 311, 312, 313, 314 321, 322, 323, 324 331, 332, 333, 334 341, 342, 343, 344 351, 352, 353, 354 410, 420 500 610

CLK_E CLK_〇

CLKDQ

D_E D_〇D1 D2 87976-28-First and third level conversion units First and third buffers Second and fourth data latching devices Second and fourth level conversion units Second and fourth Buffer data output driver data output buffer first to fourth data latch first and fourth driver data latch device level conversion unit buffer first and second data output driver data output buffer A data output driver even clock odd clock data output clock even data odd data data second data 1222083 DQ, DQl, DQ2 INV, IV1, IV2 N1, N2, N3, N4 NANDI, NAND2 NB, NB1 1, NB2_1, NB1, NB2_2 NB1, NB2 NM NM2, NM1J, NM1 NoR1, NoR2 NT1, NT2, NT3 〇T1 OT2 PB, PB11, PB2_1, PB1, PB2_2 PB1, PB2

PM1, PM2, PM1_1, PM1 PT1, PT2, PT3 PTRST1, PTRST_2 PTRSTE SW1-SW2 > SW3 > SW4 > S 'output data inverter node NAND gate 2 pull-down control signal first and second pull-down control signal 2 pull-down Transistor NOR gate NMOS transistor first output signal second output signal 2 pull-up control signal first and second pull-up control signal 2 pull-up transistor PMOS transistor first and second buffer control signal Even buffer control signal, SW6, SW7, SW8 switch-29-87976

Claims (1)

1222083 Patent application scope: 1. A data output circuit in a combined single data rate / double data rate (SDR / DDR) semiconductor memory device, the data output circuit includes: a first and a third data latch In a dual data rate mode, the first and third data latches respond to an even clock to latch the even data and generate a first pull-up control signal and a first pull-down control signal, respectively, And in a single data rate mode, the first and third data latches latch the first data in response to a data output clock and separately generate the first pull-up control signal and the first down Pull signal; a second and a fourth data latch, in the dual data rate mode, the second and fourth data latches respond to an odd clock to latch the odd data, and generate the first data respectively A pull-up control signal and the first pull-down control signal, and in the single data rate mode, the second and fourth data latches respond to the data output clock and latch the second data, and generate the data separately A second pull-up control signal A second pull-down signal; a first data output driver that drives a first output contact region to a predetermined voltage level in response to the first pull-up control signal @ and the first pull-down control signal; and A second data output driver drives a second output contact area to a predetermined voltage level in response to the second pull-up control signal and the second pull-down control signal. 2. If the data output circuit of the first patent application range, wherein in the single data rate mode, the second data output driver is electrically connected to the second and fourth data latches, and the dual data In rate mode, it is separate from the second and fourth data latches of 87976 1222083. 3. The data output circuit according to item 2 of the patent application scope, wherein the data output circuit includes: a first switch that connects the second data latch to the first data output in the dual data rate mode Driver; a second switch that connects the second data locker to the second data output driver in the single data rate mode; a third switch that connects the first data lock in the dual data rate mode Four data lock registers are connected to the first data output driver; and a fourth switch connects the fourth data latch to the second data output driver in the single data rate mode. 4. The data output circuit according to item 1 of the patent application scope, further comprising: a first clock buffer that generates the even clock in response to a rising edge of a clock in the dual data rate mode; and a first clock The two-clock buffer generates the odd clock in response to the falling edge of the clock in the dual-data-rate mode, where the first clock buffer is used in the single-data-rate mode, Generate the data output clock. 5. The data output circuit according to item 1 of the patent application, wherein when a predetermined buffer control signal is in an inactive state, the first, second, third and fourth data latches are generated. The first and second pull-up control signals and the first and second pull-down control signals can turn off the first and second data output drivers. 6. The data output circuit according to item 1 of the patent application scope, wherein the first 87976 and the second data output driver respectively include at least two pull-up transistors connected in parallel and at least two pull-down transistors connected in parallel. 7. —A data output circuit in a combined single-data-rate / dual-data-rate semiconductor memory device. The lean output circuit includes: a data output buffer that latches and outputs data output from a memory unit; And a first and a second data output driver, which generate output data in response to an output signal of the data output buffer, wherein the data output buffer includes: an even data output buffer unit, a pair of data In the rate mode, the even data output buffer unit latches and outputs even data in response to an even clock. The data will be output to a first data pin, and in a single data rate mode, the even data The output buffer unit latches and outputs the first data in response to a data output clock, and the data will be output to the first data pin; and an odd data output buffer unit, in the dual data rate mode, The odd-numbered data output buffer unit responds to an odd-numbered clock to latch and output the odd-numbered data. The data will be output to the first data pin. And a second latch clock and outputs data to be output data back to the data to be output to a second data connection pins. 8. The data output circuit according to item 7 of the scope of patent application, wherein: in the dual data rate mode, the first data output driver is electrically connected to the even data output buffer unit and the odd data output buffer. Unit, and in the single data rate mode, the first data output 87976 1222083 driver is connected to the read-out, under-even shell output buffer, and the single-data output unit is separated. 4. ^ q ^, the second data output driver is electrically connected to the countable data output buffer unit. 9. If the data output circuit according to the patent application is the "data output circuit", the step further includes a-clock buffer, which generates the even clock in response to the rising edge of a clock in the dual data rate mode; and a clock The two-clock buffer generates the odd-numbered clock in response to the falling edge of the clock in the dual data rate mode, and in the single data rate mode, the first clock buffer is used to generate the clock Data output clock. 10. The data output circuit of item 8 of the patent application park, wherein when a predetermined buffer control signal is in an inactive state, the first and second data output drivers are turned off to output high The output data of the impedance. Π. The data output circuit according to item 8 of the patent application range, wherein the first and second data are fortunate to include that the driver includes at least two pull-up transistors connected in parallel and at least two connected in parallel. Pull-down transistor 12. 12. A data output circuit in a combined single data rate / dual data rate semiconductor memory device, the data output circuit includes: a data output buffer, its lock Storing and outputting the data output from a memory unit; and the first and second data output drivers which respond to an output signal of the data output buffer to drive the first and second output contact areas to a member疋 _Voltage level, 87976 1222083… where the data output buffer includes a first data output buffer unit and a second data output buffer unit, where in the -dual data rate mode, the first and second The two data output buffer units are electrically connected to the first data output driver and latch the even data and the odd data to be output to the first output contact area in response to the rising edge and the τ falling edge of the clock signal. And in the single data rate mode, the first data output buffer unit is 'electrically connected to the first data output driver' and responds to the rising edge or falling edge of the clock as a number and latches the output to The data in the first output contact area and the second data output buffer unit are electrically connected to the second data output driver and respond to the rising edge of the clock signal. The falling edge latches the data that will be output to the second output contact area.! 3. The data output circuit according to item 12 of the patent application scope, further comprising: a first clock buffer, which is in the dual data The even-numbered clock is generated in response to the rising edge of the clock in the rate mode; and a second clock buffer generates the odd-numbered clock in response to the falling edge of the clock in the dual-data-rate mode, where In the single data rate mode, the first clock buffer is used to generate the data output clock. 14. The data output circuit of item 12 of the patent application scope, wherein when a predetermined buffer control signal is in an inactive state In the state, the first and second data output drivers are turned off to output high-impedance output data. 87976 1222083 15. If the data output circuit of the patent application No. 12, the first and second data output drivers Each includes at least two pull-up transistors connected in parallel and at least two pull-down transistors connected in parallel. 16. —A method of operating a data output circuit configured to operate in a combined single data rate / dual data rate (SDR / DDR) semiconductor device, including: during a dual data rate mode, responding to an even clock using one A first data latch and a third data latch to latch even data; ^ during the dual data rate mode, a second data latch and a fourth data lock are used in response to an odd clock Register to latch odd data; during a single data rate mode, in response to a data output clock, use the first data latch and the third data latch to latch the first data; in the single data During the data mode, the second data latch and the fourth data latch are used to latch the second data in response to the data output clock; during the dual data rate mode, the first and third data are used. The data lock * register generates a first pull-up control signal and a first pull-down control- signal, respectively, and also uses the second and fourth data latches to generate the first pull-up control signal and the first A pull-down control signal; During the single data rate mode, the first and third data latches are used to generate the first pull-up control signal and the first pull-down control signal, respectively, and the second and fourth data latches are used. The controller generates a second pull-up control signal and a second pull-down control signal respectively; in response to the first pull-up control signal and the first pull-down control signal, 87976 1222083 uses a first data output driver to transfer a first-round The output contact area is driven to a predetermined voltage level; and σ should use a second pull-up control signal and the pull-down control signal and use a second data output driver to drive a second round of output contact area to A predetermined voltage level. • The method of claim 16 of the patent scope, further comprising: electrically connecting the second data output driver to the second data latch and the fourth data latch in a single-batch rate mode, and In the dual lean mode, the second data output driver is electrically separated from the second data latch and the fourth data latch. • The method according to claim 17 of the patent scope, further comprising: during the dual lean mode, using a first switch and a third switch respectively to connect the first data output driver to the second data latch And the fourth data latch; and during the single data rate mode, a second switch and a fourth switch are used to connect the second data output driver to the second data latch and The first data latch. 19. The method of claim 16 in the scope of patent application, further comprising: in the dual data rate mode, responding to the rising edge of a clock and using the -th -clock buffer to generate the even clock, and respond to the time The second clock buffer is used to generate the odd-numbered clock at the falling edge of the clock. In the single data rate mode, the first clock buffer is also used to generate the data output clock. 20. For example, the scope of application for patent No. 16J Beizhifang &, wherein the _ ^ 拉 _ 信 1222083, the second pull-up control signal, the first pull-down control signal and the second pull-down control signal are used for configuration The first and second data output drivers are turned off when a predetermined buffer control signal is in an inactive state. 21. The method of claim 16, wherein using a first data output driver to drive a first output contact area to a predetermined voltage level includes using at least two pull-up transistors connected in parallel; and Wherein using a second data output driver to drive a second output contact area to a predetermined voltage level includes using at least two pull-down transistors. 87976