TWI313459B - Write circuit of memory device and method for driving the same - Google Patents

Write circuit of memory device and method for driving the same Download PDF

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Publication number
TWI313459B
TWI313459B TW095123714A TW95123714A TWI313459B TW I313459 B TWI313459 B TW I313459B TW 095123714 A TW095123714 A TW 095123714A TW 95123714 A TW95123714 A TW 95123714A TW I313459 B TWI313459 B TW I313459B
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Taiwan
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data
block
comparison
signal
output
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TW095123714A
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Chinese (zh)
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TW200713272A (en
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Beom-Ju Shin
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Hynix Semiconductor Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Description

1313459 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體記憶體裝置之寫入電路；更明 確言之，本發明係關於一種用於在寫入操作期間減少電流 消耗之半導體記憶體裝置之寫入電路。 【先前技術】BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a write circuit for a semiconductor memory device; more specifically, the present invention relates to a semiconductor memory for reducing current consumption during a write operation The write circuit of the body device. [Prior Art]

為了以高速操作半導體記憶體裝置，不僅需要改良中央 處理單元（CPU)之操作速度而且需要藉由盡可能多地減少 CPU之等待時間來縮短半導體記憶體裝置的存取時間。 在非同步動態隨機存取記憶體（DRAM)之狀況下，需要一 延遲時間對非同步DRAM之時脈與系統時脈進行同步。因 此，為避免延遲時間之必要性，一與系統時脈同步操作之 同步動態隨機存取記憶體（SDRAM)為較佳的。由於SDRAM 不需要延遲時間，故SDRAM具有較短存取時間。 一般而言，SDRAM回應在系統時脈轉變時所產生之脈衝 訊號而操作。SDRAM根據用於轉變系統時脈之方法而分類 為單資料速率（SDR)SDRAM及雙資料速率（DDR)SDRAM。 SDR SDRAM回應系統時脈之上升邊緣而產生一脈衝訊 號進而輸入或輸出與所產生之脈衝訊號同步的資料及指 令。DDR SDRAM回應系統時脈之上升及下降邊緣而產生脈 衝訊號進而輸入或輸出與所產生脈衝訊號同步之資料及指 令。 DDR SDRAM根據預提取操作之種類而分類為DDR1 SDRAM、DDR2 SDRAM 等。DDR1 SDRAM在資料輸入或輸 112499.doc 1313459 出操作期間執行2位元預提取。DDR2 SDRAM在資料輸入或 輸出操作期間執行4位元預提取。 圖1為展示先前技術SDRAM之寫入操作之方塊圖。 如圖所示，SDRAM包括：資料輸入/輸出墊（DQ_PAD) 1 0、 預提取區塊20、資料傳遞區塊30、放大區塊（DIN IOSA)40 及全域資料輸入/輸出線50。 在SDRAM之寫入操作期間，SDRAM經由DQ_PAD 10接收 輸入資料。In order to operate the semiconductor memory device at a high speed, it is not only necessary to improve the operation speed of the central processing unit (CPU) but also to shorten the access time of the semiconductor memory device by reducing the waiting time of the CPU as much as possible. In the case of non-synchronous dynamic random access memory (DRAM), a delay time is required to synchronize the clock of the asynchronous DRAM with the system clock. Therefore, in order to avoid the necessity of delay time, a synchronous dynamic random access memory (SDRAM) synchronized with the system clock is preferred. Since SDRAM does not require a delay time, SDRAM has a shorter access time. In general, the SDRAM operates in response to a pulse signal generated during system clock transitions. SDRAM is classified into single data rate (SDR) SDRAM and dual data rate (DDR) SDRAM according to the method used to convert the system clock. The SDR SDRAM generates a pulse signal in response to the rising edge of the system clock to input or output data and instructions synchronized with the generated pulse signal. The DDR SDRAM generates a pulse signal in response to the rising and falling edges of the system clock and then inputs or outputs data and instructions synchronized with the generated pulse signal. DDR SDRAMs are classified into DDR1 SDRAM, DDR2 SDRAM, etc. depending on the type of pre-fetch operation. DDR1 SDRAM performs 2-bit prefetch during data entry or output operation. DDR2 SDRAM performs 4-bit prefetching during data input or output operations. 1 is a block diagram showing a write operation of a prior art SDRAM. As shown, the SDRAM includes: a data input/output pad (DQ_PAD) 10, a pre-fetch block 20, a data transfer block 30, an amplifying block (DIN IOSA) 40, and a global data input/output line 50. During the write operation of the SDRAM, the SDRAM receives the input data via the DQ_PAD 10.

對於DDR1 SDRAM而言，需要兩個預提取區塊20來預提 取經由DQ_PAD 10輸入之輸入資料。對於DDR2 SDRAM而 言，需要四個預提取區塊20來預提取經由DQ_PAD 10輸入 之輸入資料。DDR2 SDRAM係描述於圖1中。 參看圖1，在DDR2 SDRAM之寫入操作期間，自預提取區 塊20輸出之預提取資料A0至A3根據藉由模式暫存器設定 之行位址CA<1:0>及叢發類型而經由資料傳遞區塊30作為 寫入資料D0至D3傳遞至放大區塊40。 表1為基於行位址CA<1:0>及叢發類型經資料傳遞區塊 30傳遞至放大區塊40之寫入資料D0至D3的例示性說明。叢 發類型分類為循序類型及交錯類型。 [表1] 叢發類型 CA<1:0> DO D1 D2 D3 循序 00 AO A1 A2 A3 01 A1 A2 A3 A0 10 A2 A3 A0 A1 11 A3 AO A1 A2 112499.doc 1313459 .w叫例叫机八窃，便得放大For DDR1 SDRAM, two prefetch blocks 20 are required to prefetch the input data input via DQ_PAD 10. For DDR2 SDRAM, four pre-fetch blocks 20 are required to pre-fetch the input data input via DQ_PAD 10. The DDR2 SDRAM is described in Figure 1. Referring to FIG. 1, during the write operation of the DDR2 SDRAM, the prefetched data A0 to A3 output from the prefetch block 20 are based on the row address CA<1:0> and the burst type set by the mode register. The data transfer block 30 is transferred to the enlargement block 40 as the write data D0 to D3. Table 1 is an illustrative illustration of the write data D0 to D3 that are passed to the amplification block 40 via the data transfer block 30 based on the row address CA<1:0> and the burst type. The burst type is classified into a sequential type and an interleaved type. [Table 1] Cluster type CA<1:0> DO D1 D2 D3 Sequence 00 AO A1 A2 A3 01 A1 A2 A3 A0 10 A2 A3 A0 A1 11 A3 AO A1 A2 112499.doc 1313459 .w Calling a machine , you have to zoom in

區塊刪回應資料輸出訊號DQS之上升及下降邊緣而鎖存 之寫入貝料DG至D3進行放大以將放大之資料輸出至全域 資料輸入輸出線50。為了同步輸人資料，在寫人操作期間 施加資料輸出tfl號DQS。亦即，將寫人以彻至出自_ 域轉換成時脈域。 參看圖1 ’在SDRAM寫入操作期間，用於控制放大區塊 4〇之啟用訊號為時脈訊號CLK。因此，放大區塊4q始終回 應資料輸出訊號DQS之上升及下降邊緣而將寫人f料〇〇至 D3作為全域資料輸出至全域資料輸入/輸出線，而不檢查 全域資料輸入/輸出線5〇處之全域資料。 如上文所述，放大區塊4〇始終在SDRAM2寫入操作期間 運作進而消耗不必要之電流。The block deletes the rising and falling edges of the response data output signal DQS and latches the write stuff DG to D3 for amplification to output the amplified data to the global data input/output line 50. In order to synchronize the input data, the data output tfl number DQS is applied during the writer operation. That is, the writer is converted into the clock domain from the _ domain. Referring to FIG. 1 ' during the SDRAM write operation, the enable signal for controlling the amplification block 4 is the clock signal CLK. Therefore, the amplifying block 4q always responds to the rising and falling edges of the data output signal DQS and outputs the writing material to the D3 as the global data output to the global data input/output line without checking the global data input/output line 5〇. Global information. As described above, the amplifying block 4 is always operated during the SDRAM 2 write operation to consume unnecessary current.

交錯 00 A0 01 A1 — 10 A2 11 A3 —A1 A2 A3 A0 A3 A2 A3 A0 *"1 _ A1 A2 A1 __ — --------- A0 【發明内容】 因此，本發明之目的為提供一種半導體記憶體裝置之寫 入電路，其藉由基於寫入資料與半導體記憶體裝置内全域 資料I/O線之全域資料的比較結果而選擇性地執行寫入操 作來減少不必要之電流消耗。 根據本發明之一態樣，提供一種半導體記憶體裝置之寫 入電路，其包括：一全域資料輸入/輸出（I/O)線；—放大區 塊’其用於接收及放大寫A資料並將放大之寫入資料作為 全域貧料而傳輸至全域資料1/0線上；及一控制區塊，其用 I12499.doc 寫入資料與全域資料Interleaving 00 A0 01 A1 — 10 A2 11 A3 — A1 A2 A3 A0 A3 A2 A3 A0 *"1 _ A1 A2 A1 __ — --------- A0 [Invention] Therefore, the object of the present invention is A write circuit for a semiconductor memory device is provided for selectively reducing a unnecessary current by performing a write operation based on a comparison result between a write data and a global data of a global data I/O line in a semiconductor memory device Consumption. According to an aspect of the present invention, a write circuit of a semiconductor memory device is provided, comprising: a global data input/output (I/O) line; and an amplification block for receiving and amplifying write A data. The amplified write data is transmitted to the global data 1/0 line as a global poor material; and a control block, which uses I12499.doc to write data and global data.

1313459 於比較寫入資料與全域資料，進而當 具有大體相同資料值時停用放大區塊 據本發明之一態樣，提供一種用於寫入資料之半導體 口己隐體裝置，丨包括：_全域資料輸入/輸出㈣線；一全 域鎖存區塊’其用於鎖存該全域資料ι/〇線之全域資料；一 =提取區塊’其用於接收及預提取經由資料墊傳輪之輸入 f料亚在寫人操作期間將輸人資料作為經預提取之資料而 輸出，及-貝料傳遞區塊，其用於接收經預提取之資料並 回應藉由模式暫存器設定之行位址及叢發類型而將經接收 之資料作為寫人資料輸出；—控制區《，其用於藉由比較 寫入資料與全域資料1/0線之全域資料，而產生放大啟用訊 號，及一放大區塊，其基於放大啟用訊號而接收及放大寫 入貝料並選擇性地將經放大之寫入資料作為全域資料傳輸 至全域資料I/O線上。 根據本發明之另一態樣，提供一種用於驅動一半導體記 體裝置之方法，該半導體記憶體裝置包括一用於接收及 放大寫入資料並將寫入資料作為全域資料而輸出至全域資 料輸入/輸出（I/O)線上之放大及驅動裝置，該方法包括：比 較寫入資料與全域資料；當寫入資料與全域資料具有相同 資料值時停用該放大及驅動裝置；及當寫入資料與全域資 料具有大體不同之資料值時啟用該放大及驅動裝置。 【實施方式】 下文中，將參看隨附圖式詳細描述根據本發明之半導體 記憶體裝置之寫入電路。 112499.doc 1313459 圖2為根據本發明之半導體記憶體裝置之寫入操作的方 塊圖。 根據本發明之半導體記憶體裝置包括：資料輸入/輸出墊 (DQ PAD)10、預提取區塊200、資料傳遞區塊300、資料輸 入放大區塊（DIN IOSA)400、全域資料輸入/輸出線500、控 制區塊600及全域鎖存區塊700。 預提取區塊200接收並預提取經由DQ PAD 10輸入之輸入 資料，以將輸入資料作為預提取資料A0至A3予以輸出。 資料傳遞區塊300接收自預提取區塊200輸出之預提取資 料A0至A3，以回應藉由模式暫存器設定之行位址CA<1:0> 及叢發類型（意即，循序類型或交錯類型），而將經接收之資 料作為寫入資料D0至D3而輸出至資料輸入放大區塊400。 資料輸入放大區塊400接收及放大寫入資料D0至D3，以 將經放大之資料作為全域資料GIO_DO至GIO_D3而輸出至 全域資料I/O線500，意即，GIO_QO至GIO_Q3。 控制區塊600比較輸入至資料輸入放大區塊400之寫入資 料D0至D3與全域資料I/O線500之全域資料GIO—DO至 GIO_D3，進而當寫入資料D0至D3與全域資料GIO_DO至 GIO—D3具有相同資料值時停用資料輸入放大區塊400。 控制區塊600包括比較區塊620及訊號產生區塊640。比較 區塊620比較寫入資料D0至D3與全域資料GIO—DO至 GIO_D3。訊號產生區塊640藉由將比較區塊620之輸出與時 脈訊號CLK相組合，而產生一用於啟用或停用資料輸入放 大區塊400之放大啟用訊號AMP EN。 112499.doc 1313459 全域鎖存區塊700鎖存全域資料I/O線500之全域資料 GIO—D0至GIO—D3進而防止全域資料I/O線500浮動。 下文中，將根據多種實施例描述用於選擇性地驅動資料 輸入放大區塊400之方法。 為了便於闡述，使用基本單元（例如單元資料輸入放大區 塊400A、全域資料I/O線500A、單元控制區塊600A及單元 全域鎖存區塊700A)來描述半導體記憶體裝置之每一組件。 圖3為根據本發明之第一實施例之用於選擇性驅動資料 輸入放大區塊400之半導體記憶體裝置的方塊圖。 如圖所示，單元資料輸入放大區塊400A回應自單元控制 區塊600A輸出之放大啟用訊號AMP_EN而比較寫入資料D 與全域資料GIO_D。單元全域鎖存區塊700A鎖存單元資料 輸入放大區塊400 A之輸出以將經鎖存之資料輸出至對應全 域資料I/O線500A。 單元控制區塊600A包括單元比較區塊620A及單元訊號 產生區塊640A。單元比較區塊620A比較寫入資料D與全域 資料GIO_D。單元訊號產生區塊640A基於單元比較區塊 620A之輸出與時脈訊號CLK而產生用於控制單元資料輸入 放大區塊400A之放大啟用訊號AMP_EN。 詳言之，本發明之第一實施例之單元比較區塊620A始終 被啟用。參看圖3,單元比較區塊620 A包括一互斥閘XOR1， 其用於接收寫入資料D及全域資料GIO_D以在其之間執行 一”互斥或"（XOR)運算。亦即，單元比較區塊620A僅當寫 入資料D與全域資料GIO_D具有不同資料值時輸出具有邏 112499.doc 10· 1313459 輯位準’’高”之資料。 此外，單元訊號產生區塊640A包括一 π及”（AND)閘 AND1，其執行單元比較區塊620A之輸出與時脈訊號CLK 之’’及”運算，以將結果作為放大啟用訊號AMP_EN而輸出至 單元資料輸入放大區塊400A。 圖4為根據本發明之第二實施例之半導體記憶體裝置的 方塊圖，該半導體記憶體裝置基於一測試模式訊號而選擇 性地驅動資料輸入放大區塊400。 p 如圖所示，除了單元比較區塊620B接收一作為比較啟用 訊號COM_EN而輸入之外部測試模式訊號TEST—MODE以 便基於該比較啟用訊號COM_EN選擇性地被啟用之外，圖4 中所示之第二實施例之記憶體裝置類似於圖3中所示的第 一實施例之記憶體裝置。 單元比較區塊620B包括一”互斥反或"（XNOR)閘XNOR1 及一 ”反及"（NAND)閘NAND1。”互斥反或”閘XNOR1接收寫 入資料D及全域資料GIO_D以在其之間執行”互斥反或”運 • 算。”反及”閘NAND1接收”互斥反或”閘XNOR1之輸出及比 較啟用訊號COM_EN以在其之間執行一”反及”運算。因此， 若比較啟用訊號COM_EN被啟用，則單元比較區塊620B僅 當寫入資料D與全域資料GIO_D具有不同資料值時才輸出 具有邏輯位準”高”之資料。 此外，單元訊號產生區塊640B包括一 ”及”閘AND2，其執 行單元比較區塊620B之輸出與時脈訊號CLK之及”運算， 以將其作為放大啟用訊號AMP_EN而輸出至單元資料輸入 112499.doc -11 - 1313459 放大區塊400A。 圖5為根據本發明之第三實施例之半導體記憶體裝置的 方塊圖，該半導體記憶體裝置基於一熔絲選用而選擇性地 驅動資料輸入放大區塊4 0 0。 如圖所示，除了用於控制單元比較區塊620C之比較啟用 訊號COM_EN係藉由一熔絲選用電路660C產生之外，圖5 所示之第三實施例之記憶體裝置類似於圖4中所示的第二 實施例之記憶體裝置。 | 用於產生比較啟用訊號COM_EN之熔絲選用電路660C包 括：NMOS電晶體N1、熔絲選用件FUSE1、鎖存單元662及 反轉器INV1。 NMOS電晶體N1回應自外部輸入之開機訊號（power-up signal)PWRUP_P而將接地電壓VSS傳遞至第一節點 NODE1。熔絲選用件FUSE1將電源電壓VDD傳遞至第一節 點NODE1。鎖存單元662鎖存自NMOS電晶體N1傳遞之接地 電壓VSS與自熔絲選用件FUSE1傳遞之電源電壓VDD之邏 • 輯值之一。反轉器INV1使鎖存單元662之輸出反轉以將經鎖 存之訊號作為比較啟用訊號COM_EN而輸出至單元比較區 塊620C。因此，若藉由熔絲選用件FUSE1啟用比較啟用訊 號COM—EN，則單元比較區塊620C僅當寫入資料D與全域資 料GIO_D具有不同資料值時輸出具有邏輯位準”高”之資 料。1313459 Comparing written data with global data, and then deactivating the amplified block when having substantially the same data value. According to one aspect of the present invention, a semiconductor port hidden device for writing data is provided, including: Global data input/output (four) line; a global latch block 'which is used to latch the global data of the global data ι/〇 line; one = extract block 'which is used for receiving and pre-fetching via the data pad The input material material is outputted as pre-extracted data during the writing operation, and the -bee delivery block is used to receive the pre-extracted data and respond to the line set by the mode register. The address and the type of the burst are outputted as the data of the writer; the control area is used to generate the amplification enable signal by comparing the global data of the written data with the global data 1/0 line, and An amplification block that receives and amplifies the written material based on the amplification enable signal and selectively transmits the amplified write data as global data to the global data I/O line. According to another aspect of the present invention, a method for driving a semiconductor memory device includes a method for receiving and amplifying written data and outputting the written data as global data to global data. An amplification/drive device on an input/output (I/O) line, the method comprising: comparing write data with global data; deactivating the amplification and driving device when the written data and the global data have the same data value; and when writing The amplification and driving device are enabled when the data has substantially different data values than the global data. [Embodiment] Hereinafter, a write circuit of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings. 112499.doc 1313459 Figure 2 is a block diagram of a write operation of a semiconductor memory device in accordance with the present invention. The semiconductor memory device according to the present invention comprises: a data input/output pad (DQ PAD) 10, a pre-fetch block 200, a data transfer block 300, a data input amplification block (DIN IOSA) 400, and a global data input/output line. 500, control block 600 and global latch block 700. The pre-fetch block 200 receives and pre-fetches input data input via the DQ PAD 10 to output the input data as pre-fetched data A0 to A3. The data transfer block 300 receives the pre-fetched data A0 to A3 output from the pre-fetch block 200 in response to the row address CA<1:0> and the burst type set by the mode register (ie, the sequential type) Or the interleave type), and the received data is output to the data input amplification block 400 as the write data D0 to D3. The data input amplification block 400 receives and amplifies the write data D0 to D3 to output the amplified data as the global data GIO_DO to GIO_D3 to the global data I/O line 500, that is, GIO_QO to GIO_Q3. The control block 600 compares the global data GIO_DO to GIO_D3 of the write data D0 to D3 and the global data I/O line 500 input to the data input amplification block 400, and further writes the data D0 to D3 and the global data GIO_DO to When the GIO_D3 has the same data value, the data input amplification block 400 is deactivated. Control block 600 includes comparison block 620 and signal generation block 640. The comparison block 620 compares the write data D0 to D3 with the global data GIO_DO to GIO_D3. The signal generation block 640 generates an amplification enable signal AMP EN for enabling or disabling the data input amplification block 400 by combining the output of the comparison block 620 with the clock signal CLK. 112499.doc 1313459 The global latch block 700 latches the global data of the global data I/O line 500. GIO_D0 through GIO-D3 thereby prevent the global data I/O line 500 from floating. Hereinafter, a method for selectively driving a data input amplification block 400 will be described in accordance with various embodiments. For ease of explanation, each of the components of the semiconductor memory device is described using a base unit (e.g., unit data input amplification block 400A, global data I/O line 500A, unit control block 600A, and unit global latch block 700A). 3 is a block diagram of a semiconductor memory device for selectively driving a data input amplification block 400 in accordance with a first embodiment of the present invention. As shown, the unit data input amplification block 400A compares the write data D with the global data GIO_D in response to the amplification enable signal AMP_EN outputted from the unit control block 600A. Cell Global Latch Block 700A Latch Unit Data The output of the amplification block 400 A is input to output the latched data to the corresponding global data I/O line 500A. The unit control block 600A includes a unit comparison block 620A and a unit signal generation block 640A. The unit comparison block 620A compares the write data D with the global data GIO_D. The unit signal generation block 640A generates an amplification enable signal AMP_EN for controlling the unit data input amplification block 400A based on the output of the unit comparison block 620A and the clock signal CLK. In particular, the cell comparison block 620A of the first embodiment of the present invention is always enabled. Referring to FIG. 3, the unit comparison block 620 A includes a mutual exclusion gate XOR1 for receiving the write data D and the global data GIO_D to perform a "mutual exclusion" or "(XOR) operation therebetween. The unit comparison block 620A outputs the data having the logic 112499.doc 10· 1313459 level "'high" only when the write data D and the global data GIO_D have different data values. In addition, the unit signal generating block 640A includes a π and "AND" gate AND1, and the execution unit compares the output of the block 620A with the ''and' operation of the clock signal CLK to output the result as the amplification enable signal AMP_EN. The unit data input amplification block 400A. 4 is a block diagram of a semiconductor memory device in accordance with a second embodiment of the present invention that selectively drives a data input amplification block 400 based on a test mode signal. p As shown, in addition to the unit comparison block 620B receiving an external test mode signal TEST_MODE input as the comparison enable signal COM_EN to be selectively enabled based on the comparison enable signal COM_EN, as shown in FIG. The memory device of the second embodiment is similar to the memory device of the first embodiment shown in FIG. The cell comparison block 620B includes a "mutually exclusive" or "XNOR" gate XNOR1 and a "NAND" gate NAND1. Mutual exclusion or gate XNOR1 receives the write data D and the global data GIO_D to perform a "mutual exclusion" or "operation" between them. The "reverse" gate NAND1 receives the "mutually exclusive" OR gate XNOR1 output and compares the enable signal COM_EN to perform an "reverse" operation therebetween. Therefore, if the compare enable signal COM_EN is enabled, the unit compare block 620B outputs the data having the logic level "high" only when the write data D and the global data GIO_D have different data values. In addition, the unit signal generating block 640B includes a AND gate AND2, and the execution unit compares the output of the block 620B with the clock signal CLK to output it to the unit data input 112499 as the amplification enable signal AMP_EN. .doc -11 - 1313459 Amplifying block 400A. Figure 5 is a block diagram of a semiconductor memory device in accordance with a third embodiment of the present invention, the semiconductor memory device selectively driving a data input amplification region based on a fuse selection Block 40. As shown, the memory device of the third embodiment shown in FIG. 5 is used except that the comparison enable signal COM_EN for the control unit comparison block 620C is generated by a fuse selection circuit 660C. The memory device of the second embodiment is similar to that shown in FIG. 4. The fuse selection circuit 660C for generating the comparison enable signal COM_EN includes: an NMOS transistor N1, a fuse option FUSE1, a latch unit 662, and a counter. INV1. The NMOS transistor N1 transmits the ground voltage VSS to the first node NODE1 in response to an externally input power-up signal PWRUP_P. The fuse option FUSE1 supplies the power supply voltage. VDD is passed to the first node NODE 1. The latch unit 662 latches one of the logic values of the ground voltage VSS transmitted from the NMOS transistor N1 and the power supply voltage VDD delivered from the fuse option FUSE1. The inverter INV1 locks The output of the memory unit 662 is inverted to output the latched signal as the compare enable signal COM_EN to the cell comparison block 620C. Therefore, if the compare enable signal COM-EN is enabled by the fuse option FUSE1, the cell comparison area Block 620C outputs data having a logic level "high" only when the write data D and the global data GIO_D have different data values.

單元比較區塊620C具有與第二實施例相同之結構且基於 比較啟用訊號COM_EN執行寫入資料D與全域資料GIO D 112499.doc -12^ 1313459 之邏輯運算。 此外，單元訊號產生區塊640C包括及閘AND3，其執行單 元比較區塊620C之輸出與時脈訊號CLK之"及"運算，以將 其作為放大啟用訊號AMP_EN而輸出至單元資料輸入放大 區塊400A。 圖6為根據本發明之第四實施例之半導體記憶體裝置的 方塊圖，該半導體記憶體裝置藉由組合測試模式訊號及熔 絲選用而選擇性地驅動資料輸入放大區塊400。 如圖所示，圖6中所示之第四實施例的記憶體裝置具有圖 3及圖4中所示之第二實施例及第三實施例之組合結構，使 得第四實施例之記憶體裝置進一步包含一比較控制單元 660D，該比較控制單元660D藉由組合測試模式訊號 TEST—MODE與熔絲選用而產生比較啟用訊號COM_EN。 用於藉由組合測試模式訊號TEST_MODE與熔絲選用而 產生比較啟用訊號COM_EN之比較控制單元660D包括： NMOS電晶體N2、熔絲選用件FUSE2、鎖存單元664、反轉 器 INV2，及"或"（OR)閘 OR1。 NMOS電晶體N2回應外部開機訊號PWRUP—P而將接地電 壓VSS傳遞至第二節點NODE2。熔絲選用件FUSE2將電源 電壓VDD傳遞至第二節點NODE2。鎖存單元664鎖存自 NMOS電晶體N2傳遞之接地電壓VSS與自熔絲選用件 FUSE2傳遞之電源電壓VDD之邏輯值之一。反轉器INV2使 鎖存單元664之輸出反轉。"或"閘OR1執行測試模式訊號 TEST—MODE與反轉器INV2之輸出的”或”運算，以將結果訊 112499.doc • 13- 1313459 號作為比較啟用訊號COM_EN而輸出至單元比較區塊 620D。因此，若藉由熔絲選用件FUSE2或測試模式訊號 TEST—MODE來啟用比較啟用訊號COM—EN，貝ij單元比較區 塊620D僅當寫入資料D與全域資料010_0具有不同資料值 時輸出具有邏輯位準"高”之資料。 單元比較區塊620D具有與第二實施例或第三實施例相同 之結構，且基於比較啟用訊號COM_EN而執行寫入資料D與 全域資料GIO_D之邏輯運算。 此外，單元訊號產生區塊640D包括及閘AND4，其執行單 元比較區塊620D之輸出與時脈訊號CLK之”及”運算，以將 其作為放大啟用訊號AMP_EN而輸出至單元資料輸入放大 區塊400A。 圖7為圖2至圖6中所示之單元資料輸入放大區塊400A之 詳細方塊圖。' 藉由放大啟用訊號AMP_EN啟用之單元資料輸入放大區 塊400A放大寫入資料D以將經放大之資料作為全域資料 GIO_D輸出至對應全域資料I/O線500A。 單元資料輸入放大區塊400A包括：差動放大區塊420、啟 用區塊4 4 0及驅動區塊4 6 0。 差動放大區塊420回應放大啟用訊號AMP_EN而感測及 放大寫入資料D以將經放大之差動訊號輸出至驅動區塊 460 ° 啟用區塊440回應放大啟用訊號AMP_EN而控制差動放 大區塊420。 112499.doc -14- 1313459 驅動區塊460驅動差動放大區塊420之經放大差動訊號並 將其輸出至對應全域資料I/O線500Α。 因此’根據本發明’控制區塊600比較寫入資料D與全域 資料GIO_D。若他們具有不同資料值，則控制區塊6〇〇啟用 具有邏輯位準”高”之放大啟用訊號AMP_EN並將其輸出至 資料輸入放大單元400 «因此’資料輸入放大單元400執行 寫入操作。另一方面，若他們具有相同值’則控制區塊6〇〇 停用具有邏輯位準”低”之放大啟用訊號amp_en並將其輸 出至資料輸入放大單元400。因此’資料輸入放大單元4〇〇 未執行寫入操作進而減少了寫入操作期間之不必要的電流 消耗。 如上文所述’在先前技術中，不論全域資料1/0線之全域 資料如何’當將資料寫入至全域資料1/0線時，資料輸入/ 輸出感測放大器始終被啟用，以致由於資料輸入/輸出感測 放大器之不必要操作而消耗額外電流。 另一方面’在本發明中’可藉由基於寫入資料與半導體 記憶體裝置内全域資料I/O線之全域資料之比較結果選擇 性地執行寫入操作而減少不必要的電流消耗。本發明對於 預提取操作已增加之裝置（諸如DDR2 SDRAM及DDR3 SDRAM)甚至更有效。 本申請案含有與在2005年9月29曰於韓國專利局申請之 韓國專利申請案第2005-91549號及第2005-132643號有關之 主題’該等專利申請案之全文以引用的方式併入本文中。 儘管已關於特定實施例描述了本發明，但熟習此項技術 112499.doc -15- 1313459 人者將明顯看出，在不偏離如以下中請專利範圍所界定之 本發明之精神及範嘴的狀況下，可進行多種變化及修正。 【圖式簡單說明】 圖1為半導體記憶體裝置之先前技術寫入操作之方塊圖； 圖2為根據本發明之半導體記憶體裝置之寫入操作的方 塊圖； 圖3為根據本發明之第一實施例用於選擇性驅動資料輸 入放大區塊之半導體記憶體裝置的方塊圖； 圖4為根據本發明之第二實施例之半導體記憶體裝置的 方塊圖’該半導體記憶體裝置基於測試模式訊號而選擇性 地驅動資料輸入放大區塊； 圖5為根據本發明之第三實施例之半導體記憶體裝置的 方塊圖’該半導體記憶體裝置基於熔絲選用而選擇性地驅 動資料輸入放大區塊； 圖6為根據本發明之第四實施例之半導體記憶體裝置的 方塊圖’該半導體記憶體裝置藉由組合一測試模式訊號與 一炫絲選用來選擇性地驅動資料輸入放大區塊；及 圖7為圖2至圖6所示之單元資料輸入放大區塊之詳細方 塊圖。 【主要元件符號說明】 10 資料輸入/輸出墊 20 領提取區塊 30 資料傳遞區塊 40 放大區塊 112499.doc • 16 - 1313459The cell comparison block 620C has the same structure as the second embodiment and performs a logical operation of writing the data D and the global data GIO D 112499.doc -12^ 1313459 based on the comparison enable signal COM_EN. In addition, the unit signal generating block 640C includes a AND gate AND3, and the execution unit compares the output of the block 620C with the "" operation of the clock signal CLK to output it to the unit data input as the amplification enable signal AMP_EN. Block 400A. Figure 6 is a block diagram of a semiconductor memory device in accordance with a fourth embodiment of the present invention, the semiconductor memory device selectively driving the data input amplification block 400 by combining test mode signals and fuse selection. As shown in the figure, the memory device of the fourth embodiment shown in FIG. 6 has the combined structure of the second embodiment and the third embodiment shown in FIGS. 3 and 4, so that the memory of the fourth embodiment The device further includes a comparison control unit 660D that generates a comparison enable signal COM_EN by combining the test mode signal TEST_MODE with the fuse selection. The comparison control unit 660D for generating the comparison enable signal COM_EN by combining the test mode signal TEST_MODE and the fuse selection comprises: an NMOS transistor N2, a fuse option FUSE2, a latch unit 664, an inverter INV2, and a " Or "(OR) gate OR1. The NMOS transistor N2 transmits the ground voltage VSS to the second node NODE2 in response to the external power-on signal PWRUP_P. The fuse option FUSE2 passes the supply voltage VDD to the second node NODE2. The latch unit 664 latches one of the logical values of the ground voltage VSS transmitted from the NMOS transistor N2 and the power supply voltage VDD delivered from the fuse option FUSE2. The inverter INV2 inverts the output of the latch unit 664. " or " gate OR1 performs the OR operation of the test mode signal TEST_MODE and the output of the inverter INV2 to output the result 112499.doc • 13-13431459 as the comparison enable signal COM_EN to the unit comparison area Block 620D. Therefore, if the compare enable signal COM_EN is enabled by the fuse option FUSE2 or the test mode signal TEST_MODE, the Bay ij unit comparison block 620D has output only when the write data D and the global data 010_0 have different data values. The logical level "high." The unit comparison block 620D has the same structure as the second embodiment or the third embodiment, and performs a logical operation of writing the data D and the global data GIO_D based on the comparison enable signal COM_EN. In addition, the unit signal generating block 640D includes a AND gate AND4, and the execution unit compares the output of the block 620D with the clock signal CLK and outputs it to the unit data input amplifying block as the amplification enable signal AMP_EN. 400A. Fig. 7 is a detailed block diagram of the unit data input amplification block 400A shown in Fig. 2 to Fig. 6. 'The unit data input amplification block 400A enabled by the amplification enable signal AMP_EN amplifies the write data D to The amplified data is output as the global data GIO_D to the corresponding global data I/O line 500A. The unit data input amplification block 400A includes: a differential amplification block 420, enabled Block 4 4 0 and drive block 4 6 0. The differential amplification block 420 senses and amplifies the write data D in response to the amplification enable signal AMP_EN to output the amplified differential signal to the drive block 460 °. The 440 responds to the amplification enable signal AMP_EN to control the differential amplification block 420. 112499.doc -14- 1313459 The drive block 460 drives the amplified differential signal of the differential amplification block 420 and outputs it to the corresponding global data I/O. Line 500. Therefore, according to the present invention, the control block 600 compares the write data D with the global data GIO_D. If they have different data values, the control block 6 enables the amplification enable signal AMP_EN with the logic level "high". And outputting it to the data input amplification unit 400 «Therefore the data input amplification unit 400 performs a write operation. On the other hand, if they have the same value', the control block 6 〇〇 disables the logic level "low" The enable signal amp_en is amplified and output to the data input amplification unit 400. Therefore, the data input amplification unit 4 does not perform a write operation and thereby reduces unnecessary current cancellation during the write operation. As mentioned above, 'in the prior art, regardless of the global data of the global data 1/0 line', when the data is written to the global data 1/0 line, the data input/output sense amplifier is always enabled, so that Additional current is consumed due to unnecessary operation of the data input/output sense amplifier. On the other hand, 'in the present invention' can be compared with the global data of the global data I/O line based on the written data and the semiconductor memory device. As a result, the write operation is selectively performed to reduce unnecessary current consumption. The present invention is even more effective for devices with increased pre-fetch operations, such as DDR2 SDRAM and DDR3 SDRAM. The present application contains the subject matter related to Korean Patent Application Nos. 2005-91549 and 2005-132643, filed on Sep. 29, 2005, to the Korean Patent Office. In this article. Although the invention has been described in terms of a particular embodiment, it will be apparent to those skilled in the art that the teachings of the teachings of the present invention are not limited by the scope of the invention as defined in the following claims. In the situation, a variety of changes and corrections are possible. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a prior art write operation of a semiconductor memory device; FIG. 2 is a block diagram of a write operation of a semiconductor memory device in accordance with the present invention; Figure 4 is a block diagram of a semiconductor memory device for selectively driving a data input amplification block; Figure 4 is a block diagram of a semiconductor memory device according to a second embodiment of the present invention. The device selectively drives the data input amplification block; FIG. 5 is a block diagram of the semiconductor memory device according to the third embodiment of the present invention. The semiconductor memory device selectively drives the data input amplification region based on fuse selection. Figure 6 is a block diagram of a semiconductor memory device in accordance with a fourth embodiment of the present invention. The semiconductor memory device selectively drives a data input amplification block by combining a test mode signal and a skein selection; And FIG. 7 is a detailed block diagram of the unit data input amplification block shown in FIGS. 2 to 6. [Main component symbol description] 10 Data input/output pad 20 Collar extraction block 30 Data transfer block 40 Enlarge block 112499.doc • 16 - 1313459

50 全域資料輸入/輸出線 200 預提取區塊 300 貢料傳遞區塊 400 貨料輸入放大區塊 400A 單元資料輸入放大區塊 420 差動放大區塊 440 啟用區塊 460 驅動區塊 500 全域資料輸入/輸出線 500A 全域資料輸入/輸出線 600 控制區塊 600A 單元控制區塊 620 比較區塊 620A 單元比較區塊 620B 單元比較區塊 620C 單元比較區塊 620D 單元比較區塊 640 訊號產生區塊 640A 單元訊號產生區塊 640B 早元訊號產生區塊 640C 單元訊號產生區塊 640D 單元訊號產生區塊 662 鎖存單元 660C 熔絲選用電路 112499.doc -17- 1313459 660D 比較控制單元 700 全域鎖存區塊 700A 單元全域鎖存區塊 112499.doc -18 ·50 Global Data Input/Output Line 200 Pre-Extraction Block 300 Dividend Transfer Block 400 Material Input Amplification Block 400A Unit Data Input Amplification Block 420 Differential Amplification Block 440 Enable Block 460 Drive Block 500 Global Data Input / Output Line 500A Global Data Input/Output Line 600 Control Block 600A Unit Control Block 620 Comparison Block 620A Unit Comparison Block 620B Unit Comparison Block 620C Unit Comparison Block 620D Unit Comparison Block 640 Signal Generation Block 640A Unit Signal generation block 640B Early element signal generation block 640C Unit signal generation block 640D Unit signal generation block 662 Latch unit 660C Fuse selection circuit 112499.doc -17- 1313459 660D Comparison control unit 700 Global latch block 700A Cell global latch block 112499.doc -18 ·

Claims (1)

13134谬9123714號專利申請案 厂一--~~一_ 中文申請專利範圍替換本(98年4月） 价年斗月1日修正本 十、申請專利範圍： 1. 一種半導體記憶體裝置之寫入電路，其包含： 一全域資料輸入/輸出（I/O)線； 一放大區塊，其用於接收及放大寫入資料，並將經放 大之寫入資料作為全域資料而傳輸至該全域資料1/0線 上；及 一控制區塊’其肢比較該寫人資料與該全域資料， 進而當該寫入資料與該全域資料具有大體相同之資料值 時停用該放大區塊。 2. 如請求項1之寫入電路，其進一步包含： 一全域鎖存區塊，其用於鎖存該全域資料以防止該全 域資料I/O線浮動； 一預提取區塊’其用於接收及預提取經由一資料墊傳 ’輸之輸人資料，並在-寫人操作期間將該輸人資料作為 經預提取之資料予以輸出；及 • 一資料傳遞區塊’其用於接收該經預提取之資料，並 回應藉由-模式暫存器設定之一行位址及一叢發類型， 而將该經接收之資料作為該寫入資料輸出至該放大區 塊。 3. 如請求項1之寫入電路，其中該控制區塊包括： 比較區塊，其用於比較該寫入資料與該全域資料；及 Λ號產生區塊’其用於藉由組合一時脈訊號與該比 較區塊之一輪出’而產生—用於控制該放大區塊之放大 啟用訊號。 112499-980409.doc 1313459 如m求項3之寫入電路，其中該比較區塊始終被啟用。 5. 如請求項4之寫入電路，其中該比較區塊包括一用於執行 "亥寫入資料與該全域資料之"互斥或"（XOR)運算之第— 邏輯閘’且該訊號產生區塊包括一用於執行該時脈訊號 與該比較區塊之該輸出之一"及”（and)運算以將該放大 啟用訊號輸出至該放大區塊的第二邏輯閘。13134谬9123714 Patent Application Factory--~~一_ Chinese Patent Application Replacement (April 1998) Price Year 1st Revision 10, Patent Application Range: 1. Write a semiconductor memory device Into the circuit, comprising: a global data input/output (I/O) line; an amplifying block for receiving and amplifying the written data, and transmitting the amplified written data as global data to the global domain The data 1/0 line; and a control block's limb compare the writer data with the global data, and then deactivate the enlarged block when the written data has substantially the same data value as the global data. 2. The write circuit of claim 1, further comprising: a global latch block for latching the global data to prevent the global data I/O line from floating; a prefetch block 'for Receiving and pre-fetching the input data of the input through a data pad, and outputting the input data as pre-extracted data during the operation of the writer; and • a data transfer block 'which is used to receive the data And pre-fetching the data, and responding to setting a row address and a burst type by the -mode register, and outputting the received data as the write data to the amplifying block. 3. The write circuit of claim 1, wherein the control block comprises: a comparison block for comparing the written data with the global data; and an apostrophe generating block 'for combining a clock The signal is generated by one of the comparison blocks and is used to control the amplification enable signal of the amplification block. 112499-980409.doc 1313459 Write circuit of item 3, where the comparison block is always enabled. 5. The write circuit of claim 4, wherein the comparison block includes a first logic gate for performing a "mutual exclusion&" (XOR) operation of the data and the global data and The signal generating block includes a second logic gate for performing the "and" operation of the clock signal and the output of the comparison block to output the amplification enable signal to the amplifying block. 6. 如凊求項3之寫入電路，其中該比較區塊係基於一比較啟 用訊號予以選擇性地啟用。 清求項6之寫入電路，其τ吻PU权一一 ” 其用於執行該寫入資料與該全域資料之 輯閘 -下、μ场雨八貝竹興琢坌域貢料之一"互斥反 或（XNOR)運算；及一第二邏輯閘，其用於執行該比較啟 2 °孔1 2 3 4 5虎與δ亥第—邏輯閘之一輸出的一"反及"(NAND)運 算且該汛號產生區塊包括一第三邏輯閘，該第三邏輯 閘用於執行該時脈訊號與該比較區塊之該第二邏輯閘之 一輸出的一 "β丨丨〜 汉運鼻，以將該經”及"運算之訊號作為該放 大啟用訊號而輪出至該放大區塊。 长員7之寫入電路，其中該比較啟用訊號係基於一自 外部輪入之測試模式訊號予以產生。 9.如請求項7之宫λ ‘ '''電路’其中該比較啟用訊號係藉由使用 一熔絲選用t路予以產生。 1 〇·如請求項9之寫入曾 # 2 尾路’其中該熔絲選用電路包括： 一熔絲選用株 ^ 3 ，其用於將一第一電壓傳遞至一第一節 4 點； 其用於回應一外部開機訊號輸入而將 5 112499-980409.doc 1313459 一第二電壓傳遞至該第—節點； 一鎖存單元，其用於鎖存該第—電壓及該第二電壓之 邏輯值之一；及 一欠轉器’其用於使該鎖存單元之一妗 卄早兀；輸出反轉，並將 Λ、、'工反轉之訊被作為該比較啟用^[妹 w山r 权敬用5孔唬輸出至該比較區 塊。 11.6. The write circuit of claim 3, wherein the comparison block is selectively enabled based on a comparison enable signal. Clearing the write circuit of item 6, the τ kiss PU right one" is used to execute the write data and the global data of the gate-down, the one field of the rain a mutually exclusive or (XNOR) operation; and a second logic gate that is used to perform the comparison of the 2° hole 1 2 3 4 5 and the δHai-logic gate one of the outputs of a "reverse &quot (NAND) operation and the nickname generation block includes a third logic gate for performing a "β output of the clock signal and one of the second logic gates of the comparison block丨丨~ Han Yun Nao, to turn the "and" operation signal as the amplification enable signal to the amplification block. The write circuit of the elder 7 is wherein the comparison enable signal is generated based on a test mode signal from an external turn-in. 9. The λ ‘ ''' circuit of claim 7 wherein the comparison enable signal is generated by using a fuse to select the t path. 1 〇·If the write of the request item 9 has a #2 tail circuit', the fuse selection circuit includes: a fuse selection system ^3 for transmitting a first voltage to a first node 4 points; And transmitting a second voltage to the first node in response to an external power-on signal input; a latch unit for latching the logic value of the first voltage and the second voltage One; and an under-rotator' is used to make one of the latch units premature; the output is inverted, and the signal of Λ, , 'work reversal is enabled as the comparison ^[妹山山r The right is output to the comparison block with 5 holes. 11. 如請求項7之寫人電路，其中該比較啟用訊號係藉由一採 用-炫絲選用及-測試模式訊號之—比較控制單元予以 產生。 12.如4求項u之寫入電路，其中該比較控制單元包括： 一熔絲選用件，其用於將—第一電壓傳遞至—第一節 點， NMOS電晶體’其用於回應-自外部輸入之開機訊號 而將一第二電壓傳遞至該第一節點； 一鎖存單元’其用於鎖存該第一電壓及該第二電壓之 邏輯值之一； 一反轉器，其用於使該鎖存單元之一輸出反轉；及 一第四邏輯閘，其用於執行該測試模式訊號與該反轉 器之一輸出的一"或"（OR)運算，並將該經"或”運算之訊號 作為該比較啟用訊號輸出至該比較區塊。 13.如請求項3之寫入電路，其中該放大區塊包括： 一差動放大區塊’其用於回應該放大啟用訊號而感測 及放大該寫入資料’以輸出經放大之差動訊號； 一啟用區塊’其用於回應該放大啟用訊號而控制該差 112499-980409.docThe writer circuit of claim 7, wherein the comparison enable signal is generated by a comparison control unit using a - ray selection and - test mode signal. 12. The write circuit of claim 4, wherein the comparison control unit comprises: a fuse option for transmitting a first voltage to the first node, and the NMOS transistor for responding to Externally inputting a power-on signal to deliver a second voltage to the first node; a latching unit 'for latching the first voltage and one of the logic values of the second voltage; an inverter for using And causing the output of one of the latch units to be inverted; and a fourth logic gate for performing a " or " (OR) operation of the test mode signal and one of the inverters, and The signal of the " or operation is output as the comparison enable signal to the comparison block. 13. The write circuit of claim 3, wherein the amplification block comprises: a differential amplification block 'which is used for response Amplifying the enable signal to sense and amplify the write data 'to output the amplified differential signal; an enable block' for returning the amplified enable signal to control the difference 112499-980409.doc 1313459 動放大區塊；及 一驅動區塊，其用於驅動該等經放大之差動訊號，並 將該等經驅動之訊號作為該全域資料而輸出至該全域資 料1/0線。 14· 一種用於寫入資料之半導體記憶體裝置，其包含 一全域資料輸入/輸出（I/O)線； 一全域鎖存區塊，其用於鎖存該全域資料ι/〇線之全域 資料； 一預提取區塊，其用於接收及預提取一經由一資料墊 傳輸之輸入資料，並在一寫入操作期間將該輸入資料作 為經預提取之資料予以輸出；及 一資料傳遞區塊，其用於接收該經預提取之資料，並 回應藉由-模式暫存器設^；之_行位址及—叢發類型， 而將該經接收之資料作為寫入資料予以輸出； -控制區塊，其用於藉由比較該寫人f料與該全域資 料而線之該全域資料，而產生一放大啟用訊號；及 -放大區塊’其基於該放大啟用訊號而接收及放大該 寫入資料’並將該經放大之寫人f料作為該全域資料選 擇性地傳輸至該全域資料1/〇線上。 15.如請求項14之半導體記憶體裝置 該全域資料具有一不同資料值時 動0 其中當該寫入資料與 該放大啟用訊號被啟 16. 如請求項15之半導體記憶體襞置 一比較區塊，其用於比較該寫 其中該控制區塊包括： 入資料與該全域資料；及 112499-980409.doc -4- 1313459 一訊號產生區塊，其用於藉由組合一時脈訊號與該比 較區塊之一輸出，而產生用於控制該放大區塊之該放大 啟用訊號。 17. 如請求項16之半導體記憶體裝置，其中該比較區塊始終 被啟用。 18. 如請求項17之半導體記憶體裝置，其中該比較區塊包括 用於執行該寫入資料與該全域資料之一"互斥或„運算 的第一邏輯閘；且該訊號產生區塊包括一用於執行該時 脈訊號與該比較區塊之該輸出之一"及，，運算以將該放大 啟用訊號輸出至該放大區塊的第二邏輯閘。 19. 如睛求項16之半導體記憶體裝置，其中該比較區塊係基 於一比較啟用訊號予以選擇性地啟用。 20. 如請求項19之半導體記憶體裝置，其中該比較區塊包 括·一第一邏輯閘，其用於執行該寫入資料與該全域資 料之一"互斥反或”運算；及一第二邏輯閘，其用於執行該 比較啟用訊號與該第一邏輯閘之一輸出的一”反及”運 算，且該訊號產生區塊包括一第三邏輯閘，該第三邏輯 閘用於執行該時脈訊號與該比較區塊之該第二邏輯閘之 一輸出的一，，及，’運算，以將該經，，及"運算之訊號作為該放 大啟用訊號輸出至該放大區塊。 21. 如凊求項20之半導體記憶體裝置，其中該比較啟用訊號 係基於一外部測試模式訊號輸入予以產生。 22. 如請求項20之半導體記憶體裝置，其中該比較啟用訊號 係藉由使用一熔絲選用電路予以產生。 112499-980409.doc 1313459 .23.如請求項22之半導體記憶體裝置，其中該熔絲選用電路 包括： 一熔絲選用件’其用於將一第一電壓傳遞至一第一節 點； — NMOS電晶體，其用於回應一外部開機訊號輸入而將 一第二電壓傳遞至該第一節點； —鎖存單元，其用於鎖存該第一電壓及該第二電壓之 邏輯值之一；及 一反轉器，其用於使該鎖存單元之一輸出反轉，並將 该經反轉之訊號作為該比較啟用訊號輸出至該比較區 塊。 24. 如請求項20之半導體記憶體裝置，其中該比較啟用訊號 係藉由一採用一熔絲選用及一測試模式訊號之一比較控 制單元予以產生。 25. 如請求項24之半導體記憶體裝置，其中該比較控制單元 包括： -熔絲選用件，其用於將一第一電壓傳遞至一第一節 點； NMOS電晶體，其用於回應一外部開機 一第二電壓傳遞至該第一節點； 一鎖存單元，其用於鎖存該第-電壓及該第二電壓 邏輯值之一； π $ $ ^轉器’其用於使該鎖存單元之-輪出反轉；及 四邏輯閘，其用於執行該測試模式訊號與該反轉 112499-980409.doc 1313459 器之一輸出的一"或’'運算，並將該經，，或"運算之訊號輸出 至該比較區塊。 26. 如請求項16之半導體記憶體裝置，其中該放大區塊包括： 一差動放大區塊，其用於回應該放大啟用訊號而感測 及放大S亥寫入資料’以輸出經放大之差動訊號； 一啟用區塊，其用於回應該放大啟用訊號而控制該差 動放大區塊；及 一驅動區塊，其用於驅動該等經放大之差動訊號，並 將該經驅動之訊號作為該全域資料輸出至該全域資料1/0 線。 27. —種用於驅動半導體記憶體裝置之方法，該半導體記憶 體裝置包括一用於接收及放大寫入資料並將全域資料輸 出至一全域資料輸入/輸出（I/O)線之放大及驅動裝置，該 方法包含： 比較該寫入資料與該全域資料； 當該寫入資料與該全域資料具有相同資料值時停用該 放大及驅動裝置；及 當該寫入資料之資料值與該全域資料之資料值彼此大 體不同時啟用該放大及驅動裝置。 28. 如請求項27之用於驅動半導體記憶體裝置之方法，其進 一步包含： 預提取經由一資料墊傳遞之輸入資料，以在一寫入操 作期間輸出經預提取之資料；及 接收該經預提取之資料，並回應藉由一模式暫存器設 112499-980409.doc 1313459 定之一行位址及一叢發類型而將經接收之資料作為該寫 入資料予以輸出。 29. 如睛求項27之用於驅動半導體記憶體裝置之方法，其中 基於一比較啟用訊號而執行該寫入資料與該全域資料之 該比較。 30. 如請求項29之用於驅動半導體記憶體裝置之方法，其中 以一測試模式啟動該比較啟用訊號。 31·如請求項29之用於驅動半導體記憶體裝置之方法，其中 根據一熔絲選用而啟動該比較啟用訊號。 32.如請求項29之用於驅動半導體記憶體裝置之方法，其中 根據一熔絲選用以一測試模式啟動該比較啟用訊號。a 1313459 dynamic amplification block; and a drive block for driving the amplified differential signals, and outputting the driven signals as the global data to the global data 1/0 line. 14. A semiconductor memory device for writing data, comprising a global data input/output (I/O) line; a global latch block for latching the global data of the global data ι/〇 line Data; a pre-fetching block for receiving and pre-fetching input data transmitted via a data pad, and outputting the input data as pre-fetched data during a writing operation; and a data transfer area a block for receiving the pre-fetched data, and responding to the -type address and the burst type by the -mode register, and outputting the received data as write data; a control block for generating an amplification enable signal by comparing the global data of the write material and the global data; and - amplifying the block to receive and amplify based on the amplification enable signal The write data 'and the amplified writes are selectively transmitted as the global data to the global data 1/〇 line. 15. The semiconductor memory device of claim 14 wherein the global data has a different data value, wherein the write data and the amplification enable signal are enabled. 16. The semiconductor memory device of claim 15 is compared. a block for comparing the writes wherein the control block includes: an entry data and the global data; and 112499-980409.doc -4- 1313459 a signal generation block for comparing the clock signal by the comparison One of the blocks is output, and the amplification enable signal for controlling the amplification block is generated. 17. The semiconductor memory device of claim 16, wherein the comparison block is always enabled. 18. The semiconductor memory device of claim 17, wherein the comparison block comprises a first logic gate for performing a "mutual exclusion" operation of the write data and the global data; and the signal generation block Included is a second logic gate for performing the clock signal and the output of the comparison block " and, to output the amplification enable signal to the amplification block. The semiconductor memory device, wherein the comparison block is selectively enabled based on a comparison enable signal. 20. The semiconductor memory device of claim 19, wherein the comparison block comprises a first logic gate, Executing the one of the write data and the global data " mutually exclusive OR operation; and a second logic gate for performing a "reverse" of the output of the comparison enable signal and the first logic gate "Operation, and the signal generating block includes a third logic gate for performing one of the output of the clock signal and the second logic gate of the comparison block, and, 'operation To the passage, And the "computation signal is output to the amplification block as the amplification enable signal. 21. The semiconductor memory device of claim 20, wherein the comparison enable signal is generated based on an external test mode signal input. 22. The semiconductor memory device of claim 20, wherein the comparison enable signal is generated by using a fuse selection circuit. The semiconductor memory device of claim 22, wherein the fuse selection circuit comprises: a fuse option 'for transmitting a first voltage to a first node; - NMOS a transistor for transmitting a second voltage to the first node in response to an external power-on signal input; a latch unit for latching one of a logic value of the first voltage and the second voltage; And an inverter for inverting an output of the latch unit and outputting the inverted signal as the comparison enable signal to the comparison block. 24. The semiconductor memory device of claim 20, wherein the comparison enable signal is generated by a comparison control unit using a fuse selection and a test mode signal. 25. The semiconductor memory device of claim 24, wherein the comparison control unit comprises: - a fuse option for transmitting a first voltage to a first node; and an NMOS transistor for responding to an external Turning on a second voltage to the first node; a latch unit for latching one of the first voltage and the second voltage logic value; π $ $ ^ 旋 ' it is used to make the latch a unit-inversion reversal; and a four-logic gate for performing a "or' operation on the output of the test mode signal and the inversion 112499-980409.doc 1313459, and the Or the signal of the operation is output to the comparison block. 26. The semiconductor memory device of claim 16, wherein the amplifying block comprises: a differential amplifying block for retrieving the amplified enable signal and sensing and amplifying the S-writing data to output the amplified a differential signal; an enable block for controlling the differential amplification block to be amplified by the enable signal; and a drive block for driving the amplified differential signals and driving the same The signal is output as the global data to the global data 1/0 line. 27. A method for driving a semiconductor memory device, the semiconductor memory device comprising an amplification for receiving and amplifying written data and outputting global data to a global data input/output (I/O) line a driving device, the method comprising: comparing the written data with the global data; deactivating the amplifying and driving device when the written data has the same data value as the global data; and when the data value of the written data is The amplification and driving device are enabled when the data values of the global data are substantially different from each other. 28. The method of claim 27 for driving a semiconductor memory device, further comprising: pre-fetching input data communicated via a data pad to output pre-fetched data during a write operation; and receiving the Pre-fetching the data and responding to outputting the received data as the write data by a mode register setting 112499-980409.doc 1313459 to define a row address and a burst type. 29. The method of claim 27, wherein the comparing of the write data to the global data is performed based on a compare enable signal. 30. The method of claim 29 for driving a semiconductor memory device, wherein the compare enable signal is initiated in a test mode. 31. The method of claim 29 for driving a semiconductor memory device, wherein the compare enable signal is enabled based on a fuse selection. 32. The method of claim 29, wherein the compare enable signal is activated in a test mode in accordance with a fuse. 112499-980409.doc112499-980409.doc
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