TW200713272A - Write circuit of memory device - Google Patents

Write circuit of memory device

Info

Publication number
TW200713272A
TW200713272A TW095123714A TW95123714A TW200713272A TW 200713272 A TW200713272 A TW 200713272A TW 095123714 A TW095123714 A TW 095123714A TW 95123714 A TW95123714 A TW 95123714A TW 200713272 A TW200713272 A TW 200713272A
Authority
TW
Taiwan
Prior art keywords
data
memory device
write
write circuit
global
Prior art date
Application number
TW095123714A
Other languages
Chinese (zh)
Other versions
TWI313459B (en
Inventor
Beom-Ju Shin
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200713272A publication Critical patent/TW200713272A/en
Application granted granted Critical
Publication of TWI313459B publication Critical patent/TWI313459B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

A write circuit of a semiconductor memory device includes a global data input/output (I/O) line; an amplifying block for receiving and amplifying write data and transmitting the amplified write data as global data onto the global data I/O line; and a control block for comparing the write data with the global data to thereby disable the amplifying block when the write data and the global data have substantially the same data value.
TW095123714A 2005-09-29 2006-06-30 Write circuit of memory device and method for driving the same TWI313459B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20050091549 2005-09-29
KR1020050132643A KR100743995B1 (en) 2005-09-29 2005-12-28 Write circuit of memory device

Publications (2)

Publication Number Publication Date
TW200713272A true TW200713272A (en) 2007-04-01
TWI313459B TWI313459B (en) 2009-08-11

Family

ID=37959232

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095123714A TWI313459B (en) 2005-09-29 2006-06-30 Write circuit of memory device and method for driving the same

Country Status (3)

Country Link
KR (1) KR100743995B1 (en)
CN (1) CN100568379C (en)
TW (1) TWI313459B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102280138B (en) * 2011-03-31 2013-07-24 西安华芯半导体有限公司 Storage method with cumulative write-in characteristic, storage device and storage system
US9710403B2 (en) * 2011-11-30 2017-07-18 Intel Corporation Power saving method and apparatus for first in first out (FIFO) memories
KR20130123934A (en) 2012-05-04 2013-11-13 에스케이하이닉스 주식회사 Input output sense amplifier and semiconductor apparatus including the same
KR20140025012A (en) * 2012-08-20 2014-03-04 에스케이하이닉스 주식회사 Semiconductor memory device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100605600B1 (en) * 2004-07-27 2006-07-28 주식회사 하이닉스반도체 Semiconductor memory device

Also Published As

Publication number Publication date
CN1941164A (en) 2007-04-04
KR20070036569A (en) 2007-04-03
KR100743995B1 (en) 2007-08-01
TWI313459B (en) 2009-08-11
CN100568379C (en) 2009-12-09

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees