JP2000228085A - Output circuit and synchronous dram using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the effective widthness of output data at a high frequency by making a first level converting circuit converting the power source level of data from a HIGH output side and a second level converting circuit the power source level of data from a LOW output side among data which are outputted by a latch circuit have the same constitution to reduce variation in output time. SOLUTION: When a latch circuit 50 input two output data, an output permitting signal, an output clock signal and an output clock bar signal, it latchingly outputs the inputted data. Level converting circuits 60a, 60b respectively convert power source levels of data of the HIGH output side and of data of the LOW output side among data which are outputted by the circuit 50 to output them to an output transistor part 70. Thus, a time when the piece of HIGH data is outputted and a time when the piece of LOW data outputted can be equalized by making the constitution of the level converting circuit 60b of the LOW output side to be the same as that of the level converting circuit 60a of the HIGH output side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit,
In particular, the present invention relates to an output circuit using a level conversion circuit and a synchronous DRAM using the output circuit.

[0002]

2. Description of the Related Art Conventionally, there is a synchronous DRAM as one of the semiconductor memory devices which operates based on a clock signal output from a memory controller.

The operation of a general double data rate synchronous DRAM will be described below.

FIG. 4 shows a synchronous DR of a double data rate.
It is a figure showing an example of 1 composition of AM.

First, the operation at the time of inputting the ACTIVATE command will be described.

FIG. 5 is a diagram for explaining the operation of the synchronous DRAM of the double data rate shown in FIG. 4 when an ACTIVATE command is input.

As shown in FIG. 5, at time t0, an ACTIVATE command is applied to terminal group 111 to terminal 139.
When input during the input setup time and input hold time determined for the clock input to
The input ACTIVATE command is input to the input circuit 11
2 and is input to a latch circuit 113 composed of a D-type flip-flop circuit. Where ACT
The IVATE command indicates that the CS bar (hereinafter, referred to as CSB) and the RAS bar (hereinafter, referred to as RASB) are LO
W level, CAS bar (hereinafter referred to as CASB) and WE bar (hereinafter referred to as WEB) are HIGH
This is a row address selection command which is a level.

At time t0, the clock input to terminal 139 and the clock bar input to terminal 140 are input to internal clock signal generation circuit 142 via input circuit 141, and internal clock signal generation circuit 142 The internal clock signal 143 is generated and output based on the input clock and clock bar.

The internal clock signal 143 output from the internal clock signal generation circuit 142
113, a write control circuit 125 and a read control circuit 126.

At time t0, the clock input to terminal 139 and the clock bar input to terminal 140 are also input to internal clock bar signal generation circuit 145 via input circuit 144, and are output to internal clock bar signal generation circuit. At 145, an internal clock bar signal 146 is generated and output based on the input clock and clock bar, and input to the read control circuit 126.

ACTIVAT input to terminal group 111
The E command is latched in the latch circuit 113 by the internal clock signal 143 output from the internal clock signal generation circuit 142, and the latched ACTIVA
The TE command signal 114 is supplied to the row address control circuit 118
Is input to

Thereafter, the row address control circuit 118 outputs a row address permission signal 119 based on the input ACTIVATE signal 114.

At time t0, when a row address input (X) is input to the terminal group 101 for an input setup time and an input hold time determined with respect to the clock input to the terminal 139, the input is made. The row address input (X) is input to a latch circuit 103 including a D-type flip-flop circuit via an input circuit 102,
The latch circuit 103 is latched by the internal clock signal 143 output from the internal clock signal generation circuit 142.

The row address (X) latched by the latch circuit 103 is then input to a row decoder 108 via a row address buffer 107, and the row decoder 108 corresponds to the input row address (X). The row selection line 109 is selected.

Thereafter, in the row address control circuit 118, the amplification start signal 122 is activated after a predetermined time in order to activate the sense amplifier 123, so that the data stored in the memory cell array 110 is restored. Amplified.

Next, the operation at the time of data reading will be described.

FIG. 6 is a diagram for explaining an operation at the time of data reading of the synchronous DRAM of the double data rate shown in FIG.

First, at time t0, the terminal group 111 receives a READ command, the terminal group 101 receives an address (Y1), and the input setup time and input hold time determined with respect to the clock input to the terminal 139. During this time, the input READ command is decoded via the input circuit 112 and input to the latch circuit 113. Here, the READ command is C
SB and CASB are LOW level, and RASB and WE
B is a read operation command with a HIGH level.

Then, in the latch circuit 113, the latched REA is latched by the internal clock signal 143 output from the internal clock signal generation circuit 142.
The D command signal 117 is input to the column address control circuit 120 and also to the read control circuit 126.

In the column address control circuit 120, a column address enable signal 121 is output based on the input READ command signal 117, and the column address buffer 1
04 is input.

The address (Y1) input to the terminal group 101 is input to the latch circuit 103 composed of a D-type flip-flop circuit via the input circuit 102, and the latch circuit 103 outputs the address (Y1) from the internal clock signal generation circuit 142. Latched by the internal clock signal 143.

The address (Y1) latched by the latch circuit 103 is input to a column decoder 105 via a column address buffer 104, and the column decoder 105 selects a column selection line 106 corresponding to the input address. .

Also, a double data rate synchronous DRA
In M, since it is necessary to output two bits of data in one cycle, the column selection line corresponding to the next address (Y2) is simultaneously selected. This means that the memory cell to be read has been selected.

Next, the data read from the memory cell array 110 via the sense amplifier 123 is stored in two sets of I
The internal clock generated by the internal clock signal generation circuit 142 corresponding to the clock input to the terminal 139 at the time t0 in the data amplifier 133 is input to the two data amplifiers 133 via the / O line pair 124. Signal 1
The signal is amplified by the data amplifier control signal 127 generated by the read control circuit 126 based on the signal 43 and output.

Next, in latch circuit 134 composed of a D-type flip-flop circuit, based on internal clock signal 143 generated by internal clock signal generating circuit 142 in response to the clock input to terminal 139 at time t1. The two output data output from the data amplifier 133 are latched and output by the output data latch signal 128 generated by the read control circuit 126, and the output enable signal 129 and the output clock signal 130 generated by the read control circuit 126 are output. And output clock bar signal 131, and sequentially output to terminal 136 via output circuit 135.

At the same time, the DQ strobe signal output circuit 151 generates a DQ strobe signal and outputs it to the terminal 147.

FIG. 7 is a diagram showing signal waveforms in the output circuit 135 shown in FIG. 4, and shows operation waveforms when the burst length (bit length for simultaneously executing reading and writing) is 8 bits.

As shown in FIG. 7, in a synchronous DRAM of a double data rate, two bits of data are output in one cycle, so that the next bit read operation is executed and processed in parallel every cycle. You. That is, 3,
The fourth bit (Y3, Y4) is time t2 to time t5, the sixth bit (Y5, Y6) is time t2 to time t3, and the seventh bit (Y7, Y8) is time t3 to time t4. Be executed.

The above-described read operation is called "CAS LATENCY 2" because data is output at the second clock after the READ command is input.

Next, the operation at the time of data writing will be described.

FIG. 8 is a diagram for explaining an operation at the time of data writing of the synchronous DRAM of the double data rate shown in FIG.

First, at time t0, a WRITE command is input from the terminal group 111, write data (DQ) is input from the terminal 136, and an address (Y1) is input from the terminal 101 to the clock input to the terminal 139. The input is made during an input setup time and an input hold time which are determined for the same, and a DQ strobe signal (DQS) is input from a terminal 147. here,
The WRITE command is a write operation command in which CSB, CASB, and WEB are at a low level, and RASB is at a high level.

The WRITE command input to the terminal group 111 is decoded via the input circuit 112 and input to the latch circuit 113.

Then, in latch circuit 113, the WRITE command is latched by internal clock signal 143 output from internal clock signal generation circuit 142 in response to the clock input to terminal 139 at time t0, and WRITE command signal 116 Is output to the column address control circuit 120 and the write control circuit 125.

In the column address control circuit 120, a column address permission signal 121 is output based on the input WRITE command signal 116, and is input to the column address buffer 104.

The address (Y1) input to the terminal 101 is supplied to the latch circuit 1 composed of a D-type flip-flop circuit via the input circuit 102 in the same manner as at the time of reading.
03 and is latched by the internal clock signal 143 output from the internal clock signal generation circuit 142.

The latched address (Y1) is input to a column decoder 105 via a column address buffer 104, and the column decoder 105 selects a column selection line 106 corresponding to the input address and the next address. You.

The write data (DQ) inputted to the terminal 136 is inputted to a latch circuit 138 comprising a D-type flip-flop circuit via an input circuit 137.
In the latch circuit 138, the D signal input to the terminal 147 corresponding to the clock input to the terminal 139 at time t0.
The rising edge and falling edge of the internal strobe signal 150 generated by the internal strobe signal generation circuit 149 based on the Q strobe signal (DQS) are latched for two bits and input to the write control circuit 125.

Further, the two write data input to the write control circuit 125 are supplied to the terminal 139 at time t0.
Of the memory cell array 110 via two sets of I / O line pairs 124 and two sense amplifiers 123 by the falling of the internal clock signal 143 output from the internal clock generation circuit 142 in response to the clock input to The data is written to the corresponding 2-bit memory cell.

Next, the operation when the PRECHRAGE command is input will be described.

FIG. 9 is a diagram for explaining the operation of the synchronous DRAM of the double data rate shown in FIG. 4 when a PRECHRAGE command is input.

First, at time t0, when a PRECHRAGE command is input to the terminal group 111 for an input setup time and an input hold time determined with respect to the clock input to the terminal 139, the terminal group 11
The PRECHRAGE command input to 1 is decoded via the input circuit 112 and input to the latch circuit 113 including a D-type flip-flop circuit. Where P
The RECHAGE command includes CSB, RASB and WE
This is a row address non-selection command in which B is at a LOW level and CASB is at a HIGH level.

PRECH input to the latch circuit 113
The RAGE command is latched in the latch circuit 113 by the internal clock signal 143 output from the internal clock signal generation circuit 142, and the latched PREC
The HRAGE command signal 115 is input to the row address control circuit 118.

Then, in the row address control circuit 118, the row address permission signal 119 is reset, and thereafter, the row selection line 109 and the amplification start signal 22 of the sense amplifier 123 are also reset.

Next, the output circuit during the read operation will be described in detail.

FIG. 10 is a diagram showing a configuration example of a level conversion circuit used in the output circuit 135 shown in FIG.

As shown in FIG. 10, the level conversion circuit of this embodiment has two P-channel MOS transistors 30.
1, 302 and two N-channel MOS transistors 3
03, 304 and an inverter 305.

FIG. 11 is a timing chart for explaining the operation of the level conversion circuit shown in FIG.

As shown in FIG. 11, first, at time t0, when the input goes from the ground level to the power supply level (1), the output contact b of the inverter 305 goes to the ground level, whereby the N-channel MOS transistor 304
Is turned off. At the same time, an N-channel MOS
The transistor 303 is turned on, whereby the contact a is set to the ground level. As a result, a waveform of the power supply level (2) is output.

Next, at time t1, when the input changes from the power supply level (1) to the ground level, the output contact b of the inverter 305 using the power supply level (1) becomes the power supply level (1), whereby N-channel MOS transistor 304 is turned on. At the same time, since the N-channel MOS transistor 303 is in the OFF state, the contact a goes to the power supply level (2).

As a result, a ground level waveform is output at the output.

Next, the operation of the output circuit will be described.

FIG. 12 is a diagram showing a configuration example of the output circuit 135 shown in FIG.

First, when a READ command is input at time t0, as described above, the output circuit 135
Two output data output from the latch circuit 134;
Output enable signal 1 generated by read control circuit 126
29, an output clock signal 130, and an output clock bar signal 131 are input.

The output clock signal 130 is a signal synchronized with an externally input clock, and the output clock bar signal 131 is a signal synchronized with an externally input clock bar.

The output permission signal 129 is a signal for setting the output transistor to the OFF state and setting the output to high impedance when inactive.

As shown in FIG. 12, two output data output from the latch circuit 134 are
419, NOR gates 402 and 420 and NAND gates 403 and 421 perform logical operation,
It is input to a CMOS transfer composed of S transistors 404 to 408 and 423 to 426.

Here, in the logical operation, the difference between NAND gates 403 and 421 and NOR gates 402 and 420 is that both output transistors 418 and 430 are set to OFF when output enable signal 129 is inactive. That's why.

The CMOS transistors 404 to 40
A latch circuit is constituted by a CMOS transfer comprising 8,423 to 426 and inverters 409, 410, 427, 428, and the clock signal of the latch circuit is two of the above-mentioned output clock signal and output clock bar signal. There are types, and the logic is such that data is output in order.

That is, in FIG. 7, output data 1 and output data 2 are simultaneously generated for one cycle, but the output clock signal, the output clock bar signal and T alternately become the power supply level, and output data 1 and output data 2 are output. Data 2 can be alternately latched in one cycle.

Normally, in a synchronous DRAM, a power supply for output (VCCQ in the figure) different from the power supply of the internal circuit is used on the pull-up side of the output transistor, so that the power supply level is provided on the high output side. Requires a level conversion circuit for converting.

This is because when the power supply level of the internal circuit is lower than the output power supply level by the threshold value of the P-channel MOS transistor, the P-channel MOS transistor 418 on the HIGH output side is set to the OFF state. This is to prevent a through current from flowing between the N-channel MOS transistor 430 and the N-channel MOS transistor 430.

Therefore, the data on the HIGH output side is
It is input to a level conversion circuit composed of P-channel MOS transistors 411 and 412, N-channel MOS transistors 413 and 414, and an inverter 415, and then is supplied to a P-channel MOS transistor 416 and an N-channel MOS transistor 417 through a buffer. The MOS transistor 418 is activated or deactivated.

The data on the LOW output side activates or deactivates the N-channel MOS transistor 430 via the buffer including the inverter 429.

As a result, as shown in FIG. 7, two bits can be sequentially output in one cycle at the DQ terminal.

[0066]

However, in the conventional output circuit as described above, since the HIGH output side and the LOW output side have different circuit configurations, the time during which the HIGH level signal is output and the LOW signal are output. The variation in the time taken is large. This becomes even more pronounced if the process fluctuates.

Here, a double data rate synchronous DRA
In M, since two bits of data are output in one cycle, the effective width of the output data is small at a high frequency of 100 MHz or more.

Therefore, if the output data time varies, there is a problem that the operation margin of the system using the double data rate synchronous DRAM is deteriorated.
RAM cannot be used at high frequencies.

The present invention has been made in view of the above-mentioned problems of the prior art, and has been made to reduce the variation in output time and to secure the effective width of output data at a high frequency. It is an object of the present invention to provide an output circuit that can perform the above.

[0070]

In order to achieve the above object, the present invention provides a latch circuit for latching input HIGH and LOW output data, respectively, and a latch circuit for latching data output from the latch circuit. And a first level conversion circuit for converting the power supply level of the data on the HIGH output side, and L of the data output from the latch circuit.
A second level conversion circuit for converting a power level of data on the OW output side, and an output for outputting data converted by the first level conversion circuit and data converted by the second level conversion circuit An output circuit having a transistor section, wherein the first level conversion circuit and the second level conversion circuit
Is characterized by having the same configuration as that of the level conversion circuit.

The first level conversion circuit and the second level conversion circuit each include an inverter for inverting and outputting data output from the latch circuit, and a gate for outputting data output from the latch circuit. , A first N-channel MOS transistor having a drain grounded, a first potential VCCQ applied to a source, and a first P-channel MOS transistor having a drain connected to the source of the first N-channel MOS transistor. A channel MOS transistor and a second P-channel MOS in which a predetermined potential VCCQ is applied to the source and a gate is connected to the drain of the first N-channel MOS transistor and the source of the first P-channel MOS transistor
A transistor and a signal output from the inverter are input to a gate, and a source is connected to the first P-channel MO.
The gate of the S transistor and the second P-channel MO
It has a second N-channel MOS transistor to which the drain of the S transistor is connected and whose drain is grounded.

The first level conversion circuit and the second level conversion circuit each include an inverter for inverting and outputting data output from the latch circuit, and a gate for outputting data output from the latch circuit. , A first N-channel MOS transistor having a drain grounded, a first potential VCCQ applied to a source, and a first P-channel MOS transistor having a drain connected to the source of the first N-channel MOS transistor. A channel MOS transistor and a second P-channel MOS in which a predetermined potential VCCQ is applied to the source and a gate is connected to the drain of the first N-channel MOS transistor and the source of the first P-channel MOS transistor
A transistor and a signal output from the inverter are input to a gate, and a source is connected to the first P-channel MO.
The gate of the S transistor and the second P-channel MO
A signal output from the latch circuit is input to the gate of a second N-channel MOS transistor to which the drain of the S transistor is connected and the drain of which is grounded, and a predetermined potential VCCQ is applied to the source. A gate of the first P-channel MOS transistor;
A third N-channel MOS transistor to which a drain of the second P-channel MOS transistor 2 and a source of the second N-channel MOS transistor are connected;
A signal output from the inverter is input to a gate, a predetermined potential VCCQ is applied to a source,
The semiconductor device is characterized by having a fourth N-channel MOS transistor having a drain connected to a drain of the first P-channel MOS transistor and a gate of the second P-channel MOS transistor.

Further, the latch circuit latches and outputs the HIGH output data of the input data, and the first latch unit latches and outputs the LOW output data of the input data. And two latch portions.

Further, each of the latch circuit and the transistor section has a buffer.

A synchronous DRAM is characterized in that the output circuit is used.

(Operation) In the present invention configured as described above, of the data output from the latch circuit, H
A first level conversion circuit for converting the power supply level of the data on the IGH output side, and a second level conversion circuit for converting the power supply level of the data on the LOW output side among the data output from the latch circuit.
Has the same configuration as the level conversion circuit of FIG.
The time at which the data is output is equal to the time at which the LOW data is output, thereby securing the effective width of the output data at a high frequency.

[0077]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the output circuit of the present invention, which is applied to the double data rate synchronous DRAM shown in FIG.

In the present embodiment, as shown in FIG.
A latch circuit 50 for latching and outputting the data on the HIGH output side and the data on the LOW output side, a first level conversion circuit 60a for converting the power supply level of the data on the HIGH output side among the data output from the latch circuit 50, A second level conversion circuit 6 for converting the power supply level of the data on the LOW output side of the data output from the latch circuit 50
0b and an output transistor unit 70 that outputs data converted by the first level conversion circuit 60a and data converted by the second level conversion circuit 60b.

FIG. 2 is a circuit diagram showing a specific configuration example of the output circuit shown in FIG.

As shown in FIG. 2, the latch circuit 50 according to the present embodiment includes a first latch section 51 for latching and outputting the HIGH output data of input data, and a LOW output of input data. And a second latch section 52 for latching and outputting data on the output side. The first latch section 51 receives an output permission signal, and inverts the output permission signal and outputs the inverted signal. And a signal output from the inverter 1 are input, a NOR gate 2 that outputs a signal obtained by inverting the logical sum of the two, a HIGH output side data and an output enable signal are input, and the logical product of the two is input. N that outputs a signal obtained by inverting
An AND gate 3, an inverter 4 to which an output clock signal is input, inverts the output clock signal, and outputs the inverted output clock signal;
The signal output from the inverter 4 is input to the gate,
A P-channel MOS transistor 5 to which the signal output from the NOR gate 2 is input to the source; an N-channel MOS transistor 6 to which the output clock signal is input to the gate and the signal output from the NOR gate 2 to the source , A signal output from inverter 4 is input to a gate, a signal output from NAND gate 3 is input to a source, P-channel MOS transistor 7, and an output clock signal is input to a gate and output from NAND gate 3 N-channel MO where the input signal is input to the source
S transistor 8 and P channel MOS transistor 5
An inverter 9 for inverting and outputting a signal output from the drain of the N-channel MOS transistor 6, and an inverter 10 for inverting and outputting the signal output from the inverter 9, and a second latch unit 5
2, an inverter 19 to which an output permission signal is input and which inverts the output permission signal and outputs the inverted signal; a data on the LOW output side and a signal output from the inverter 19;
A NOR gate 20 that outputs a signal obtained by inverting the logical sum of the two, NAN that receives the data on the LOW output side and the output enable signal and outputs a signal obtained by inverting the logical product of the two
D gate 21, an output clock bar signal is input, an inverter 22 inverts and outputs the output clock bar signal, and a signal output from the inverter 22 is input to the gate, and a signal output from the NOR gate 20 is A P-channel MOS transistor 23 input to the source,
An output clock bar signal is input to the gate, a signal output from the NOR gate 20 is input to the source, an N-channel MOS transistor 24, and a signal output from the inverter 22 is input to the gate.
P-channel M in which the signal output from is input to the source
An OS transistor 25 and an N-channel MOS transistor 2 to which an output clock bar signal is input to the gate and a signal output from the NAND gate 21 is input to the source
6, an inverter 27 for inverting and outputting a signal output from the drains of the P-channel MOS transistors 7 and 25 and the N-channel MOS transistors 8 and 26, and an inverter 28 for inverting and outputting the signal output from the inverter 27 It is composed of Note that the signals output from the drains of the P-channel MOS transistor 23 and the N-channel MOS transistor 24 are also input to the inverter 9. The signal output from the inverter 10 is input to the inverter 9, and the signal output from the inverter 28 is input to the inverter 27.

The level conversion circuit 60 of the present embodiment
As shown in FIG. 2A, among the data output from the latch circuit 50, the data on the HIGH output side is input, the inverter 15 inverts the data and outputs the inverted data, and the data a of the data output from the latch circuit 50. Among them, the data on the HIGH output side is input to the gate, the first N-channel MOS transistor 13 whose drain is grounded, the predetermined potential VCCQ is applied to the source, and the drain is connected to the source of the N-channel MOS transistor 13. A connected first P-channel MOS transistor 11 and a second P-channel MOS transistor 11 having a predetermined potential VCCQ applied to the source and a gate connected to the drain of the N-channel MOS transistor 11 and the source of the P-channel MOS transistor 13.
The signal output from the channel MOS transistor 12 and the inverter 15 is input to the gate, and the gate of the P channel MOS transistor 11 and the P channel M
A second N-channel MOS transistor 14 having a drain connected to the OS transistor 12 and a grounded drain
It is composed of

The level conversion circuit 60 according to the present embodiment
As shown in FIG. 2B, among the data output from the latch circuit 50, the data on the LOW output side is input, and the inverter 33 inverts the data and outputs the inverted data. Among them, the first N-channel MOS transistor 31 whose data on the LOW output side is input to the gate, the drain of which is grounded, and the predetermined potential VCCQ are applied to the source, and the drain is connected to the source of the N-channel MOS transistor 31. The connected first P-channel MOS transistor 29 and a predetermined potential VCCQ are applied to the source, and the drain of the N-channel MOS transistor 29 and the P-channel
A signal output from the second P-channel MOS transistor 30 to which the source of the S transistor 31 is connected, and a signal output from the inverter 33 are input to the gate.
A second N-channel MOS transistor 32 is connected to the drain of the transistor 30 and has the drain grounded.

As shown in FIG. 2, the output transistor section 70 of the present embodiment has a P-channel MOS in which a signal output from the level conversion circuit 60a is input to the gate, and a predetermined potential VCCQ is applied to the source. The transistor 16 and a signal output from the level conversion circuit 60a are input to the gate, the source is connected to the drain of the P-channel MOS transistor 16, and the drain is grounded.
A P-channel MOS transistor 18 connected to the drain of the channel MOS transistor 16 and the source of the N-channel MOS transistor 17 and having a source applied with a predetermined potential VCCQ, and a signal output from the level conversion circuit 60b input to the gate. A signal output from the P-channel MOS transistor 34 to which a predetermined potential VCCQ is applied to the source and a signal output from the level conversion circuit 60b are input to the gate.
An N-channel MOS transistor 35 connected to the drain of the transistor 34, the drain of which is grounded;
Connected to the source of the channel MOS transistor 35,
The source is connected to the drain of the P-channel MOS transistor 18 and the N-channel MOS transistor 36 whose drain is grounded.
The drain of the S transistor 18 and the source of the N-channel MOS transistor 36 are connected to the output terminal 80.

The operation when the output circuit configured as described above is applied to the double data rate synchronous DRAM shown in FIG. 4 will be described below.

When a READ command is input to the terminal group 111 (see FIG. 4), two output data are output to the output circuit, an output permission signal 124 generated by the read control circuit 125 (see FIG. 4), An output clock signal 130;
The output clock bar signal 131 is input.

First, the input data is latched and output by the latch circuit 50. The operation of the latch circuit 50 is the same as that of the conventional example shown in FIG.

The data on the HIGH output side of the data output from the latch circuit 50 is input to the level conversion circuit 60a, the power supply level is converted, and output to the output transistor unit 70.

Thereafter, in the output transistor section 70, the input data is transmitted to the P-channel MOS transistor 18 via the buffer composed of the P-channel MOS transistor 16 and the N-channel MOS transistor 17, and activates the P-channel MOS transistor 18. Or deactivate.

The data on the LOW output side of the data output from the latch circuit 50 is
b, the power supply level is converted and output to the output transistor unit 70.

Thereafter, in output transistor section 70, the input data is transmitted to P-channel MOS transistor 36 via a buffer comprising P-channel MOS transistor 34 and N-channel MOS transistor 35, and activates N-channel MOS transistor 36. Or deactivate.

As described above, the circuit on the LOW output side is set to the HIG
By using the same configuration as the circuit on the H output side, HIG
The time when the H data is output can be made equal to the time when the LOW data is output.

Note that, compared to the conventional example shown in FIG.
The speed difference due to the process variation can be made equal between the HIGH side and the LOW side as compared with the case where the delay time is adjusted by adding an inverter to the path on the OW output side.

FIG. 3 is a circuit diagram showing another specific example of the configuration of the output circuit shown in FIG.

The circuit shown in FIG. 3 differs from the circuit shown in FIG. 2 in that the signal output from the inverter 9 is input to the gate in the level conversion circuit 60a, and the predetermined potential VCCQ is applied to the source. A third N-channel MOS transistor having the drain connected to the gate of the P-channel MOS transistor 11, the drain of the P-channel MOS transistor 12, and the source of the N-channel MOS transistor 14.
The signal output from the S transistor 37 and the inverter 15 is input to the gate, and a predetermined potential VCCQ
Is applied to the source and the drain is connected to the drain of the P-channel MOS transistor 11 and the gate of the P-channel MOS transistor 12.
A transistor 38 is provided. Further, in the level conversion circuit 60b, a signal output from the inverter 27 is input to the gate, a predetermined potential VCCQ is applied to the source, and the gate of the P-channel MOS transistor 29 is connected to the drain. , A third N-channel MOS transistor 39 to which the drain of P-channel MOS transistor 30 and the source of N-channel MOS transistor 32 are connected
And a signal output from the inverter 33 is input to the gate, a predetermined potential VCCQ is applied to the source, and the drain of the P-channel MOS transistor 29 and the gate of the P-channel MOS transistor 30 are connected to the drain. N channel MOS transistor 40
Are provided.

Here, in the level conversion circuits 60a and 60b, there is a period during which a through current flows, and it takes time to invert the through current.

Therefore, as described above, the N-channel MOS
By providing the transistors 37 to 40, the inversion operation can be performed at high speed, whereby the operation of the level conversion circuit can be stabilized, and the process dependency can be further reduced.

[0098]

As described above, in the present invention,
A first level conversion circuit for converting the power supply level of the data on the HIGH output side of the data output from the latch circuit, and a LOW level for the data output from the latch circuit;
Since the second level conversion circuit for converting the power supply level of the data on the output side has the same configuration, the time when the HIGH data is output is equal to the time when the LOW data is output. The effective width of the output data can be secured at a high frequency, and the operating margin of the system can be expanded. This effect is particularly large when there is a process variation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of an output circuit of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration example of the output circuit shown in FIG.

FIG. 3 is a circuit diagram showing another specific configuration example of the output circuit shown in FIG. 1;

FIG. 4 is a diagram illustrating a configuration example of a synchronous DRAM of a double data rate.

FIG. 5 shows a synchronous DR of the double data rate shown in FIG.
It is a figure for explaining operation at the time of an ACTIVATE command input of AM.

FIG. 6 shows a synchronous DR of the double data rate shown in FIG.
FIG. 4 is a diagram for explaining an operation at the time of reading data of AM.

FIG. 7 is a diagram showing signal waveforms in the output circuit shown in FIG.

FIG. 8 shows a synchronous DR of the double data rate shown in FIG.
FIG. 4 is a diagram for explaining an operation at the time of writing data in AM.

9 is a synchronous DR of the double data rate shown in FIG.
It is a figure for explaining operation at the time of a PRECHRAGE command input of AM.

FIG. 10 is a diagram illustrating a configuration example of a level conversion circuit used in the output circuit illustrated in FIG. 4;

11 is a timing chart for explaining an operation of the level conversion circuit shown in FIG.

FIG. 12 is a diagram illustrating a configuration example of the output circuit illustrated in FIG. 4;

[Explanation of symbols]

1,4,9,10,15,19,22,27,28,3
3 Inverter 2,20 NOR gate element 3,21 NAND gate 5,7,11,12,16,18,23,25,29,
30, 34 P-channel MOS transistors 6, 8, 13, 14, 17, 24, 26, 31, 32,
35-40 N-channel MOS transistor 50 Latch circuit 51, 51 Latch section 60a, 60b Level conversion circuit 70 Output transistor section 80 Output terminal

Claims (6)

[Claims] 1. A latch circuit for latching and outputting input HIGH and LOW output data, respectively.
A first level conversion circuit for converting a power supply level of data on the HIGH output side of the data output from the latch circuit;
A second level conversion circuit for converting the power supply level of the data on the LOW output side, and an output for outputting the data converted by the first level conversion circuit and the data converted by the second level conversion circuit An output circuit comprising a transistor unit, wherein the first level conversion circuit and the second level conversion circuit have the same configuration. 2. The output circuit according to claim 1, wherein the first level conversion circuit and the second level conversion circuit each include an inverter that inverts and outputs data output from the latch circuit, A data output from the latch circuit is input to a gate, a first N-channel MOS transistor whose drain is grounded, a predetermined potential VCCQ is applied to a source, and a drain is the first N-channel MOS transistor A first P-channel MOS transistor connected to the source of the first N-channel MOS transistor, a predetermined potential VCCQ is applied to the source, and the gate is connected to the drain of the first N-channel MOS transistor and the source of the first P-channel MOS transistor. And a second P-channel MOS transistor connected to The input signal is input to the gate, the source is connected to the gate of the first P-channel MOS transistor and the drain of the second P-channel MOS transistor, and the second N is connected to the ground.
An output circuit comprising a channel MOS transistor. 3. The output circuit according to claim 1, wherein the first level conversion circuit and the second level conversion circuit each include an inverter for inverting and outputting data output from the latch circuit, A data output from the latch circuit is input to a gate, a first N-channel MOS transistor whose drain is grounded, a predetermined potential VCCQ is applied to a source, and a drain is the first N-channel MOS transistor A first P-channel MOS transistor connected to the source of the first N-channel MOS transistor, a predetermined potential VCCQ is applied to the source, and the gate is connected to the drain of the first N-channel MOS transistor and the source of the first P-channel MOS transistor. And a second P-channel MOS transistor connected to The input signal is input to the gate, the source is connected to the gate of the first P-channel MOS transistor and the drain of the second P-channel MOS transistor, and the second N is connected to the ground.
A channel MOS transistor, a signal output from the latch circuit is input to a gate, a predetermined potential VCCQ is applied to a source,
A third N-channel MOS transistor having a drain connected to a gate of the first P-channel MOS transistor, a drain of the second P-channel MOS transistor 2, and a source of the second N-channel MOS transistor; Is output to the gate, a predetermined potential VCCQ is applied to the source,
An output circuit, comprising: a fourth N-channel MOS transistor having a drain connected to a drain of the first P-channel MOS transistor and a gate of the second P-channel MOS transistor. 4. The output circuit according to claim 1, wherein the latch circuit latches and outputs a HIGH output side data of the input data; And a second latch unit for latching and outputting data on the LOW output side of the input data. 5. The output circuit according to claim 1, wherein the latch circuit and the transistor unit each include a buffer. 6. A synchronous DRAM using the output circuit according to any one of claims 1 to 5.