1221668 玖、發明說明： 【發明所屬之技術領域】 本發明係關於一種靜電放電保護電路，尤指一種利用 金氧半電晶體與矽控整流子串接，進而控制矽控整流子導 通以構成放電路徑的靜電保護電路。 【先前技術】 由於人們接觸1C時，手上的靜電電荷會形成瞬間高 壓，導致元件損壞，因此IC靜電放電（ESD)保護電路的設 計益顯得格外重要。 一般而言，有兩種基本元件可以作為靜電放電保護電 路之用。第一種電路是由薄的或厚的閘極氧化金氧半場效 體（MOSFET)構成，t ESD ;見象發生時，金氧半場效電晶 體會導通，接著寄生的雙極接面電晶體（BJT)跟著導通，以 構成一放電路徑。在ESD結束後，金氧半場效電晶體便不 再導通。前述保護電路的優點在於不會發生鎖住（Latch_up) 現象，原因在於ESD結束後的箝制電壓（H〇iding v〇hage) 通常大於1C的電源4，故不致發生前述的鎖住現象。但 其缺點則在於靜電電荷放電效率不佳。 第一種電路係如第五圖所示，主要係由一石夕控整流子 (7 0 ) (SCR)設於容易產生ESD現象的正電源焊墊Vdd 與Vss電源之間。當ESD現象發生時，正電源焊墊Vdd處 具有較高電壓，而透過電阻（7 )觸發矽控整流子（7 0 )使其導通，而在正電源焊墊vDD與Vss電源構成一放 4 電路徑，以達到靜電保護之目的。 和所有類型的靜電放電電路相比，前述電路中的矽控 整机子（7 0 )在單位面積的放電效率最佳。換言之，一 個由矽控整流子構成的靜電保護電路，是可以非常有效的 達成靜電放電的防護效果，故其運用已愈來愈普遍。然而 其缺點是在於需要較高的觸發電壓，因此多少限制了它的 應用。 為了改善這個問題，許多改良的電路被相繼提出··如 第六圖所不低電壓觸發的矽控整流子電路（LVTSCR)，第七 圖所不的低電壓閘極耦合的矽控整流子電路（GCSCR)、第 八圖所不的二極體串觸發矽控整流子電路（DCTScR)及第九 圖所不的稽納二極體觸發矽控整流子電路（ZDTSCR);前揭 所示的保濩電路雖然降低了觸發電壓，卻也遭遇了 一些問 題： 汝第七圖所示的保護電路係令一場效電晶體與矽控整 机子（7 0 )的NPN電晶體並聯，其閘極則與一 Rc電路 連接。而在某些動態的過壓應力時，閘極搞合石夕控整流子 雖有較低的觸發電壓，惟除需適當的RC電路配合外，當 暫束後’ #控整流子仍然鎖住，且無法抵撐直流的過 壓應力’都是嚴重的缺點。 如第八圊所示的二極體串觸發石夕控整流子電路，不僅 有較低的觸發電壓’且無論IC在動態或靜態時產生過壓 應力都能提供保護，然而順向偏壓時二極體串di〜d4所產 生的漏電卻成為一個很嚴重的問題。 如第九圓所示的稽 nmm 發外整流子電路，則 一 一極體串觸發矽控整 ^ ^ ^ ^ f，瓜千电路具備相同的優點，其皆有 叙低的觸發電壓，R fch 1、 /、白另 白可为別在靜態、動離過屬廄 時提供保護，但是兑缺點0… H過壓應力產生 。 /、缺j疋％要較長的時間進入鎖住狀態 已針對1C的靜電放電 ’但依然分別存在缺陷 由上述可知，在既有技術中， 保護電路提出多種不同的改良方案 ，猶待進一步謀求可行的解決方案 發明目的及概述： 鑑於上述之發明背景中 電放電電路會有漏電流、觸 鎖住的問題及金氧半元件靜 差及使用面積較大的問題。 ’習知技藝中的矽控整流子靜 發電壓過高、箝制電壓太低、 電放電保護電路會有放電效率 【發明内容】 本發明之主要目的在提供一種具較低觸發電壓 、較佳放電效率且不易發生鎖住現象的靜電放電保護電路 ’其將在靜電放電的防護上獲致更高的效率及穩定性。 為達成前述目的採取的主要技術手段係前述靜電放電 保護電路包括有： 一矽控整流子，係設於正/負電源焊墊之間丨 觸叙電壓控制電路，係連接於正電源焊墊與矽控整 流子的閘極間； 1221668 一金氧半場效電晶體，係與石夕控整流子中一電晶體的 射極端連接，以控制其導通與否； 一電晶體控制電路，係設於正電源焊墊與金氧半場效 電晶體之間； 利用前述電路設計，在順向動態過壓應力發生在正電 源焊墊時，電晶體控制電路將產生夠大的輸出電壓使金氧 半場效電晶體導通，並在同時間由觸發電壓控制電路產生 崩潰或其他種觸發電流讓矽控整流子導通，以形成放電路1221668 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to an electrostatic discharge protection circuit, in particular, a metal oxide semiconductor transistor is connected in series with a silicon-controlled commutator to control the conduction of the silicon-controlled commutator to form a discharge. Path for electrostatic protection circuit. [Previous technology] Because people's electrostatic charge on their hands can cause high voltage transients when they come into contact with 1C, the design of IC electrostatic discharge (ESD) protection circuits is extremely important. In general, there are two basic components that can be used as electrostatic discharge protection circuits. The first circuit consists of a thin or thick gate metal oxide half field effect (MOSFET), t ESD; when an image occurs, the metal oxide half field effect transistor will be turned on, followed by a parasitic bipolar junction transistor (BJT) is then turned on to form a discharge path. After the ESD is over, the metal-oxide half-field-effect transistor no longer conducts. The advantage of the aforementioned protection circuit is that a latch-up phenomenon does not occur, because the clamping voltage (Hodding voltage) after the end of the ESD is usually greater than the power source 4 of 1C, so the aforementioned latch-up phenomenon does not occur. However, the disadvantage is that the electrostatic charge discharge efficiency is not good. The first circuit is shown in the fifth figure, which is mainly composed of a stone-controlled commutator (7 0) (SCR) between the positive power supply pad Vdd and Vss power source which is prone to ESD. When the ESD phenomenon occurs, the positive power supply pad Vdd has a higher voltage, and the silicon controlled commutator (7 0) is triggered by the resistor (7) to make it conductive, and the positive power supply pads vDD and Vss power supply form a single amplifier 4 Electrical path to achieve the purpose of electrostatic protection. Compared with all types of electrostatic discharge circuits, the silicon control unit (70) in the aforementioned circuit has the best discharge efficiency per unit area. In other words, an electrostatic protection circuit composed of silicon-controlled commutators can effectively achieve the protection effect of electrostatic discharge, so its application has become more and more common. However, its disadvantage is that it requires a higher trigger voltage, which limits its application to some extent. In order to improve this problem, many improved circuits have been put forward successively. As shown in the sixth figure, the silicon controlled rectifier circuit (LVTSCR) triggered by the low voltage, the low voltage gate coupled silicon controlled rectifier circuit shown in the seventh (GCSCR), the diode-triggered silicon-controlled rectifier circuit (DCTScR) shown in the eighth figure, and the diode-triggered silicon-controlled rectifier circuit (ZDTSCR) not shown in the ninth figure; Although the protection circuit lowered the trigger voltage, it also encountered some problems: The protection circuit shown in the seventh figure is a field effect transistor connected in parallel with the NPN transistor of the silicon control unit (70), and its gate It is connected with an Rc circuit. Under certain dynamic overvoltage stresses, although the gate electrode is suitable for the Shixi controlled commutator, although it has a lower trigger voltage, except for the proper RC circuit cooperation, the #controlled commutator is still locked after the temporary bundle. , And can not withstand the DC overvoltage stress' are serious disadvantages. The diode string-triggered Shixi controlled rectifier circuit as shown in Figure VIII not only has a lower trigger voltage, but also provides protection whether the IC generates overvoltage stress during dynamic or static conditions. The leakage current generated by the diode strings di ~ d4 has become a serious problem. As shown in the ninth circle of the external commutator circuit, the one-to-one string triggers the silicon control circuit ^ ^ ^ ^ f. The guaqian circuit has the same advantages, all of which have a low trigger voltage, R fch 1, /, white and white can provide protection when it is static, moving away from a maggot, but against the disadvantage of 0 ... H overpressure stress. /, The lack of j 疋% takes a long time to enter the locked state. It has been targeted for the electrostatic discharge of 1C. However, there are still defects. As can be seen from the above, in the existing technology, a variety of different improvement schemes have been proposed for the protection circuit. Objectives and summary of the invention: In view of the above-mentioned background of the invention, the electric discharge circuit has the problems of leakage current, contact lock, and the static difference of the metal-oxygen half element and the problem of large area. 'The silicon-controlled commutator in the conventional technique has too high static voltage, too low clamping voltage, and the electric discharge protection circuit has discharge efficiency. [Summary of the Invention] The main purpose of the present invention is to provide a lower discharge voltage and better discharge. An electrostatic discharge protection circuit that is efficient and is not prone to lock-in, it will achieve higher efficiency and stability in the protection of electrostatic discharge. The main technical measures adopted in order to achieve the foregoing purpose are that the aforementioned electrostatic discharge protection circuit includes: a silicon controlled commutator, which is located between the positive / negative power pads, and a contact voltage control circuit, which is connected to the positive power pads and Between the gates of the silicon controlled commutator; 1221668 A metal-oxide half field effect transistor is connected to the emitter terminal of a transistor in the Shi Xi controlled commutator to control its conduction; a transistor control circuit is located at Between the positive power pad and the metal oxide half field effect transistor; using the aforementioned circuit design, when the forward dynamic overvoltage stress occurs in the positive power pad, the transistor control circuit will generate a large enough output voltage to make the metal oxygen half field effect The transistor is turned on, and at the same time, the trigger voltage control circuit generates a breakdown or other trigger current to turn on the silicon controlled rectifier to form a discharge circuit.
徑’由於石夕控整流子呈現鎖住狀態，故正電源焊墊處的電 壓將迅速降到矽控整流子的箝制電位，而達到靜電放電之 保護目的。以該等設計即兼具低觸發電壓、有效增進靜電 放電效率等優點。 前述的矽控整流子係由一 NPN電晶體與一 pNP電晶 體組成，其t PNP電晶體係以其射極構成SCR其中一陽 極，其集極係連接NPN電晶體的基極，並構成SCR的另Since the Shixi controlled commutator is locked, the voltage at the positive power supply pad will quickly drop to the clamping potential of the silicon controlled commutator to achieve the protection purpose of electrostatic discharge. These designs have both the advantages of low trigger voltage and effective improvement of electrostatic discharge efficiency. The aforementioned silicon controlled commutator system is composed of an NPN transistor and a pNP transistor. The t PNP transistor system has one of the anodes of the SCR with its emitter. The collector is connected to the base of the NPN transistor and forms the SCR. Another
一陽極，X PNP電晶體之基極係與卿t晶體的集極連 接，並構成SCR的閘極。 前述金氧半場效電晶體係以汲極與矽控整流子中NP 電晶體的射極連接’又以閘極與電晶體控制電路連接。 前述的電晶體控制電路係由電容、電阻組成，其二_ 之連接即點係與金氧半場效電晶體的閘極連接，並可透纪 調整電容容值、電阻阻值調整其時間常數，而控制金氧= 場效電晶體的導通時間長短，以便有足夠的時間將動” 壓應力降至最低，以達到較佳的靜電放電防護。 7 1221668 前述電晶體控制電路可由其他具有類似功能的電路構 成。 前述觸發電壓控制電路係以—稽納二極體連接於石夕控 整流子中清/NPN電晶體的基極間，其可在金氧半場效 電晶體關閉後仍能達到繼續放電的功效。 前述觸發電壓控制電路中的稽納二極體進一步串接一 二極體，其彳使稽、納二極體在逆㈣態過壓應力發生在正 電源焊墊時獲得保護’更可降低稽納二極體所帶來的漏電 流。 前述矽控整流子與負電源焊墊間串接有一二極體串， 其可在動態過壓應力結束後，讓矽控整流子繼續導通，更 可進一步提升靜態時的箝制電壓，達到靜電放電的防護。 前述的二極體串亦可連接在正電源焊墊與矽控整流子 之間。 【實施方式】 如第一圖所示，係本發明之方塊圖，其包括有： _ 一矽控整流子（1 〇 )，係設於正電源焊墊vDD與負 電源焊墊vss之間； 一觸發電壓控制電路（20)，係連接於正電源焊墊 VDD與矽控整流子（1 〇 )的閘極間； 一金氧半場效電晶體（3 〇 )，係與矽控整流子（工 0 )連接，以控制其導通與否； 電aa體控制電路（4 0 )，係設於正電源焊墊 8 1221668 與金氧半場效電晶體（3 〇 )之間；其中： 如前述之靜電放電保護電路可設於正電源/輸出入谭 塾’或者輸出入/負電源烊墊處。 ϊ過壓應力發生在正電源焊塾vDD時，前述電晶體抑 制電路（4 0 )將產生夠大的輸出電壓使金氧半場效電晶 體（3 0 )導通，同時間並由觸發電壓控制電路（2 〇 ) 產生崩潰電流讓矽控整流子（丄〇 )導通，以形成放電路 徑，由於矽控整流子（1 〇)呈現鎖住狀態，故正電源焊 墊VDD處的電壓將迅速降到矽控整流子的箝制電位，而達 到靜電放電之保護目的。 有關前述實施例的詳細電路圖，請參閱第二圖所示， 該石夕控整流子（i 〇 )係、由一 PNP電晶體（2工）與丄 NPN電晶體（i 2 )組成，其二者可由雙載子電晶體構成 ’其中PNP電晶體（1 1 )係以其射極構成SCR其中一 陽極’且其基極透過-電阻Rn連接到正電源谭墊Vd'd，電 阻RN之-端構成SCR的另一陽極，又電晶體（1 1 )集極係連接函電晶體（1 2)的基極，並透過一電阻An anode, the base of the X PNP transistor is connected to the collector of the crystal, and constitutes the gate of the SCR. The aforementioned metal-oxide-half-effect transistor system is connected to the emitter of the NP transistor in the silicon controlled commutator by the drain and connected to the transistor control circuit by the gate. The foregoing transistor control circuit is composed of a capacitor and a resistor. The second connection is the point connection with the gate of the metal-oxide-semiconductor field-effect transistor, and the capacitance and resistance of the capacitor can be adjusted through time. And control the conduction time of the metal oxide = field effect transistor, so that there is enough time to minimize the dynamic "compressive stress to achieve better electrostatic discharge protection. 7 1221668 The aforementioned transistor control circuit can be similar to Circuit configuration. The aforementioned trigger voltage control circuit is connected to the base of the Shixi controlled commutator in the Qing / NPN transistor with an audit diode, which can continue to discharge after the metal-oxygen half field effect transistor is turned off. The above mentioned diode in the trigger voltage control circuit is further connected in series with a diode, which enables the diode and nano diode to be protected when the reverse over-state stress occurs in the positive power pad. It can reduce the leakage current brought by the audit diode. A diode string is connected in series between the silicon controlled commutator and the negative power pad, which can continue the silicon controlled commutator after the dynamic overvoltage stress is over. Continuity can further increase the clamping voltage in static state to achieve electrostatic discharge protection. The aforementioned diode string can also be connected between the positive power pad and the silicon controlled commutator. [Embodiment] As shown in the first figure Is a block diagram of the present invention, which includes: _ a silicon controlled commutator (10), which is located between the positive power pad vDD and the negative power pad vss; a trigger voltage control circuit (20), Connected between the positive power pad VDD and the gate of the silicon controlled commutator (10); a metal-oxide half field effect transistor (30) is connected to the silicon controlled commutator (0) to control its conduction and No; the electric aa body control circuit (40) is located between the positive power supply pad 8 1221668 and the metal-oxide half field effect transistor (30); of which: the aforementioned electrostatic discharge protection circuit can be provided at the positive power supply / I / O Tan 塾 'or I / O / negative power supply pads. ΪOvervoltage stress occurs when the positive power supply is welded. VDD, the aforementioned transistor suppression circuit (40) will generate a large enough output voltage to make the metal-oxygen half field effect power. The crystal (3 0) is turned on at the same time and controlled by the trigger voltage control circuit (2 ) Generate a breakdown current to make the silicon-controlled commutator (丄 〇) turn on to form a discharge path. Since the silicon-controlled commutator (10) is in a locked state, the voltage at the positive power supply pad VDD will quickly drop to the silicon-controlled rectifier. The clamping potential of the electron is achieved to achieve the purpose of protection of electrostatic discharge. For the detailed circuit diagram of the foregoing embodiment, please refer to the second figure. The Shixi controlled commutator (i 〇) is a PNP transistor (2 workers) And 丄 NPN transistor (i 2), both of which can be composed of bipolar transistor 'where PNP transistor (1 1) is composed of one of the anodes of the SCR with its emitter' and its base is connected through a resistance Rn To the positive power supply Tan pad Vd'd, the-terminal of the resistor RN constitutes the other anode of the SCR, and the collector of the transistor (1 1) is connected to the base of the transistor (1 2) and passes through a resistor
Rsub與接地端Vss連接’又PNJ)電晶體（丄丄）之基極係 與ΝΡΝ電晶體（1 2 )的集極連接开接 木《迓镬，並構成SCR的閘極 ，而與觸發電壓控制電路（2 〇 )連接. 該觸發電壓控制電路（2 〇 1沾六+ v匕U )的存在，能大幅降低矽 控整流子（1 0 )的觸發電壓， J以採用的觸發電壓控制 電路有很多種，例如利用金氧丰 軋牛％效電晶體汲極崩潰機制 、閉極耗合(Gate C_ed)、稽納穿透機制觸發電路等。於 9 1221668 本實施例中，係採用稽納二極體觸發電路（Zener Di〇de trigger)，其電壓參考工具包括一個稽納二極體（ζι)，該稽 納二極體（Z1)係連接在石夕控整流子（1 〇 )的pnP/npn電 晶體（1 1 ) / ( 1 2 )的基極間，其一端並透過電阻Rn 連接至正電源焊墊vDD。 而前述金氧半％效電晶體（3 〇 )係與碎控整流子（ 1 0 )中的NPN電晶體（1 2 )串接，本實施例中，其係 以沒極連接NPN電晶體（1 2 )的射極端。 又於本實施例中，該電晶體控制電路（4 〇 )係由 RC電路構成，其中，電阻R1 一端係與正電源焊墊VDD連 接，另、與電容C1的連接節點則連接金氧半場效電晶體 (3 0 )的閘極，當調整電阻R1阻值與電容C1容值時， 可調節該RC電路的時間常數，從而控制金氧半場效電晶 體（3 0 )的導通時間。 由上述說明可看出本發明一較佳實施例之具體電路構 造’至於其如何達成靜電放電保護，詳如以下所述： 當順向動態過壓應力發生在正電源焊墊VDD時，電晶 體控制電路（4 0)會產生足夠大的電壓輸出，使得金氧 半場效電晶體（3 〇 )導通，同時間觸發電壓控制電路（ 2 〇 )將產生崩潰電流讓矽控整流子（1 〇 )導通，此時 放電路徑形成’矽控整流子（1 0 )呈現鎖住的狀態，故 正電源焊塾VDD會迅速降到矽控整流子（1 〇 )的箝制電 & ’達到靜電放電的保護。又在動態過壓應力結束後，電 曰曰歧控制電路（4 0 )的輸出信號小到不足以驅動金氧半 10 場效電晶體（3 G )導通，此㈣控整流子（i Q )有一 邊不會導通’故不致發生鎖住現象，如此可避免習知技藝 中’積體電路（ICs)在動態過麼應力結束後，因箝制電愿小 於正電源焊墊vDD而發生永遠鎖住的現象。 當逆向動態過壓應力發生在正電源焊墊VDD時，電晶 體控制電路（40)會產生負向高a，因而無法使金氧半 場效電晶體（3 0 )導通，而矽控整流子（i 〇 )則會部 分電路導通，從Vss經矽控整流子（1〇) (NpN電晶體 基極到集極）到正電源焊墊vdd形成一條放電路徑，故在 逆向動態過壓應力發生時，亦可達到靜電放電的保護。 又，在動態過壓應力發生時，電晶體控制電路（4 〇 )可以決定金氧半場效電晶體（3 0 )的導通時間長度， 同時也決定了矽控整流子（i 〇 )的導通時間，故適當的 控制電晶體控制電路（4 〇 )導通時間長度，可使矽控整 流子（1 0 )有足夠的時間將動態過壓應力降至最低，以 達到較佳的靜電放電防護。 再者，當過壓應力結束後，假如正電源焊墊Vdd仍然 存在著較高的電壓，而存在傷害電路的疑慮，則稽納二極 體（Z1)的存在，可在金氧半場效電晶體（3 〇 )關閉後仍 月b達到繼續放電的功效。主要係因正電源焊墊V⑽的電壓 大於稽納二極體（Z1)的崩潰電壓，將使稽納二極體（Z1)導 通’崩潰電流能使矽控整流子（1 0 )中的PNP電晶體（ 1 1 )進入主動區’此時有兩條放電路徑同時形成，其分 別疋正電源焊墊VDD經稽納二極體（zi)到Vss，以及正電 1221668 源焊塾VDD經PNP電晶體（1 1 )到vss，而使矽控整流 子（1 0 )部分導通，以達到繼續放電的效果。 如第三圖所示，係本發明又一較佳實施例的詳細電路 圖’其基本架構與第二圖所示實施例大致相同，不同處在 於矽控整流子（1 〇 )與接地端版間進一步串接有一二極 體串D1〜D4。又觸發電壓控制電路（2〇)之稽納二極體 (Z1)係與一二極體〇5串接在矽控整流子（1 〇 )的 PNP/NPN電晶體（1 1 ) / ( 1 2 )的基極間。 其工作原理亦與前一實施例大致相同，不同處在於放 電路徑形成且動態過壓應力結束後，電晶體控制電路（4 0 )的輸出電壓小到不足以驅動金氧半場效電晶體（3 〇 )導通，但矽控整流子（1 〇 )中的NPN電晶體（1 2 ) 射極串接的二極體串D1〜D4，不僅能讓矽控整流子（1 〇 )繼續導通，更可進一步提升靜態時的箝制電壓，達到靜 電放電的防護。 至於觸發電壓控制電路（2 0 )中的稽納二極體（z 1) 和矽控整流子（1 〇 )中NPN電晶體（1 2 )基極間所連 接的二極體D5，除了能使稽納二極體（Z1)在逆向動態過壓 應力發生在正電源焊墊VDD時獲得保護，更降低了稽納二 極體（Z1)所帶來的漏電流。 所以本發明所能達成的功效，係可使矽控整流子（1 0 )無論處在動態、靜態過壓應力產生時都持續導通著， 此為已知的其他靜電放電保護電路所不能及的，而矽控整 流子（1 0 )中的NPN電晶體（1 2 )射極串接的二極體 12 串D1 D4貝《j大幅提升準靜態、靜態時的箱制電I，有效避 免了鎖住現象。 再如第四圖所示，係本發明再一較佳實施例的詳細電 路圖，其基本架構與前一實施例大致相同，不同處係將二 極體串D1〜D4移至石夕控整流子（1 0 )中PNP電晶體（ 1 1 )射極與正電源焊墊Vdd間，又使金氧半場效電晶體 (3 0 )移至正電源焊墊vDD與矽控整流子（1 〇 )之間 。但效果上則與前一實施例完全相同，其能使矽控整流子 (1 0 )無論處在動、靜態過壓應力時都持續導通著，且 大幅提升準靜態、靜態時的箝制電壓，避免了鎖住現象。 綜合以上所述，本發明揭露了一種控制矽控整流子導 通的技術。根據本發明控制矽控整流子導通的技術手段， 可以確保動態過壓應力發生在電源焊墊時，矽控整流子可 迅速導通’使電源焊墊的過壓應力立刻降至矽控整流子的 箝制電壓，達到保護的效果。當過壓應力結束後，雖然金 氧半場效電晶體不再導通，但因矽控整流子中的NPN電晶 體射極串接二極體串，故能使矽控整流子無論處在動、靜 態過壓應力時都持續導通著，同時大幅提升準靜態、靜態 時的箝制電壓，避免了鎖住現象。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其他為脫離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下所述之申 請專利範圍。 13 【圖式簡單說明】 (一） 圖式部分 第一圖：係本發明之方塊圖。 第- 一圖·係本發明一較佳實施例之詳細電路圖。 第二[21 . ^ a —㈤·係本發明又一較佳實施例之詳細電路圖。 ^四圖·係本發明再一較佳實施例之詳細電路圖。 圖。五圖·係習用矽控整流子靜電放電保護電路之電路 z、圖·係習用低電壓觸發矽控整流子靜電放電保護 电略之電路圖。 七圖：係習用低電壓閘極耦合矽控整流子靜電放電 保遵電路之電路圖。 第八圖：係習用二極體串觸發矽控整流子靜電放電保 °電路之電路圖。 第九圖·係習用稽納二極體觸發矽控整流子靜電放電 保護電路之電路圖。 (二） 元件代表符號 (1 0 )矽控整流子（1 1 ) PNP電晶體 (1 2 ) NPN電晶體 （2 〇 )觸發電壓控制電路 (3 0 )金氧半場效電晶體 (4 0 )電晶體控制電路 (7 0 )石夕控整流子 （7 1 )電阻 14Rsub is connected to the ground terminal Vss, and the base of the PNJ transistor (丄 丄) is connected to the collector of the NPN transistor (1 2), which is connected to the ground and forms the gate of the SCR, and is controlled by the trigger voltage. The circuit (20) is connected. The existence of the trigger voltage control circuit (201 + 6) can greatly reduce the trigger voltage of the silicon controlled commutator (10). J uses a trigger voltage control circuit which has There are many types, for example, the use of metal oxides to reduce the efficiency of the transistor's drain collapse mechanism, closed-circuit consumption (Gate C_ed), the penetrating mechanism trigger circuit and so on. In 9 1221668 in this embodiment, a Zener Diode trigger circuit is used. The voltage reference tool includes a Zener Diode (ζι). The Zener Diode (Z1) is It is connected between the bases of the pnP / npn transistor (1 1) / (1 2) of the Shixi controlled commutator (10), and one end of the pnP / npn transistor (1 2) is connected to the positive power pad vDD through a resistor Rn. The aforementioned metal-oxygen half-efficiency transistor (30) is connected in series with the NPN transistor (1 2) in the broken control commutator (1 0). In this embodiment, it is connected to the NPN transistor with a pole ( 1 2). Also in this embodiment, the transistor control circuit (40) is composed of an RC circuit, wherein one end of the resistor R1 is connected to the positive power supply pad VDD, and the connection node to the capacitor C1 is connected to a metal-oxygen half field effect. The gate of the transistor (3 0) can adjust the time constant of the RC circuit when adjusting the resistance of the resistor R1 and the capacitance of the capacitor C1, so as to control the on-time of the metal-oxygen half field effect transistor (30). From the above description, we can see the specific circuit structure of a preferred embodiment of the present invention. As for how to achieve electrostatic discharge protection, the details are as follows: When the forward dynamic overvoltage stress occurs on the positive power supply pad VDD, the transistor The control circuit (40) will generate a sufficiently large voltage output to make the metal-oxide half field effect transistor (30) turn on. Triggering the voltage control circuit (20) at the same time will generate a breakdown current for the silicon-controlled commutator (10). Turn on, at this time the discharge path is formed. The silicon controlled commutator (1 0) appears locked, so the positive power source welding VDD will quickly drop to the clamping voltage of the silicon controlled commutator (1 0) & protection. After the dynamic overvoltage stress is over, the output signal of the electric control circuit (40) is small enough to drive the metal-oxide-semiconductor 10 field effect transistor (3G) to turn on. This controllable commutator (iQ) One side will not be turned on, so no locking phenomenon will occur. In this way, the integrated circuits (ICs) in the conventional art can be permanently locked because the clamping voltage is smaller than the positive power pad vDD after the dynamic stress is over. The phenomenon. When the reverse dynamic overvoltage stress occurs at the positive power supply pad VDD, the transistor control circuit (40) will generate a negative high a, so the metal-oxide half field effect transistor (3 0) cannot be turned on, and the silicon controlled commutator ( i 〇), part of the circuit will be turned on, from Vss through silicon controlled commutator (10) (NpN transistor base to collector) to the positive power pad vdd to form a discharge path, so when the reverse dynamic overvoltage stress occurs , Can also achieve the protection of electrostatic discharge. In addition, when a dynamic overvoltage stress occurs, the transistor control circuit (40) can determine the length of the on-time of the metal-oxide half-field-effect transistor (30), and also determines the on-time of the silicon-controlled commutator (i). Therefore, proper control of the on-time length of the transistor control circuit (40) can make the silicon controlled commutator (10) have enough time to minimize the dynamic overvoltage stress to achieve better electrostatic discharge protection. In addition, after the overvoltage stress is over, if the positive power pad Vdd still has a high voltage and there is a concern about damaging the circuit, the presence of the diode (Z1) can be used in the metal-oxygen half-field effect. After the crystal (30) is turned off, it still has the effect of continuing to discharge. Mainly because the voltage of the positive power supply pad V⑽ is greater than the breakdown voltage of the Zener diode (Z1), it will cause the Zener diode (Z1) to conduct. The breakdown current can make the PNP in the silicon controlled commutator (1 0). The transistor (1 1) enters the active area. At this time, two discharge paths are formed at the same time, which are respectively the positive power supply pad VDD via the audit diode (zi) to Vss, and the positive power 1221668 source welding VDD via PNP. The transistor (1 1) to vss, and the silicon controlled commutator (1 0) is partially turned on to achieve the effect of continuing the discharge. As shown in the third figure, it is a detailed circuit diagram of another preferred embodiment of the present invention. Its basic structure is substantially the same as the embodiment shown in the second figure, except that the silicon-controlled commutator (10) and the ground terminal plate are different. Further, a diode string D1 to D4 is connected in series. The trigger diode (Z1) of the voltage control circuit (20) is also a PNP / NPN transistor (1 1) / (1 2) between the bases. Its working principle is also roughly the same as the previous embodiment, except that after the discharge path is formed and the dynamic overvoltage stress is over, the output voltage of the transistor control circuit (40) is small enough to drive the metal-oxide half field effect transistor (3 〇) is turned on, but the NPN transistor (1 2) in the silicon controlled commutator (1 0) is connected in series with the diode string D1 to D4 of the emitter, which not only allows the silicon controlled commutator (1 0) to continue to conduct, but also Can further increase the clamping voltage in static state to achieve electrostatic discharge protection. As for the diode D5 connected between the base of the zener diode (z 1) in the trigger voltage control circuit (20) and the NPN transistor (1 2) in the silicon controlled commutator (10), The Zener diode (Z1) is protected when the reverse dynamic overvoltage stress occurs at the positive power supply pad VDD, and the leakage current caused by the Zener diode (Z1) is further reduced. Therefore, the effect achieved by the present invention is that the silicon controlled commutator (1 0) can be continuously conducted regardless of the dynamic and static overvoltage stress generated, which is beyond the reach of other known electrostatic discharge protection circuits. , And the NPN transistor (1 2) in the silicon controlled commutator (1 0) is connected in series with the diodes of 12 diodes D1 D4, which greatly improves the box electricity I in quasi-static and static state, effectively avoiding Lock phenomenon. As shown in the fourth figure, it is a detailed circuit diagram of another preferred embodiment of the present invention. The basic structure is substantially the same as the previous embodiment. The difference is that the diode strings D1 to D4 are moved to the Shixi controlled commutator. The (10) PNP transistor (1 1) between the emitter and the positive power supply pad Vdd, and the metal-oxide half field effect transistor (3 0) is moved to the positive power supply pad vDD and the silicon controlled commutator (1 0) between. However, the effect is exactly the same as the previous embodiment, which can make the silicon controlled commutator (1 0) continue to conduct regardless of the dynamic and static overpressure stress, and greatly increase the clamping voltage during quasi-static and static. Avoiding locking. In summary, the present invention discloses a technology for controlling the conduction of a silicon controlled commutator. According to the technical means for controlling the conduction of the silicon-controlled commutator according to the present invention, it can be ensured that when the dynamic overvoltage stress occurs on the power supply pad, the silicon-controlled commutator can be turned on quickly, so that the overvoltage stress of the power pad is immediately reduced to that of the silicon-controlled commutator. Clamp the voltage to achieve the effect of protection. When the overvoltage stress is over, although the metal-oxide half-field-effect transistor is no longer conducting, the emitter of the NPN transistor in the silicon-controlled commutator is connected to the diode string in series, so that the silicon-controlled commutator can move, The static overvoltage stress is continuously conducted, and the clamping voltage during quasi-static and static state is greatly improved, which prevents the locking phenomenon. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following The scope of patent application mentioned. 13 [Schematic description] (1) Schematic part The first diagram: a block diagram of the present invention. Figure-1 is a detailed circuit diagram of a preferred embodiment of the present invention. The second [21. ^ A —㈤ · is a detailed circuit diagram of yet another preferred embodiment of the present invention. ^ Four diagrams are detailed circuit diagrams of still another preferred embodiment of the present invention. Illustration. Figure 5 is a circuit diagram of a conventional silicon-controlled commutator electrostatic discharge protection circuit. Z, Figure is a circuit diagram of a conventional low-voltage triggered silicon-controlled commutator electrostatic discharge protection circuit. Figure 7: Circuit diagram of a conventional low voltage gate coupled silicon controlled commutator electrostatic discharge guarantee circuit. Figure 8: Circuit diagram of a silicon-controlled commutator electrostatic discharge protection circuit using a conventional diode string. The ninth figure is a circuit diagram of a conventional Schottky diode-triggered silicon-controlled commutator electrostatic discharge protection circuit. (2) Symbol of component (1 0) Silicon controlled commutator (1 1) PNP transistor (1 2) NPN transistor (2 0) trigger voltage control circuit (3 0) metal-oxide half field effect transistor (4 0) Transistor control circuit (7 0) Shi Xikong commutator (7 1) resistor 14