TWI221024B - Manufacturing process of memory module with directly chip-attaching - Google Patents

Abstract

A manufacturing process of memory module with directly chip-attaching is configured for integrating packaging procedure and module making procedure. After chips are singulated from a wafer, a plurality of chips is directly attached on a module substrate. The testing and renovating the chip on the substrate are executed prior to packaging the chip, so as to reduce installation cost of testing devices and testing cost.

Description

1221024 V. Description of the invention (1) [Field of the invention] The present invention relates to _ ^ ^. ^ Au ^. Kinds of memory cores, and the method of making k, especially β = 矣 贝 占 Memory module Of the manufacturing process. [Prior technology] The conventional memory module level > i 1 P eight & — < The manufacturing method is divided into three main chips 即, namely: f product f 之: wafer production process, Packaging process and mold assembly: The production of hemp-provided memory wafers is completed, and after the second step, the wafers are packaged by a wafer, which will be formed by a wafer substrate or a circuit film. Such as thin ^ ″ μ y sealed with resin to form a memory package junction

Package, Ts,. View package [Th in Sin a 1 1 0u 11 ine Package> gQ. Or ball grid array package [Ball Grid Array / or aging test] 'and perform electrical tests on the memory package structure and restore multiple memories / [ burn-in test]; then, a module assembly plant is used to reassemble the k & body package structure and join it to a memory module substrate [small print year inverse], -j · #-L > Into a memory module [mem 〇rym 〇du 1 e] 'and memory 捃 Γ product test' In terms of this known standard process, each type of test machine, and product to go through three different The test equipment 'i.e. the wafer testing platform is from a package structure testing machine and the module testing machine'. Although the above machine 1 is a wave | i [for the use of j Wu brother memory body ' Probe card [contact wafer], packaging structure test machine 丨 —FIX test board to fasten a θ package structure] and slot test board of module test machine (using memory ^ memory module) are completely Not the same, cannot be integrated 'In each type of two, and the manufacturing process requires the use of three Expensive testing machine k i ',-T3 II Μ surface

Page 4 1221024 V. Description of the invention (2) The cost of setting up the test machine is quite high, and various test costs are added. It is undeniable that memory modules are developing towards a low volume. Therefore, in addition to high-capacity and high-density memory, the manufacturing cost of memory modules should also effectively reduce the integration and testing of chip packaging processes and module assembly processes. The Republic of China Patent Gazette Bulletin No. 47 2 372 "wafer module and its manufacturing process" discloses a direct wafer manufacturing process, which is shown in Figure 1. First, "provide a wafer" 11, " The test results of “First Wafer Test Test” 1 3 and “Second Wafer Test” 14 and “Second Wafer Test” 14 are the test results. In “Crystal 0”, the wafer is selectively cut into As shown in the figure of the plurality of memories 2, the chip group 20 is composed of a plurality of side-by-side crystals J, and the wafers 21 are formed with bumps 22, and after the "substrate" 16 steps, the "direct attachment" is performed The chip step is to bond the chipset 20 to the memory and cover the bumps 2 with a packaging material 40 in the step of "packaging" 18, and directly attach the wafer to the above-mentioned wafer to fabricate the wafer. Although the process has integrated the chip packaging process and module assembly test steps 1 2, 1 4 It is a wafer type test. For the functions of the chipset 20 and the memory module substrate 30 electrically connected to the module substrate 30, etc., the memory module cannot be effectively detected, and it may still be defective. Another need to pay attention to the different tests will increase the price and high memory capacity: the continuous research of wafers, especially for the reduction of crystals and costs, the direct attachment of memory sticking memory module k-circle type sequentially performed " 12. "After the aging test, according to" Section 丨 cutting "15 steps of chip set 20, as in the h; 2 1 integrated structure to provide the memory module group on the substrate" 1 7 step body module substrate 30, [underfill ] The manufacturing process of the memory module, but its test _ formation of the connection status and memory by subsequent operations, the problem of its manufacture is the chipset 1221024

V. Description of the invention (3) For the production of 20, after the wafer is manufactured, the wafer cannot be completely cut, and selective cutting must be performed according to the test results to produce a wafer group 20 having a plurality of wafers 2 1 in one. The wafer cutting paths are different at one time, and the automatic design of cutting is more complicated and difficult in the past. For example, the defective wafer 21 is not properly dispersed on the wafer, which will make the integrated wafer group 20 difficult to manufacture. Furthermore, when the chipset 20 has a larger area than the conventional individual chips, when the memory module substrate 30 is attached, there is a greater thermal stress, which is easy to peel off or seduce. [Objective and Summary of the Invention] The main purpose of the present invention is to provide a manufacturing process of directly attaching a memory module to a wafer. After the wafer is diced, an unknown qualified chip (unknown g00d die) is attached to the memory. Module module substrate, and at least one module-level test in the package to reduce test machine setup costs and test costs, while ensuring the electrical connection between the chip and the memory module substrate and the memory module Functionality of the substrate. * The second purpose of the present invention is to provide a manufacturing process of directly attaching a memory chip to a chip, which tests the chip on a module substrate for packaging and then repairs the chip, such as laser repair or chip replacement, for effective integration. The front-end testing δ-type and back-end testing are at the module level, which can save the cost of front-end testing and repair. The manufacturing process of directly attaching a memory module to a chip according to the present invention includes the following steps in sequence: providing a wafer having a plurality of memory chips; cutting the wafer to form a plurality of memory chips; providing A memory module substrate; attaching a predetermined number of the memory chips to the memory

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1221024 V. Description of the invention (4) Body module substrate; the first module tests the memory chips on the memory module substrate; and the -memory packaged on the memory module substrate Preferably, it further includes an aging test, which can be performed in a wafer type or a module shape. "[Detailed description of the invention], please refer to the attached drawings" The present invention will enumerate the following embodiments:

As shown in FIG. 3, according to a first specific embodiment of the present invention, a chip directly attached to a memory module includes a memory module substrate 130, which is a small printed circuit board, and the conventional system has A plurality of circuit layers (approximately 4 to 8 layers or more), a plurality of gold fingers 1 3 1 [g 〇1 dfinger] are formed on one side of the memory module substrate 1 3 0 for insertion It is connected to another electrical component. In this embodiment, the memory module substrate 13 is a DDR L ji. · DIMM substrate [Double Data Rate Dual In-line Memory 1: Modu 1 e], which There are 184 gold fingers. However, the present invention is not limited to the number of memory module substrates 130 and their gold fingers. The memory module substrate 130 can be SDRAM [Synchronous Dynamic Random Access Memory] ], Fiash [flash memory] or other memory module substrates, the memory module substrate 1 3 0 and a buckle groove 1 3 2 are formed on both sides of the gold finger 1 3 1 for insertion Positioning and stability at the time, the memory module substrate 1 30 is connected with a plurality of memory chips 120a, 1 20b 120, and the wires 121, TAB lead ψ refers to the [tape automatic bonding lead] or the bump is electrically connected to the memory module substrate 1 3 0, and the circuit of the memory module substrate 1 3 0 Electrically conductive to the corresponding gold finger 1 3 1, In addition, the chip directly attached to the memory module further includes at least one packaging material 140, combined with the chips 120a, 120b, 120

Page 7 1221024 V. Description of the invention (5) and the memory module substrate 130. The manufacturing process of the chip directly attached to the memory module of the present invention is used to manufacture the above memory module. As shown in FIG. 4, the steps mainly include: "provide a wafer" 1 1 1 , "Wafer dicing" 1 1 3, "attach the wafer to the substrate" 1 1 4, "the first module test" 1 1 5, "repair the wafer" 1 1 6, "the second module test" 1 17 and "Packaging" 11 8 In the step of "Providing a Wafer" 1 11, a wafer is provided, which has a plurality of memory chips, preferably, in "Providing a Wafer" 1 1 After step 1 'execute a "wafer-level burn-in test" 11 2 and apply a voltage higher than the normal operation of the memory to the wafer at a temperature of about 1 2 5 to 15 0 ° C [> 2 · 5V], in order to damage the early bad memory chip on the wafer, in the "wafer dicing" step 11 of 3, the wafer is cut into a plurality of individual wafers. In the step of “attaching the wafer to the substrate” 11 4, as shown in FIG. &Amp; a ', obtain an appropriate number of wafers 1 2 0a, 120b, 120 [such as 2, 4, 8, 16, 32, or other numbers] and attached to the memory module substrate 130. In this embodiment, the chips 120a, 120b, and 120 are electrically bonded with a plurality of wires 120 to the Memory module substrate 130. In addition, flip-chip bonding and TAB bonding are also feasible methods. After that, in the steps of 1 1 5 of the "first module test", as shown in Figure 5B, the system A memory module test machine module is used to test the 5 bonded wafer module substrates 1 2 0 a, 1 2 b, 1 2 0, and the memory module test machine. It has a test substrate 170. When the memory module substrate 丨 3 〇 is inserted into the test substrate 170 slot 丨 7 i, the memory module substrate 丨 1221024 V. Description of the invention (6 ) Golden Finger 1 3 1 series is electrically connected to the module test machine for repairable module-level test. In addition, in addition to the slot test machine, the probe test The machine can also be used to test these chips at the module level 1 2 0 a, 1 2 0 b, 1 2 0; after the "first module test" 1 1 5, execute the "repair the chip" 1 1 6 steps 'It is based on the results of the first module test to repair the memory chips 1 2 0 a, 1 2 Ob, 1 2 0 on the memory module substrate 1 30, as shown in Figure 5C. 'When it is measured that the memory module substrate 130 has a defective but still repairable wafer 120a, according to the result of memory repair analysis (MRA, Memory Repair Analysis), after positioning the wafer i2〇a, a The laser device 1 80 irradiates the appropriate fuse [fu se 1 ink] of the chip 12a, and replaces the damaged memory volume circuit with a redundant circuit [redundancy circui t], as shown in FIG. 5D. When the memory module substrate 1 30 has a defective and cannot be repaired wafer 1 2 0b, another integrated circuit wafer 1 60 is used to replace the defect on the 5 Xuanzhang memory module substrate 1 30. Memory chip 1 2 0 b, such as stacking or removing, and electrically connecting the memory module with wires 16 1 or other electrical connection devices The substrate 130, preferably, the integrated circuit wafer 160 used for replacement is a known good wafer [Known Good Die, KGD]; preferably after 16 steps of "repairing the wafer", Perform "Second Module Test" 11 7, as shown in Figure 5 E, test the repaired memory module substrate 1 3 0 with the memory module test machine module, the memory module The substrate 1 30 is connected to the socket 17 1 or other probes of the test substrate 170 to confirm the quality and to be graded. Finally, the “Packaging” 11 8 project is performed with a packaging material such as electrical insulation The thermosetting resin is formed by stenciling or potting

Page 9 1221024 V. Description of the invention (Ό The memory module substrate 13 to protect the wafers 120a, 120, 160 ° Therefore, the manufacturing process of directly attaching the memory module to the wafer according to the present invention is effectively integrated Packaging process and module assembly process, and integrate the use of wafer, package structure and module test machine, to ensure that between the chip 120, the memory module substrate 130 and the above with module level test The state of the electrical connection line has the effect of low-cost manufacturing and high-quality products. According to the first specific embodiment of the present invention, the manufacturing process of another chip directly attached to the memory module is shown in FIG. 6, The main steps are the same as the first embodiment, such as "provide a wafer" 211, "wafer dicing" 2 1 2, "attach the wafer to the substrate" 2 1 3, "first module test" idc 2 1 5, "Repair chip" 2 1 6, "Second module test" 2 1 7 and "Packaging" 2 1 8; Figure 7 shows the completed memory module. "Board" 2 1 3 steps, a plurality of wafers 2 2 0 are positioned and fixed to a record The grooves 2 3 2 of the body module substrate 2 3 0, and the establishment of the grooves 2 3 2 is provided with a fixing wafer 220 and a bonding pad for preventing the sticking material of the wafer 220 from contaminating the connection pads of the memory module substrate 23 0 Draw], and connect the pads of the chips 22 0 with the connection pads of the memory module substrate 230 with a wire 221, and then electrically conduct to the gold finger 2 3 1 of the memory module substrate 2 3 0, After “attaching the wafer to the substrate” 2 1 3, a “module level burn-in test” step 2 1 4 is performed, which is performed at 70 ～ 100 ° c. 5 Ji Yi body weight group substrate 2 3 0 is applied with a predetermined voltage for several hours to damage the memory module substrate 2.30 early bad memory chip 2 2 0, in the "first module test '' 2 1 5, `` Repair chip '' 2 1 6 and

Page 10, 1221024 V. Description of the invention (8) "Second module test" After 2 1 7, a packaging material 2 40 is formed by spot coating [ρ 〇 11 ing], which seals the chips 220 and the wires. 221 to complete the "package" 2 1 8 project. The protection scope of the present invention shall be determined by the scope of the appended patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. .

Page 11 1221024 Brief description of the drawings [Schematic description] Figure 1: A manufacturing process diagram of a conventional chip directly attached to a memory module, Figure 2: Sectional schematic diagram of a conventional chip directly attached to a memory module Figure 3: A schematic diagram of a chip directly attached to a memory module according to a first embodiment of the present invention; Figure 4: A chip of directly attached memory module according to a first embodiment of the present invention Manufacturing process diagram; Figure 5A ... According to the first specific embodiment of the present invention, a cross-sectional view of a wafer directly attached memory module at the wafer attach manufacturing step; Figure 5B ... In a specific embodiment, a cross-sectional view of a chip directly attached to a memory module in the first module test manufacturing step; FIG. 5C... According to a first embodiment of the present invention, a chip is directly attached to a memory module A cross-sectional view of the manufacturing step 1 during renovation; FIG. 5D: a cross-sectional view of the second manufacturing step of a memory module directly attached to a chip according to the first embodiment of the present invention; FIG. 5E: the first In the embodiment, a cross-sectional view of a chip directly attached to a memory module in the second module test manufacturing step, FIG. 5F: According to a first specific embodiment of the present invention, a chip is directly attached to a memory module. A cross-sectional view of a package manufacturing step; FIG. 6: a manufacturing process diagram of a chip directly attached to a memory module according to a second embodiment of the present invention; and

Page 12 1221024 Brief description of the diagram Figure 7 • Schematic diagram of the memory module according to the first embodiment of the present invention, [illustration of the drawing number] 11 provide a wafer 12 first wafer test 13 aging Test 14 Second wafer test mode 15 Wafer dicing 16 Provide memory module base-board 17 Directly attach the chip set to the substrate 18 Package 20 Chip set 21 Wafer 22 Bump 30 Module substrate 40 Packaging material 111 Provide wafer 112 Wafer-level aging test 113 Wafer cutting 114 Attaching the wafer to the substrate 115 First module test 116 test 117 Second module 湏, 1 test 118 Seal 120 MW 20a, 120b wafer 121 Conductor 130 Memory module substrate 131 Gold finger 132 Buckle slot 140 Seal 150 Laser beam machine 160 Chip 161 Guide 170 Predictive substrate 171 Slot 180 Laser 211 Provide a wafer 212 Wafer cutting 213 Attach the wafer to the substrate. 214 Module-level aging j j test 215 The first module test 216 whole 217 The second module 湏 丨 1 test 218 chips directly attached #

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Claims (1)

1221024, patent application scope [patent application scope] 1. A manufacturing process of directly attaching a memory module to a wafer, which includes the steps of: providing a wafer, the wafer having a plurality of memory wafers; cutting the crystal Circle to form a plurality of individual memory chips; attach a predetermined number of the memory chips to a memory module substrate; the first module test of the memories on the memory module substrate A chip, and the memory chips packaged on the memory module substrate. 2. According to the manufacturing process of directly attaching a memory module to a chip as described in item 1 of the scope of the patent application, the additional steps include: according to the first module test results, repairing the memory module substrate The above memory chip is after the first module test step. 3. As mentioned in item 2 of the scope of patent application, the chip directly attaches the memory module | group manufacturing process, which further includes the steps of: the second module test of the memories on the memory module substrate Bulk wafer, after the reconditioning step. 4. The manufacturing process of directly attaching the memory module as described in item 2 or 3 of the patent application scope, wherein the repair step includes: replacing the memory module with another integrated circuit chip Bad memory chip on the substrate. 5. According to the manufacturing process of the chip directly attached to the memory module described in item 4 of the scope of patent application, the integrated circuit chip used for replacement is already Page 15 1221024 6. Scope of patent application Knowing good crystals 6. For example, if the body module is applied for repair, it is repaired on the wafer. 7. If the manufacturing of the application group includes the substrate, there is no good. 8. If the manufacturing of the application group knows good crystals. 9. One kind of crystal steps is: Provide one to execute [Known God Die, KGD]. The direct-attached memory manufacturing process of the chip described in item 2 or 3 of the patent scope, wherein the repair step includes: memory of the memory module substrate which can still be repaired if the defective on the memory module substrate is defective The process of directly attaching the memory module to the chip described above, in addition to the laser repair, the repair step includes: replacing the memory chip that is good and cannot be repaired in the memory module with another integrated circuit chip. The process of directly attaching a memory phantom as described in item 7 of the patent scope, wherein the integrated circuit chip to be replaced is a [Known Good Die, KGD] manufacturing process of directly attaching a memory module , Which contains a wafer having a plurality of memory wafers; a wafer-level burn-in test [wafer 1 eve 1 bur η-i η test] to damage early bad memory chips on the wafer; cutting The wafer 'forms a plurality of individual memory chips, and attaches a predetermined number of the memory chips to a memory module substrate; the first module tests the memories on the memory module substrate A body chip, and the memory chips packaged on the memory module substrate. 1 10. The chip directly attached to the memory as described in item 9 of the scope of patent application Page 16 1221024 Sixth, the test group for the module of the patent application module test structure wafer, 1 1. If the test of the module application is after the step of the record 12, if the application of the memory module is: the other bad 13 If the application module is known to be good 14, if the application memory module is: laser memory 15, if the module application step is the system module base 16, if the application module manufacturing process' The other steps include: According to the results, the memory on the memory module substrate is repaired after the first module test step. The process of directly attaching the memory chip to the chip described in item 10 of the patent scope includes the following steps: the memory chips on the module module substrate of the second module test are renovated. The manufacturing process of directly attaching a wafer as described in 10 or 11, wherein the repair step includes an integrated circuit chip instead of a memory chip on the memory module substrate. The chip directly attached to the memory manufacturing process described in item 12 of the patent scope, in which the integrated circuit chip to be replaced is [Known Good Die, KGD]. The manufacturing process of the direct attachment of the wafer as described in the patent scope No. 10 or 11, wherein the repair step includes repairing the defective wafer on the memory module substrate which can still be repaired. The process of directly attaching a memory chip as described in Item 14 of the patent scope, in addition to laser repair, the repair includes: replacing the defective and unrepairable memory board with another integrated circuit chip Memory chip. The chip directly attached to the memory manufacturing process described in the patent scope No. 15, wherein the integrated circuit chip used for replacement is _ Page 17 1221024 6. The scope of patent application is Known Good Die [KGD]. 17. A manufacturing process for directly attaching a memory module to a wafer, which includes the steps of: providing a wafer, the wafer having a plurality of memory wafers; cutting the wafer to form a plurality of individual memories Chip; attach a predetermined number of the memory chips to a memory module substrate; perform a module-level burn-in test [m odu 1 e 1 eve 1 bur η-i η tes t] to damage the memory Early bad memory chips on the body module substrate; the first module tests the memory chips on the memory module substrate; and the memory chips packaged on the memory module substrate. 18. Directly attach the chip as described in item 17 of the scope of patent application. The manufacturing process of the module includes the following additional steps: According to the test results of each group of the first mold, repair the memory chips on the memory module substrate, after the first module test step . 19. According to the manufacturing process of the chip directly attached to the memory module described in item 18 of the scope of patent application, the additional steps include: the second module test on the memory module substrate. Memory chip, after 4 steps of refurbishment. 20. The manufacturing process of directly attaching a memory module to a chip as described in item 18 or 19 of the scope of patent application, wherein the repair step includes replacing the memory module with another integrated circuit chip Body module substrate Page 18 1221024 VI. Bad patent application scope 21, if the application module is known to be good 2 2. If the application memory module has a laser memory 2 3. As in the application module manufacturing process System module base 2 4. If the system of the application module is known to be good, there are 25 kinds of grooves with multiple memories. At least one of the grooves with a plurality of boards is at least one. If the module is applied, its memory chip. The process of directly attaching a memory chip as described in the scope of patent No. 20, in which the integrated circuit chip to be replaced is a Known Good Die (KGD). The manufacturing process of the direct attachment of the wafer described in the patent scope No. 18 or 19, wherein the repair step includes repairing the defective wafer which can still be repaired on the substrate of the memory module. The process of directly attaching a memory chip as described in item 22 of the patent scope, in addition to laser repair, the repair includes: replacing another defective integrated circuit chip on the memory board, which cannot be repaired and cannot be repaired. Memory chip. The chip directly attached to the memory manufacturing process described in item 23 of the patent scope, wherein the integrated circuit chip to be replaced is a Known Good Die (KGD). A chip is directly attached to a memory module, which includes: a body module substrate having buckle grooves on both sides and gold fingers on one side, and one surface of the memory module substrate is formed with a groove; a memory chip, individually A ground is fixed on the memory module base and electrically connected to the memory module substrate; and a packaging material is formed in the grooves. The chips described in item 25 of the patent scope are directly attached to the memory. These chips are connected with wires and are electrically bonded to the memory. Page 19 1221024 6. Scope of patent application Memory module substrate. 27. The chip directly attached to the memory module as described in item 25 of the patent application scope, wherein the packaging material seals the chips. 28. The chip directly attached to the memory module as described in item 25 of the scope of patent application, wherein the packaging material is a thermosetting resin formed by spot coating.