TWI221022B - Semiconductor optoelectrical processing device for reducing light refraction - Google Patents

Semiconductor optoelectrical processing device for reducing light refraction Download PDF

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TWI221022B
TWI221022B TW092127884A TW92127884A TWI221022B TW I221022 B TWI221022 B TW I221022B TW 092127884 A TW092127884 A TW 092127884A TW 92127884 A TW92127884 A TW 92127884A TW I221022 B TWI221022 B TW I221022B
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semiconductor
item
patent application
scope
substrate
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TW092127884A
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TW200514217A (en
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Cheng-Wei Huang
Kun-Ching Chen
Yi-Tsai Lu
Tun-Ching Pi
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Advanced Semiconductor Eng
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

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  • Led Device Packages (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

A semiconductor optoelectrical processing device for reducing light refraction comprises a shell body with a glass lid, a semiconductor chip installed inside the shell body and a thixotropic optical gel. The semiconductor chip has an active surface corresponding to the glass lid. The thixotropic optical gel is filled between the active surface of the semiconductor chip and the glass lid of the shell body in order to reduce light refraction and diffraction happened in the gap between the semiconductor chip and the glass lid.

Description

12210221221022

【發明所屬之技術領域】 本發明係有關於一種減少光折射之半導體光電處理 器’特別係有關於一種減少光折射之影像顯示處理器。 【先前技術】 較常見之半導體光電處理器,係被運用於背投影機之 影像顯不’例如運用於數位光源處理器〔Digi tal Light[Technical field to which the invention belongs] The present invention relates to a semiconductor optoelectronic processor for reducing light refraction ', and more particularly to an image display processor for reducing light refraction. [Previous technology] A more common semiconductor optoelectronic processor is the image display used in a rear projector. For example, it is used in a digital light source processor [Digi tal Light

Processing device,DLP〕之數位微鏡裝置〔DigitalDigital micromirror device [Processing device, DLP]

Micfomio'ior Device,DMD〕或液晶矽基板顯示裝置 〔Liquid Crystal 〇n Silicon,LCOS〕,其應具有良好Micfomio'ior Device (DMD) or liquid crystal silicon substrate display device [Liquid Crystal ON Silicon, LCOS], which should have good

之光處理特性,以達到大尺寸精細畫面之顯示,而習知半 導體光電處理器係具有一半導體晶片,該半導體晶片係密 閉地組配裝設在一殼體内,該殼體之玻璃蓋與該半導體晶 片之間係存在有一間隔,該間隔係被空氣所填充或呈真空 狀態,而玻璃蓋之折射率係約為15,空氣之折射率係約 ,1.0003,因兩者的折射率差異,使得該半導體光電處理 器會產生光繞射與光折射現象,造成無法正確反射輸出光 源與影像,影響影像顯示畫面。 【發明内容】 本發明之主要目的係在於提供一種減少光折射之半導 體光電處理器,利用一觸變性光學膠體〔thix〇tr〇pic L· optical、gel〕形成於一半導體晶片之主動表面與一殼體 之玻璃蓋之間,以減少在該玻璃蓋與該半導體晶片間之間 隔發生光繞射與光折射之問題。 依本發明之減少光折射之半導體光電處理器,其包含Light processing characteristics to achieve large-size and fine-screen display, and the conventional semiconductor optoelectronic processor has a semiconductor wafer, which is hermetically assembled in a housing, the cover of the housing and the glass cover There is a gap between the semiconductor wafers, and the gap is filled with air or in a vacuum state. The refractive index of the glass cover is about 15, and the refractive index of air is about 1.003. Because of the difference in refractive index between the two, As a result, the semiconductor optoelectronic processor will generate light diffraction and light refraction, which will cause the output light source and image to be reflected incorrectly, which will affect the image display screen. [Summary of the Invention] The main purpose of the present invention is to provide a semiconductor optoelectronic processor that reduces light refraction. A thixotropic optical colloid (thixotropic L · optical, gel) is used to form an active surface of a semiconductor wafer and a Between the glass covers of the housing, the problems of light diffraction and light refraction between the glass cover and the semiconductor wafer are reduced. A semiconductor optoelectronic processor for reducing light refraction according to the present invention includes

1221022 五、發明說明(2) 有一殼體、一半導體晶片及一觸變性光學膠體 〔thixotropic optical gel〕,其中該殼體係具有一基 板及一玻璃蓋,其中該基板係可為陶瓷電路基板,以固定 該半導體晶片’該半導體晶片係具有一主動表面及_對應 之背面’其中該半導體晶片之背面係設於該殼體之基板 上’該半導體晶片之主動表面係對應該玻璃蓋,而該觸變 性光學膠體係形成在該半導體晶片與該玻璃蓋之間,較佳 地’該觸變性光學膠體係具有介於丨之間的折射 率〔refractive index〕,又以介於14〜1·5之間的折射 率為尤佳,以減少在該殼體與該半導體晶片間之間隔發生 光繞射與光折射之問題。 【實施方式】 參閱所附圖式,本發明將列舉以下之實施例說明。 依據本發明之第一具體實施例,請參閱第1圖,一種 減少光折射之半導體光電處理器1 〇 〇係包含有一殼體丨丨〇、 一半導體晶片120及一觸變性光學膠體130〔 thixotropic optical gel〕,其中該殼體11〇係包含有一基板111及一 玻璃蓋11 2,該基板111係可為陶瓷電路基板,該基板111 具有一頂面111 a及一底面111 b,該基板111係用以固定並 電性連接該半導體晶片1 20,在本實施例中,該基板111之 周邊固設有一框壁1 13,其係與該基板11 1之頂面11 la形成 一容晶室11 4,該容晶室11 4係位於該基板111之頂面111 a 上,以容設該半導體晶片1 2 0,並且該框壁11 3可結合該玻 璃蓋11 2〔 glass 1 id〕,使該玻璃蓋11 2裝設於該基板1111221022 V. Description of the invention (2) A casing, a semiconductor wafer and a thixotropic optical gel, wherein the casing has a substrate and a glass cover, wherein the substrate can be a ceramic circuit substrate. Fixing the semiconductor wafer 'the semiconductor wafer has an active surface and a corresponding back surface' wherein the rear surface of the semiconductor wafer is provided on the substrate of the housing 'the active surface of the semiconductor wafer corresponds to a glass cover, and the contact A denatured optical glue system is formed between the semiconductor wafer and the glass cover. Preferably, the thixotropic optical glue system has a refractive index between 丨 and a range of 14 to 1.5. The refractive index is particularly preferred to reduce the problems of light diffraction and light refraction that occur between the housing and the semiconductor wafer. [Embodiment] With reference to the drawings, the present invention will be described by the following embodiments. According to a first specific embodiment of the present invention, please refer to FIG. 1. A semiconductor optoelectronic processor 100 for reducing light refraction includes a housing, a semiconductor wafer 120, and a thixotropic optical colloid 130. [thixotropic optical gel], wherein the housing 110 includes a substrate 111 and a glass cover 112. The substrate 111 may be a ceramic circuit substrate. The substrate 111 has a top surface 111a and a bottom surface 111b. The substrate 111 It is used to fix and electrically connect the semiconductor wafer 120. In this embodiment, a frame wall 1 13 is fixed around the substrate 111, which forms a crystal-capacitor chamber with the top surface 11a of the substrate 111. 11, the crystal chamber 11 4 is located on the top surface 111 a of the substrate 111 to accommodate the semiconductor wafer 1 2 0, and the frame wall 11 3 can be combined with the glass cover 11 2 [glass 1 id], The glass cover 11 2 is mounted on the substrate 111

第9頁 1221022 五、發明說明(3) 之該頂面111 a上,以密封該容晶室11 4。 該半導體晶片120係具有一主動表面121及一對應之背 - . 面122,在本實施例中,該半導體晶片120之主動表面121 係可設有一玻璃基板123,且該玻璃基板123係具有一 ITO 〔Indium Tin Oxide, 氧化銘1錫〕導電層124,以使該半 導體晶片1 2 0及該玻璃基板1 2 3組立成為數位微鏡裝置 〔Digital Micromirr ior Device, DMD〕、液晶石夕基板胞 元〔Liquid Crystal On Silicon cell, LCOS cell 〕或 其它半導體光電元件,其中該半導體晶片120之背面122係 設於該殼體11 0之基板111上,該半導體晶片1 20其係可以 環氧黏膠1 4 3黏著於該基板111上,該半導體晶片1 2 0之主 動表面1 2 1係對應該玻璃蓋11 2,另該半導體晶片1 2 〇之主 動表面121係形成有複數個微機電形成之微鏡結構〔 mirrior〕、畫素元件〔pixel element〕或感測元件等等 〔圖未繪出〕,或者,上述之微鏡結構之微機電元件亦可 s又於或玻璃基板123在面向該半導體晶片120之主動表面 1 2 1之表面,並以複數個電性連接元件1 4 1電性連接該半導 體晶片1 2 0與該基板111,該些電性連接元件1 4 1係可為鲜 線,較佳地,以一接地元件142電性連接該玻璃基板123之 IT0導電層124至該基板111。 而該觸變性光學膠體1 3 0係填充在該半導體晶片丨2 〇與 β玻璃蓋11 2之間的間隔,使得在該半導體晶片1 2 q之主‘ 表面121與該玻璃蓋112之間不會因真空或空氣產生光繞射 與光折射現象,較佳地,該觸變性光學膠體丨3 〇係具有介 1221022Page 91221022 5. The top surface 111a of the description of the invention (3) is used to seal the crystal-capacitive chamber 11 4. The semiconductor wafer 120 has an active surface 121 and a corresponding back-surface 122. In this embodiment, the active surface 121 of the semiconductor wafer 120 can be provided with a glass substrate 123, and the glass substrate 123 has a ITO [Indium Tin Oxide] conductive layer 124, so that the semiconductor wafer 120 and the glass substrate 123 are assembled into a digital micromirror device (DMD), a liquid crystal substrate substrate cell [Liquid Crystal On Silicon cell, LCOS cell] or other semiconductor optoelectronic components, in which the back surface 122 of the semiconductor wafer 120 is provided on the substrate 111 of the housing 110, and the semiconductor wafer 120 can be epoxy adhesive 1 4 3 is adhered to the substrate 111. The active surface 1 2 1 of the semiconductor wafer 1 2 0 corresponds to the glass cover 11 2, and the active surface 121 of the semiconductor wafer 1 2 0 is formed with a plurality of micro-electromechanical devices. Mirror structure [mirrior], pixel element [pixel element] or sensing element [not shown], or the micro-electromechanical element of the above-mentioned micro-mirror structure can also be used on a glass substrate 123 The surface facing the active surface 1 2 1 of the semiconductor wafer 120 is electrically connected to the semiconductor wafer 1 2 0 and the substrate 111 by a plurality of electrical connection elements 1 4 1. The electrical connection elements 1 4 1 are As a fresh line, preferably, a ground element 142 is used to electrically connect the IT0 conductive layer 124 of the glass substrate 123 to the substrate 111. The thixotropic optical colloid 13 0 fills the space between the semiconductor wafer 丨 2 0 and the β glass cover 11 2, so that there is no difference between the main surface 121 of the semiconductor wafer 1 2 q and the glass cover 112. Diffraction and light refraction can occur due to vacuum or air. Preferably, the thixotropic optical colloid 丨 3 〇 system has a median 1221022

於1入0003 1.5之間的折射率〔refractive ,其中 以”於4〜1 · 5之間的折射率為尤佳,以減少在該殼體丨i 〇 之玻璃蓋11 2與該+ $體晶片1 20 間隔發生光繞射與光 折射現象’並且該觸變性光學膠體丨3 〇係具有一Refractive index between 1 and 0003 and 1.5 [refractive, in which the refractive index between "4 ~ 1 · 5" is particularly preferred to reduce the glass cover 11 2 and the + body in the housing 丨 i 〇 The phenomenon of light diffraction and light refraction occurs at intervals of 1 to 20 of the wafer, and the thixotropic optical colloid 3 has a

〔Q45〇Y75〇nm〕可見光吸收率,其係小於0· 003 〔/〇/micron〕’在本實施例中,該觸變性光學膠體13〇係 具有觸變性質,在施加適當壓力,該觸變性光學膠體1 3 〇 係可流動塗施在該半導體晶片12〇之主動表面121上,當該 光電處理器於靜置狀態時,該觸變性光學膠體13〇係如果 凍般黏稠狀密實地填充形成於該半導體晶片丨2〇之主動表 面12 1與玻璃蓋1 1 2之間,由於在完成處理器組裝後該觸變 性光學膠體1 3 0仍具有觸變性質,故該觸變性光學膠體丨3 〇 =同於習知固化後之透明膠體,而使得該半導體光電處理 器1 0 0具有良好之重工性,較佳地,該殼體丨丨〇内更設有一 支持板116,並以該支持板116撐托一阻隔罩丨15 〔dividing mask〕,該阻隔罩115係具有一開口117,以 顯露該觸變性光學膠體1 3 〇,該阻隔罩11 5係用以阻隔該觸 變性光學膠體130,使該觸變性光學膠體丨30不接觸該基板 111,但仍使得該觸變性光學膠體1 30能確實形成在該半導 體晶片1 2 0與該玻璃蓋11 2間,以減少該半導體光電處理器 1 〇 〇内光繞射與光折射之問題。 依據本發明之第二具體實施例,請參閱第2圖,其係 揭示有一種減少光折射之半導體光電處理器2〇〇,其係包 含有一殼體210、一半導體晶片220及一觸變性光學膠體[Q45〇Y75〇nm] Visible light absorption, which is less than 0.003 [/ 〇 / micron] 'In this embodiment, the thixotropic optical colloid 13 has thixotropic properties. The denatured optical colloid 130 can be flow-applied on the active surface 121 of the semiconductor wafer 120. When the optoelectronic processor is at rest, the thixotropic optical colloid 13 is filled densely if frozen. Formed between the active surface 12 1 and the glass cover 1 12 of the semiconductor wafer 20, since the thixotropic optical colloid 1 30 still has thixotropic properties after the processor assembly is completed, the thixotropic optical colloid 丨3 〇 = The same as the conventional transparent colloid after curing, so that the semiconductor optoelectronic processor 100 has good reworkability. Preferably, a support plate 116 is further provided in the casing. The support plate 116 supports a barrier mask 丨 15. The barrier mask 115 has an opening 117 to expose the thixotropic optical colloid 1 30, and the barrier mask 115 is used to block the thixotropic optical colloid. 130, making the thixotropic optics The body 30 does not contact the substrate 111, but still allows the thixotropic optical colloid 130 to be formed between the semiconductor wafer 120 and the glass cover 112, so as to reduce the light around the semiconductor optoelectronic processor 1000. The problem of radiation and light refraction. According to a second specific embodiment of the present invention, please refer to FIG. 2, which discloses a semiconductor optoelectronic processor 200 for reducing light refraction, which includes a housing 210, a semiconductor wafer 220 and a thixotropic optics. colloid

1221022 五、發明說明(5) 230,該殼體210係包含有一基板21 1及一玻璃蓋212,其中 該基板2 11具有一體形成於頂面周邊之框壁2 1 3,該框壁 2 1 3係可如以預模成形〔p r e 一 m 〇 1 d i n g〕,以形成一中央凹 ; 陷之容晶室2 1 4,或者亦由該基板2 1 1形成一凹穴以形成該 容晶室214,並以該框壁213結合該玻璃蓋112〔glass 1 id〕,該半導體晶片220係設於該殼體210之容晶室214内 並電性連接至邊基板211 ’該半導體晶片220係依光電產品 設計之需求不同可為投影機之影像顯示晶片、數位攝影機 之感測晶片、發光晶片與微機電晶片等半導體光電元件, s亥半導體晶片220係具有一主動表面221及一對應之背面 2 2 2 ’該主動表面2 2 1係對應該玻璃蓋21 2,而該觸變性光 學膠體230係填充於該半導體晶片220之主動表面221與該 玻璃蓋212之間,且在該半導體晶片220之主動表面221係 可設有一玻璃基板223,在本實施例中,該半導體晶片22〇 之主動表面221係形成有重分配線路224或是電性貫通孔 〔圖未繪出〕,該些重分配線路2 2 4係電性導通該半導體 晶片220之主動表面221與背面222,使得在該半導體晶片 220之背面222形成之複數個凸塊241電性連接至該主動表 面221,並且以該些凸塊241電性連接該半導體晶片22〇與 該基板211,較佳地,在該半導體晶片22〇與該基板2ι工之 間係形成有一底部填充膠242〔underfilling material〕,以穩固結合該半導體晶片22〇,因此,該半 導體光電處理器200係利用「該觸變性光學膠體23〇形Λ成於 該半導體晶片220與該殼體210之玻璃蓋212之間〆的結構、1221022 5. Description of the invention (5) 230, the housing 210 includes a substrate 21 1 and a glass cover 212, wherein the substrate 2 11 has a frame wall 2 1 3 integrally formed on the periphery of the top surface, and the frame wall 2 1 The 3 series can be formed with a pre-mold [pre-molding] to form a central cavity; the recessed cavity 2 1 4 or a substrate 2 1 1 to form a cavity to form the cavity. 214, and the frame wall 213 is combined with the glass cover 112 [glass 1 id]. The semiconductor wafer 220 is set in the capacitor cell 214 of the housing 210 and is electrically connected to the side substrate 211. The semiconductor wafer 220 series Depending on the requirements of the design of optoelectronic products, it can be a semiconductor optoelectronic element such as an image display chip of a projector, a sensor chip of a digital camera, a light emitting chip, and a micro-electromechanical chip. The semiconductor chip 220 has an active surface 221 and a corresponding back surface. 2 2 2 'The active surface 2 2 1 corresponds to the glass cover 21 2, and the thixotropic optical colloid 230 is filled between the active surface 221 of the semiconductor wafer 220 and the glass cover 212, and the semiconductor wafer 220 The active surface 221 can be provided Glass substrate 223. In this embodiment, the active surface 221 of the semiconductor wafer 22 is formed with redistribution lines 224 or electrical through holes (not shown). These redistribution lines 2 2 4 are electrically The active surface 221 and the back surface 222 of the semiconductor wafer 220 are turned on, so that a plurality of bumps 241 formed on the back surface 222 of the semiconductor wafer 220 are electrically connected to the active surface 221, and the semiconductors are electrically connected by the bumps 241. An underfilling material 242 is formed between the wafer 22 and the substrate 211. Preferably, an underfilling material 242 is formed between the semiconductor wafer 22 and the substrate 2 to securely bond the semiconductor wafer 22. Therefore, the semiconductor The optoelectronic processor 200 uses a structure in which the thixotropic optical colloid 23 is formed between the semiconductor wafer 220 and the glass cover 212 of the housing 210,

第12頁 1221022 五、發明說明(6) 特徵,以減少在該玻璃蓋212與該半導體晶片220間之間隔 發生光繞射與光折射之問題。 本發明之保護範圍當視後附之申請 為準,任何熟知此項技藝者,在不脫離本發明之 圍内所作之任何變化與修改’均屬於本發明之保:和範 叹執圍。 鲁Page 12 1221022 5. Description of the invention (6) Features to reduce the problems of light diffraction and light refraction between the glass cover 212 and the semiconductor wafer 220. The protection scope of the present invention is subject to the attached application. Any changes and modifications made by anyone skilled in the art without departing from the scope of the present invention are covered by the scope of the present invention: He Fan. Lu

1221022 圖式簡單說明 【圖式簡單說明 第1 圖:依據本發明之第 一具體實施例 5 — 種減:i 之半導體光電處理器之截面示意圖 ;及 第2 圖:依據本發明之第 二具體實施例 5 -— 種減4 之半導體光電處理器之截面示意圖 〇 元件符號簡單說明: 100 半導體光電處理器 110 殼體 111 基板 111a 頂面 111b 底面 112 玻璃蓋 113 框壁 114 容晶 115 阻隔罩 116 支持板 117 開口 120 半導體晶片 121 主動表面 122 背面 123 玻璃基板 124 導電層 130 觸變性光學膠體 141 銲線 14 2 接地件 143 黏膠 200 半導體光電處理器 210 殼體 211 基板 212 玻璃蓋 213 框壁 214 容晶室 220 半導體晶片 221 主動表面 222 背面 223 玻璃基板 224 重分配線路 230 觸變性光學膠體 241 凸塊 242 底部填充膠 室 « Φ1221022 Brief description of the drawings [Schematic illustration of the first figure: a first specific embodiment 5 according to the present invention-a kind of cross-section schematic diagram of a semiconductor optoelectronic processor minus i; and Fig. 2: a second specific according to the present invention Embodiment 5 --- A schematic diagram of a cross section of a semiconductor optoelectronic processor with minus 4 〇 Simple explanation of the component symbols: 100 semiconductor optoelectronic processor 110 housing 111 substrate 111a top surface 111b bottom surface 112 glass cover 113 frame wall 114 capacitor crystal 115 barrier cover 116 Support plate 117 Opening 120 Semiconductor wafer 121 Active surface 122 Back surface 123 Glass substrate 124 Conductive layer 130 Thixotropic optical colloid 141 Welding wire 14 2 Grounding member 143 Adhesive 200 Semiconductor optoelectronic processor 210 Housing 211 Substrate 212 Glass cover 213 Frame wall 214 Capacitor cell 220 Semiconductor wafer 221 Active surface 222 Back surface 223 Glass substrate 224 Redistribution line 230 Thixotropic optical colloid 241 Bump 242 Underfilled gel chamber «Φ

第14頁Page 14

Claims (1)

1221〇22 六、申請專利範圍 申請專利範圍】 、一種半導體光電 一殼體,其係包 一半導體晶片, ,其中該半導體 半導體晶片之主 一觸變性光學膠 係填充於該半導 如申請專利範圍 該殼體係具有一 半導體 ,該玻 面 該 其 中 該 板 室 晶片係設 璃蓋係設 處理器,其包含: 含有一基板及一玻璃蓋; 其係具有一主動表面及一對應之背 晶片之背面係設於該殼體之基板上, 動表面係對應該玻璃蓋;及 體 C thixotropic optical gel〕, 體晶片與該玻璃盍之間。 第1項所述之半導體光電處理器,其 容晶室,其係形成於該基板之頂面, 於該容晶室中並且電性連接至該基 於該基板之該頂面上,以密封該# Μ I晶 如申請專利範圍第1項所述之半導體光電處理器, 該觸變性光學膠體係具有一介於1.0 003〜1 5之卩卩从、 率〔refractive index 〕 。 如申請專利範圍第1項所述之半導體光電處理器, 該觸變性光學膠體係具有一介於1 · 4〜1 · 5之間的彳斤射/ 〔refractive index 〕 。 如申請專利範圍第1項所述之半導體光電處理器,其 該觸變性光學膠體係具有一可見光吸收率,I a t ' τ 丹係小於 0 03〔 %/micron〕。 、如申請專利範圍第1項所述之半導體光電處理器,其 中該殼體内設有一阻隔罩,用以阻隔該觸變性伞 二 X丨土尤学膠體 中 射 Λ 中 率 中 0· 6 IHil ΙΗ 12210221221〇22 6. Scope of patent application Patent scope], a semiconductor optoelectronic housing, which is a package of a semiconductor wafer, wherein the main semiconductor semiconductor wafer is thixotropic optical adhesive system filled in the semiconductor as in the patent application scope The housing has a semiconductor, the glass surface, wherein the plate chamber wafer is provided with a glass cover, and the processor includes: a substrate and a glass cover; a back surface having an active surface and a corresponding back wafer The moving surface is provided on the substrate of the casing, and the moving surface corresponds to the glass cover; and the body C thixotropic optical gel], between the body wafer and the glass case. The semiconductor optoelectronic processor according to the first item, wherein the capacitor chamber is formed on the top surface of the substrate, is in the capacitor chamber, and is electrically connected to the top surface based on the substrate to seal the substrate. The # Μ I crystal is the semiconductor optoelectronic processor described in item 1 of the scope of the patent application, and the thixotropic optical adhesive system has a refractive index between 1.0 003 and 15. According to the semiconductor optoelectronic processor described in item 1 of the scope of patent application, the thixotropic optical adhesive system has a refraction index between [1.4 to 1.5]. [Refractive index]. According to the semiconductor optoelectronic processor described in the first item of the patent application scope, the thixotropic optical adhesive system has a visible light absorption rate, and I a t 'τ Dan system is less than 0 03 [% / micron]. The semiconductor optoelectronic processor according to item 1 of the scope of patent application, wherein a blocking cover is provided in the shell to block the thixotropic umbrella II X Tuyou Xue colloid shot Λ medium rate 0.6 IHil ΙΗ 1221022 不接觸該基板。 、如申請專利範圍第 另包含有複數個電性 片與該基板。 ! 1項所述之半導體光電處理器,其 連接元件’以電性連接該半導體晶 如申凊專利範圍第7 jg邮、+, ^(項所述之半導體光電虛 π ”1 A 中該些電性連接元件係為銲線。 9'如申請專利範圍第7項所述之半導體光電處理器 中該些電性連接元件係為凸塊。 10、如申請專利範圍第i項所述之半導體光電處理器, 其中該基板係為陶瓷電路板。 1 1、如申請專利範圍第1項所述之半導體光電處理器, 其中該半導體晶片之主動表面係設有一玻璃基板。 12、 如申咕專利範圍第11項所述之半導體光電處理器, 其中該玻璃基板在面向該半導體晶片之主動表面之表 面係設有複數個微機電元件。 13、 如申晴專利範圍第11項所述之半導體光電處理器, 其中該觸變性光學膠體係形成於該半導體晶片上玻璃 基板與該玻璃蓋之間。 j 4、如申請專利範圍第1項所述之半導體光電處理器, 其中δ亥半導體晶片係具有複數個重分配線路,以電性 導通該半導體晶片之主動表面與背面。 丨5、如申請專利範圍第1項所述之半導體光電處理器, 其中該半導體晶片係具有複數個電性貫通孔,以電性 導通該半導體晶片之上下表面。 —Do not touch the substrate. For example, the scope of the patent application also includes a plurality of electrical sheets and the substrate. ! The semiconductor optoelectronic processor according to item 1, its connecting element 'is used to electrically connect the semiconductor crystal as described in the patent application scope No. 7 jg, +, ^ (semiconductor optoelectronic virtual π described in item 1) The electrical connection elements are bonding wires. 9 'The electrical connection elements in the semiconductor optoelectronic processor described in item 7 of the scope of patent application are bumps. 10. The semiconductor described in item i of scope of patent application. Optoelectronic processor, where the substrate is a ceramic circuit board. 1 1. The semiconductor optoelectronic processor as described in item 1 of the patent application scope, wherein the active surface of the semiconductor wafer is provided with a glass substrate. 12. Rushen Patent The semiconductor optoelectronic processor according to item 11 in the scope, wherein the glass substrate is provided with a plurality of microelectromechanical elements on a surface facing the active surface of the semiconductor wafer. 13. The semiconductor optoelectronic device according to item 11 in the scope of Shen Qing patent A processor, wherein the thixotropic optical adhesive system is formed between a glass substrate on the semiconductor wafer and the glass cover. J 4. The semiconductor optoelectronic processor according to item 1 of the scope of patent application, The δH semiconductor wafer has a plurality of redistribution lines to electrically connect the active surface and the back surface of the semiconductor wafer. 丨 5. The semiconductor optoelectronic processor according to item 1 of the patent application scope, wherein the semiconductor wafer has A plurality of electrical through holes for electrically conducting the upper and lower surfaces of the semiconductor wafer. 第16頁 1221022 六、申請專利範圍 1 6、如申請專利範圍第1 項所述之半導體光電處理器, 其中該半導體晶片係為數位微鏡裝置〔D i g i t a 1 Micromirrior Device, DMD 〕 。 1 7、如申請專利範圍第1 項所述之半導體光電處理器, 其中該半導體晶片係為液晶石夕基板胞元〔Liquid Crystal On Silicon cell, LCOS cell 〕 。Page 16 1221022 VI. Patent Application Range 16. The semiconductor optoelectronic processor described in item 1 of the patent application range, wherein the semiconductor wafer is a digital micromirror device [D i g i t a 1 Micromirrior Device, DMD]. 17. The semiconductor optoelectronic processor according to item 1 of the scope of patent application, wherein the semiconductor wafer is a liquid crystal on silicon cell (LCOS cell).
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