TWI220535B - A novel process for preparation of the metal silicide - Google Patents

Abstract

This invention relates to a method of preparation of ultra shallow junction by forming thinner metal silicide on the source and drain surfaces during the 1st stage of silicide formation, after the formation of BN compound on the surface of the gate. The BN compound is removed to expose the gate surface by means of the high etching selectivity between the photoresist and the BN compound, while preparing the thicker metal silicide on the gate surface to reduce the electric resistance during the 2nd stage of silicide formation. In conclusion, this invention involves (1) the formation, on the substrate, of the MOSFET which includes the formation of BN compound on the gate surface, (2) the preparation of the 1st metal silicide on the surfaces of source and drain of the MOS transistor during the 1st stage of silicide forming process, (3) the formation of the dielectric layer on the surface of the substrate, gate and BN compound, and then the formation of photoresist on the top of dielectric layer, (4) the strip-off of photoresist and the removal of the dielectric layer to expose the gate, and (5) the strip-off of photoresist and preparation of the 2nd metal silicide on the gate of MOS transistor utilizing the 2nd stage silicide-forming process.

Description

^ 20535

V. Description of the invention (1) Field of invention: Do not: Λ Ming is related to the process of metallization of semiconductor elements, especially the method of forming gate and drain / source silicidation metal in two or two stages π knife & sun and moon background ： In the trend of ultra-large integrated circuits, the number of integrated circuits is constantly increasing. #Semiconductor integrated circuit's maximum integration, external / j, and transformation trends, on the evening of integrated circuit ', due to the computer and communication technology1 different types and applications of memory & interface or other communication interface, the trend of the body It will still be oriented towards% L · · -jr- * Baiwan components are formed in specific areas. These components are connected to perform special circuits or to improve the density of wafers. ^ Structures become smaller as the component size becomes smaller and smaller ( For example, interconnects), the size of semiconductor components continues to increase along with the increase in the density of the structure. A reduction in the size of electronic components can increase the force. "As electronic component sizes increase, many challenges arise." Therefore, the booming development requires a larger number. For example, the electrical power operated by voice requires a lot of memory elements. Therefore, the co-integration degree develops. The integrated circuit includes the domain, and uses electrical conduction to interconnect. In order to achieve a high-performance integration, the size of the semiconductor is getting more and more. The electrical connection between the semiconductor elements is becoming more and more precise. Alignment and lithography are becoming more and more important.

Metal Oxide Half Field Effect Transistor (MOSFET) is one of the most widely used components in integrated circuits. As everyone knows, MOSFET includes gate, sink

Page 5 1220535 V. Description of the invention (2) ~ " 一 ~ 一 '-pole and source. Similarly, in order to achieve high-performance metal-oxide-semiconductor half-effect transistors, the size of i has also been continuously reduced to meet the requirements of current trends, such as the current requirement that components must have higher operating speeds and lower operating power. In addition, the performance of the device is easily affected by "time delay and contact resistance between the drain and source. Therefore, in the sub-micron process, the self-aligned gold silicide process has become a common method to reduce contact resistance to speed up the device. The speed is selected. &Amp; The conventional technology proposes that the reaction between metal and silicon can be used to generate silicified metal to increase the operation speed of the component. In addition, self-aligned titanium silicide (U si licide) is also often used to do In order to reduce the resistance values of the gate, drain and source to increase the operating speed of the device. The traditional silicidation metal manufacturing process is briefly described as follows. Generally, a metal layer is first deposited on the substrate surface and the gate surface. Then, the substrate is applied with A heat treatment process causes the metal layer to react with silicon to generate silicided metal. Then the unreacted metal layer is removed, and the above-mentioned g process is a general self-aligned silicided metal process. Specifically, in a standard titanium silicide process A two-step heat treatment process is usually required in the above-mentioned titanium silicide process, which often results in a short circuit or a bridge. Generally, the above-mentioned MOS transistor has The gap wall surrounds the gate. The thermal annealing is used to chemically react the titanium metal with the gate, the drain and the source. This step is generally low temperature thermal annealing. Wet etching will not be used later. The reaction titanium metal layer and titanium nitride metal layer are selectively removed, and then a high temperature thermal annealing is performed.

1220535 V. Description of the invention (3) Decrease the resistance value of Shixi Titanium. This means that the temperature of warm annealing is between ° C. However, in the above-mentioned thermal annealing for forming silicided metals. The J yuu atom is a potential source of diffusion. Therefore, based on the above-mentioned &, silicon will likely diffuse to the surface of the barrier wall and the metal on it will form a silicidated metal on the surface of the barrier wall due to the siliceous reaction. , This; May metallize; produce a short circuit between the reverse | and the drain / source. It will cause the inter-electrode I or the traditional technology to synchronize the formation of silicon metal on the gate and silicide metal on the electrode. However, in deep sub-micron technology, there must be a junction / source shanow junction) and a very low resistance = a few poles. In order to meet the requirements of the shallow junction of the drain source, / 1 is required. Thickness, but this will cause the gate voltage and reduce the resistance of the silicide electrode (that is, increase the thickness of the metallized metal V); Conversely, reduce both requirements. One of the ideas is; f cannot be obtained with t and the drain and source / source.鈇 + The end point 接 of different thickness of gold silicide μ will be more difficult and impossible: ’t chemical mechanical ^ only chemical mechanical grinding uniformity. " r mill | Objective and summary of the invention: The main purpose of the present invention is to provide a two-stage silicided metal. Another object of the present invention is to rank. | Siliconized metal manufacturing process is used to obtain boron-containing silicon nitride, and, and the source 'to solve the bridging and short circuit of traditional sanding resistors and very shallow solid metal processes: and the problem, $ 7 _ 1220535 V. Description of the invention (4) In addition, the traditional technology cannot simultaneously meet the requirements of ultra shallow junctions (ultra shallow j unc ti on) and low resistance. The invention includes forming a gate structure on a semiconductor substrate. The gate structure includes a boron nitride (BN) on an upper surface of the gate. After that, a light micro-doped electrode is formed in the semiconductor substrate, and a gap wall is formed on the sidewall of the gate structure. Then, an ion implantation is performed to form a drain and a source in the semiconductor substrate. The first metal layer is formed on the spacer wall, the gate structure, and the semiconductor substrate, and then a first thermal annealing is performed to react the first metal layer with the drain and source to form a first silicided metal, which is subsequently removed without participation. The first metal layer of the reaction. A dielectric layer is formed on the substrate, the gate, and the boron nitride (BN). The next step is to form a photoresist layer over the dielectric layer 'to remove the photoresist layer until the nitride (BN) is deleted. Successively remove the dielectric layer and remove the photoresist. The second metal layer is formed on the dielectric layer and the upper surface of the gate electrode, and then a second thermal annealing is performed to react the second metal layer with the gate electrode to form a second titanium silicide metal, and the second metal that does not participate in the reaction is similarly removed. Floor. Finally, a second thermal annealing is performed to reduce the resistance of the first and second petrified metals. , ’

Detailed description of the invention: As shown in FIG. 1, a single crystal semiconductor having a crystal plane of < 100 > is used as a substrate, such as a P-type or N-type silicon substrate 2. Next, the insulating region 4 ′ which is used as the isolation between the components can be generally fabricated by using shallow trench insulation technology (shaUow) (isolation; STI) or field oxidation insulation technology.

Page 8 1220535 V. Description of Invention (5) Domain 4. For example, if η is used to make a shallow trench and the oxide layer in the shallow trench is flattened, the formation layer 6 can be formed at < the general thick deposition method can also be deposited by vapor deposition to more than 400 angstroms. Next, the photoresist pattern is an etch (M) 10 and a multiple crystal case. Then remove the light. Next, the Li household planting technique planted the hot carriers in the hybrid electrode slightly. Referring to FIG. 1, the surface, silicon oxide stratification vapor deposition method Γ, shallow trench insulation technology uses lithography and etching method in substrate 2 to backfill with chemical vapor deposition oxide layer, and then use back etching or chemical Mechanical grinding will be frank. A gate oxide layer 6 is formed on the k plate 2. Generally, in a gate oxygen environment, the oxidation degree is about 15 to 100 angstroms at a temperature of 7 50 to 1 1 0 0 ° C. , Or the fabrication of the gate oxide layer 6 using a chemical vapor phase. Subsequently, the gate oxide layer 6 is covered with a chemical crystalline silicon layer 8 to a thickness of 1000 Å. A boron nitride (BN) 1 0 is then formed on the polycrystalline silicon layer 8 A photoresist pattern is defined on the boron nitride (BN) 10, and the above-mentioned boron nitride silicon layer 8 is etched with an etching technique using a mask and The gate oxide layer 6 defines the pattern resistance of the gate structure. The I gate structure is used as a mask for ion implantation. Ion ions are used in the substrate 2 to form a lightly doped drain 12 on the side close to the gate to reduce the silicon oxide layer formed in the channel. The surface of the substrate 2 can be formed by a chemical vapor deposition method, such as low pressure, and the process temperature is about 400 to 700 degrees Celsius. then

1220535 V. Description of the invention (7) It has the characteristics of extremely high etching selectivity and can obtain good etching effect. After removing the photoresist 2 2. As shown in FIG. 4, a conductive layer such as titanium or titanium / titanium nitride (T i / T i N) is then deposited on the gate structure and the lining oxide layer (1 i n e r X i d e) 2 0. The thickness of this conductive layer is thicker than that of the conductive layer 18 forming the drain / source electrode. Thus, the thicker silicide metal formed above the gate electrode 8 can reduce the resistance value. Then, titanium (or titanium / titanium nitride) is reacted with the gate electrode 8 by high temperature and low annealing (annea 1 ng) to form petrified metal 26 on the gate electrode. However, since the pole and source 16 are covered by liner oxide 20, they will not react with the metal, so their interface will not be affected. The temperature of the above low temperature thermal annealing is between about 350 ° and 450 ° C. The non-reactive conductive layer is selectively removed by wet etching, and then a high-temperature heat treatment is performed, and a high-temperature thermal annealing process is performed at a temperature between 800 and 90 (TC) to reduce the titanium silicide. The resistance value. Finally, the silicide metal is formed on the gate 8 and the drain / source 16 in two stages. The present invention uses a boron nitride (BN) 10 to form on the gate 8, which can be A thin silicided metal is formed on the drain and source during a single silicidation process, so that a very shallow junction can be made. The boron nitride (BN) 10 can prevent the silicided metal from forming on the gate 8. Utilize the high etching selectivity of photoresist and boron nitride (BN) 1 0 to remove boron nitride (BN) 1 0 to expose the gate surface. Use the second stage silicidation process to make thicker silicide metal on the gate. Is used to reduce resistance.

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Page 12 1220535 Brief description of the drawings Brief description of the drawings: Figure 1 is a sectional view of the gate structure of the present invention. Figure 2 is a cross-sectional view of a photoresist coated on a substrate after forming a silicided metal on a drain / source. FIG. 3 is a cross-sectional view of the polishing photoresist to the surface of a boron nitride according to the present invention. FIG. 4 is a cross-sectional view of forming a second silicide metal on a gate electrode according to the present invention. 4 ~ Insulation area 8 ~ Multicrystalline silicon layer 1 2 ~ Drain / source 1 6 ~ Drain / source 2 0 ~ Shixihua metal 2 6 ~ Shixihua metal pattern drawing number description 2 ~ $ 夕Substrate 6 ~ gate oxide layer 1 0 ~ boron nitride 14 ~ spacer 18 ~ conductive layer 2 2 ~ photoresist

Page 13

Claims (1)

1220535 6. Scope of patent application Remove the second conductive layer not participating in the reaction; and perform a third thermal annealing to reduce the resistance of the first and second silicided metals. 2. The process of claim 1 in which the first dielectric layer includes boron nitride (B N). 3. For the process of claim 1 in the scope of patent application, wherein the second dielectric layer includes an oxide layer. 4. The process of item 1 in the scope of patent application, wherein the first conductive layer mentioned above comprises titanium. 5. The process of item 1 in the scope of patent application, wherein the above-mentioned second conductive layer comprises titanium. 6. The process of item 1 in the scope of patent application, wherein the first conductive layer includes titanium / titanium nitride. 7. The process of item 1 in the scope of patent application, wherein the above-mentioned second conductive layer comprises titanium / titanium nitride. 8. If the process of item 1 of the scope of patent application is applied, the temperature of the first thermal annealing mentioned above is about 350 to 450 ° C. I Page 15 1220535 6. Application scope of patent 9. For the process of item 1 of the scope of application for patent, the temperature of the above-mentioned second thermal annealing is about 350 to 450 ° C. 10. The process of item 1 in the scope of patent application, wherein the second heat annealing temperature is about 800 to 900 ° C. 11 1. The process of item 1 in the scope of patent application, wherein the photoresist is removed by a chemical mechanical polishing process. A kind of silicided dielectric crystalline silicon layer nitride boron-nitride structure, micro-doped barrier wall at 12, a gate formation complex formation I insect engraving the gate formation light metal process, including at least: a semiconductor substrate Over; on the gate dielectric layer; (BN) on the above-mentioned polycrystalline silicon layer; (BN), the polycrystalline silicon layer and the gate dielectric layer are drawn in the shape of the semiconductor substrate Forming a spacer on a side wall of the gate structure; forming a body substrate, performing a first electrode generation, removing an unformed substrate, and performing an ion implantation to form a drain and a source in the semiconductor substrate; a titanium-containing metal layer Above the gap wall, the gate structure, and the semiconductor; a thermal decompression reaction to participate in the anti-electric layer to fire the first titanium-containing metal layer with the drain and the source to form the first titanium silicide ; Corresponding to the first titanium-containing metal layer; the substrate, the gate electrode, and the boron nitride (BN); Page 16 1220535 6. Apply for a patent to form a photoresist covering the dielectric layer; remove the photoresist layer to the boron nitride (BN); remove the dielectric layer to expose the gate; remove the light Forming a second titanium-containing metal layer on the dielectric layer and the gate; performing a second thermal annealing to react the second titanium-containing metal layer with the gate to form a second titanium silicide ; Removing the second titanium-containing metal layer not participating in the reaction; and performing a third thermal annealing to reduce the resistance of the first and second titanium silicides. 13 3. The process of item 12 in the scope of patent application, wherein the above-mentioned dielectric layer includes an oxide layer. 14. The process according to item 12 of the scope of patent application, wherein the first titanium-containing metal layer further includes titanium nitride. 15. The process according to item 12 of the scope of patent application, wherein the second titanium-containing metal layer further includes titanium nitride. 16. According to the process of item 12 in the scope of patent application, wherein the first heat annealing temperature is about 350 to 450 ° C. 17. If the process of item 12 in the scope of patent application is applied, wherein the second heat annealing temperature is about 350 to 450 ° C. Page 17 1220535 6. Scope of patent application 18. For the process of item 12 of patent application scope, the above-mentioned second thermal annealing temperature is about 800 to 90 Ot. 19. The process of item 12 in the scope of patent application, wherein the photoresist is removed by a chemical mechanical polishing process. 20. A two-stage silicidation metal process, comprising at least: forming a gold-oxide semi-transistor on a substrate, the gold-oxygen semi-transistor comprising a first dielectric layer formed on a gate; performing a first-stage silicidation process, Used for making a first silicide metal on the drain and source of the metal-oxide semiconductor; forming a second dielectric layer on the substrate, the gate electrode and the first dielectric layer; forming a photoresist cover Over the second dielectric layer; removing the photoresist to the first dielectric layer; removing the first dielectric layer to expose the gate electrode; removing the photoresist; and performing a second-stage silicidation process using A second silicide metal is fabricated on the gate of the metal-oxide semiconductor transistor. 2 1. The process of item 20 in the scope of patent application, wherein after completing the second stage silicidation process, it further includes performing thermal annealing to reduce the resistance of the first and second silicided metals. Page 18 1220535 6. Scope of Patent Application 2 2. For the process of claim 20 in the scope of patent application, wherein the above-mentioned first dielectric layer includes boron nitride (B N). 2 3. The process of claim 20 in the scope of patent application, wherein the second dielectric layer includes an oxide layer. 2 4. If the process of applying for the scope of patent application No. 20, wherein the temperature of the above thermal annealing is about 800 to 90 (TC. 2 5. If the process of applying for the scope of patent application No. 20, where the above photoresist is It is removed using a chemical mechanical polishing process. Page 19 丄 220535 Positive / none The next step is to perform the fabrication of the spacers using anisotropic etching ^. The spacers 14 are fabricated on the side wall spacers. In this step, a silicon oxide layer is etched to form the side of the oxide / stone structure. On the wall. As shown in the first figure, the gate structure and the partition wall 14 are used as a mask for ion implantation, and ions are used as ions. :::: 4rr; = r is a well-known technology, here = v After the cladding layer 18 is fabricated in the source and drain electrodes, the cladding layer 18 is comprehensive, and has six products: the gate structure, the spacer 14 and the substrate 2. In a preferred embodiment, the conductive layer 18 includes, but is not limited to, titanium or titanium / titanium nitride (Ti / TiN), and then titanium (or titanium / titanium nitride) is subjected to low temperature thermal annealing (anneaUng). ) Reacts with silicon. The gate electrode 8 is covered by the partition wall 4 and the boron nitride (10), so it does not react with the metal, and only the drain / source 2 reacts to form a silicide metal 20 such as titanium silicide. The temperature of the above-mentioned low-temperature thermal annealing is about "between 3 50 and 4 5 (TC.), And the above-mentioned non-reactive conductive layer is selectively removed by a wet etching method, as shown in Fig. 2. See Fig. 1 ' A thin dielectric layer, such as a liner oxide layer (1 iner 〇χ 丨 ^ e) 20, is uniformly deposited on the gate structure and the surface of the substrate 2. Then, a photoresist 22 is coated on the liner oxide layer (1 iner 〇). χ ide) 2 0. Then, the above-mentioned photoresist 22 is polished to a boron nitride (BN) 1 taste surface by a chemical mechanical polishing method, and this boron nitride (BN) 1 0 can be used as the end point detection of the grinding. The results are shown in Figure 3. Using photoresist 2 2 as a barrier and removing the boron nitride (BN) 1 0 by a wet etching process, the upper surface of the gate electrode 8 is exposed. Using boron nitride (BN) 1 0 and the photoresist twenty two Page 10 1220535 9 Amendment / Correction / Completion on the afternoon of June 3rd, 2013. Patent Application Scope of Application Patent Scope: 1. A silicidation metal manufacturing process, including at least: forming a gate dielectric layer on a semiconductor substrate; forming A polycrystalline silicon layer on the gate dielectric layer; forming a first dielectric layer on the polycrystalline stone layer; using a lithography and etching process to etch the first dielectric layer, the polycrystalline silicon layer, and The gate dielectric layer is used to form a gate structure; a lightly doped electrode is formed in the semiconductor substrate; a base is formed on a sidewall of the gate structure; an ion implantation is performed to form a drain and a source A first conductive layer is formed in the semiconductor substrate on the spacer wall, the gate structure and the semiconductor plate; a first thermal annealing is performed to generate the first conductive layer and the drain and source electrodes; Reacting to form a first silicide metal; removing the first conductive layer not participating in the reaction; forming a second dielectric layer on the substrate, the gate electrode and the first dielectric layer; forming a photoresist to cover the second dielectric Above the electrical layer Removing the photoresist to the first dielectric layer; removing the first dielectric layer; removing the photoresist to expose a gate electrode; forming a second conductive layer on the second dielectric layer and the gate electrode; Performing a second thermal annealing to react the second conductive layer with the gate to form a second silicide metal;