TWI220285B - Semiconductor test structure for clarifying the cause of leakage current - Google Patents

Semiconductor test structure for clarifying the cause of leakage current Download PDF

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TWI220285B
TWI220285B TW92116088A TW92116088A TWI220285B TW I220285 B TWI220285 B TW I220285B TW 92116088 A TW92116088 A TW 92116088A TW 92116088 A TW92116088 A TW 92116088A TW I220285 B TWI220285 B TW I220285B
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well
isolation element
test structure
type
doped region
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TW92116088A
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TW200428552A (en
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Wang Zheng
De-Xue Leng
Meng-Jin Cai
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Grace Semiconductor Mfg Corp
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Abstract

The present invention provides a kind of semiconductor test structure for clarifying generation cause of leakage current. The invention contains a well having the first conduction characteristic; and the first isolation device is located in the well. At least the first doped region is located at one side of the first isolation device, and the first doped region has the second conduction characteristic. The second doped region is located in the well that is located at the other side opposite to that of the first isolation region. The second doped region has the first conduction characteristic with its doping concentration larger than that of the well, and is connected externally to a grounding electric-potential. The structure can be used to clarify each kind of leakage current types, for example surface type, field edge type, polysilicon edge type, or gate edge type, caused by junction or oxide layer.

Description

1220285 五、發明說明(1) 【發明所屬之技術領域】 本發明係有關於一種測試結構,用於釐清元件發生問 題之原因,其特別是關於一種半導體測試結構,用於釐清 元件之接合與氧化層之漏電流的問題原因。 【先前技術】 半導體元件通常是由數層電性不同的材料所共同構成 的。當這些材料彼此接觸之後,一些因電性不同所衍生的 現象也隨著發生,這些接觸的結果會影響半導體整個元件 的表現。習知,以接合(j unc t i on)來形容半導體元件材料 間的各種接觸。 利用半導體間的接合,加上外界的施加電壓方式,例 如順向偏壓(forward bias)或逆向偏壓(reverse bias), 使得半導體可以作為開關(switch)、整流器(current rectifier)或放大器(amplifier),甚至將這些整合於一 半導體元件中。 然而,由於電子本身的熱運動、内部或外部電場、以 及外加電壓的作用,造成接合所衍生之遺漏電流(1^^“ current)現象。雖然如此,遺漏電流在習知小整合積集度 (integration)的設計上,是可以被忽略的。但是,當半 導體元件的尺寸快速減少、整合積集度迅速增加的同時, 遺漏電流的存在與發生,便無法忽略。此外,不同半導體 結構間的接合也成為元件良好表現的關鍵之一。但是,存 在於半導體元件内之接合面與遺漏電流有許多的來=,當 半導體元件的表現或性質發生問題時,會造成很難釐清^1220285 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a test structure used to clarify the cause of component problems, and particularly to a semiconductor test structure used to clarify the bonding and oxidation of components The cause of the layer leakage problem. [Previous Technology] A semiconductor device is usually composed of several layers of materials with different electrical properties. When these materials come into contact with each other, some phenomena derived from the difference in electrical properties also occur. The results of these contacts will affect the performance of the entire semiconductor device. Conventionally, j unc t i on is used to describe various contacts between semiconductor device materials. The use of junctions between semiconductors and external applied voltage methods, such as forward bias or reverse bias, enables semiconductors to be used as switches, current rectifiers, or amplifiers ), And even integrate these into a semiconductor element. However, due to the thermal motion of the electrons, the internal or external electric field, and the applied voltage, the leakage current (1 ^^ "current) phenomenon caused by the junction is caused. However, the leakage current is known in the small integrated accumulation degree ( The design of integration) can be ignored. However, when the size of semiconductor elements is rapidly reduced and the degree of integration accumulation is rapidly increased, the existence and occurrence of leakage current cannot be ignored. In addition, the bonding between different semiconductor structures It has also become one of the keys to the good performance of the device. However, there are many joint surfaces and leakage currents existing in the semiconductor device =, when the performance or properties of the semiconductor device have problems, it will be difficult to clarify ^

玉、發明說明(2) 題發生之原因。尤其當發生問題的原因之間存在共通性或 相似性時,更增加發現原因的困難度。 因此,業界通常會設計一些測試結構,來模擬發生問 題之貫際半導體元件5找出問題發生之原因。然而,失當 的結構設計,不但無法協助找出問題的原因,甚之誤導判 斷,增加半導體元件之設計與製造成本。因此,只有正確 的測試結構設計,才能事半功倍,迅速且正確地推斷問題 的原因。 【發明内容】 鑒於上述,本發明的目的之一,係在提供一種結構設 計’用以釐清接合與氧化層之遺漏電流原因,藉由三種蜇 態的設計’正確地反應出發生問題的主要原因。 本發明之另一目的,係在提供一種半導體結構設計, 用於,清接合與氧化層遺漏電流之原因,藉由放大特定原 因的貢獻度,找出發生問題之主要原因。 為達到以上所述之目的,本發明提供一種半導體測試 f構,用以釐清漏電流發生原因,其包含一井具有一第一 ‘電〖生 第一隔離元件位於井中,至少一第一換雜區位Jade and Invention Explanation (2) The reason for the problem. Especially when there is commonality or similarity between the causes of a problem, it becomes more difficult to find the cause. Therefore, the industry usually designs some test structures to simulate the interim semiconductor device 5 where the problem occurs and find out the cause of the problem. However, improper structural design can not only help to find out the cause of the problem, but also mislead the judgment and increase the design and manufacturing cost of semiconductor components. Therefore, only the correct test structure design can do more with less and quickly and correctly infer the cause of the problem. [Summary of the Invention] In view of the above, one of the objectives of the present invention is to provide a structural design 'to clarify the cause of the leakage current of the junction and the oxide layer, and to correctly reflect the main cause of the problem through the design of three states . Another object of the present invention is to provide a semiconductor structure design for clearing the cause of the leakage current of the junction and the oxide layer, and by amplifying the contribution of the specific cause to find out the main cause of the problem. In order to achieve the above-mentioned object, the present invention provides a semiconductor test structure for clarifying the cause of leakage current, which includes a well having a first electrical isolation element located in the well, and at least one first replacement Location

於第一隔離元件之一側,此第一摻雜區具有一第二導電 =j τ 2雜區位於第一隔離元件之相反另一側的井 :區具有第一導電性,且其摻雜濃度大於 井,以及對外連接至一接地電壓。 -體實施例配合所附的圖式詳加說明,當更 谷易瞭解本么明之目的、技術内《、特點及其所達成之功On one side of the first isolation element, the first doped region has a second conductivity = j τ 2. A well located on the opposite side of the first isolation element: the region has a first conductivity and is doped. The concentration is greater than the well and is externally connected to a ground voltage. -The embodiment will be explained in detail with the accompanying drawings. When Gu Yi understands the purpose, the technical characteristics, the features and the accomplishments of this technology,

1220285 五、發明說明(3) 效0 圖號說明: 10 井 12 第一摻雜區域 14 隔離元件 16 第二摻雜區域 18 多晶矽結構 2 0 氧化層 2 2 第一摻雜閘極 【實施方式】 本發明的半導體設計可被廣泛地應用到許多半導體設 :乂一卜f ΐ可利用許多不同的半導體材料製作,當本發明 二例來說明本發明方法時,習知此領域的人士 的步驟可以改€ ’材料及雜質也可替換 i 疑地亦不脫離本發明的精神及㈣。 〜;、,t ’ t 用示意圖詳細描述如下,在詳述本笋明 广例時,表示半導體結構的剖面圖在半導不 的認知。料,在實際的 作為有限定 度的三維空間尺寸。 中應匕a長度、寬度及深 苐1圖為本發明之一;】 剖面示意圖。井1 〇 ’例如一p 接合測試結構的 材中換雜P型離子來完成。隔離利用於;半導體底 結構(Shal low Trench τ ,例如淺溝槽隔離 ch Isolation,阳),位於井 1〇 中。 1220285 五、發明說明(4) 隔離元件1 4可利用習知的方法形. 摻雜區域12,例如一請重摻雜區域在不於加詳述。第-之-側的井1。中,並可連接於—外_ 、t離凡件14 =的。此外,弟二摻雜區域16,例如 域,形成於隔離元件14之相反另—側的井1〇中m 於一外部接地電壓。在此實施例中二换^ μ ^ A & x 1 j Y,弟二摻雜區域1 6盥隔 t 離的’只與井10形成—接合(junction)。、而 測试、、、Q構的^寸為50〇um*500um,但不侷限於此大小)。 一般計算總接合漏電流時,由接合面積、接合長产、 夕=邊緣長度與接觸數目和各自的漏電流乘積相加^到 ^因此’第1圖的結構設計’放大接合面積效應,針對接 δ面積所導致之漏電流為主要漏電流發生原因,1220285 V. Description of the invention (3) Effect 0 Description of drawing number: 10 well 12 First doped region 14 Isolation element 16 Second doped region 18 Polycrystalline silicon structure 2 0 Oxide layer 2 2 First doped gate [Embodiment] The semiconductor design of the present invention can be widely applied to many semiconductor devices: 乂 一 卜 f ΐ can be made using many different semiconductor materials. When two examples of the present invention are used to illustrate the method of the present invention, the steps of those skilled in the art can Modifications of materials and impurities can also be replaced without doubt, without departing from the spirit and spirit of the present invention. ~ ,,, t 't is described in detail with a schematic diagram as follows. In detailing this broad example, the cross-sectional view of a semiconductor structure is semi-conducting. Material, in actual, as a limited three-dimensional space size. The length, width, and depth of the middle shovel are shown in Figure 1. This is one of the inventions; Well 10 'is done, for example, by replacing the P-type ions in a p-bonded test structure. Isolation is used; the semiconductor bottom structure (Shal low Trench τ, such as shallow trench isolation ch Isolation, Yang), is located in the well 10. 1220285 V. Description of the invention (4) The isolation element 14 can be formed by a conventional method. The doped region 12, for example, a heavily doped region, will not be described in detail. Number-of-side of well 1. And can be connected to — 外 _, t Lifan 14 =. In addition, the second doped region 16, such as a region, is formed in the well 10 on the other side of the isolation element 14 at an external ground voltage. In this embodiment, ^ μ ^ A & x 1 j Y, the second doped region 16 separated by t ′ is formed only with the well 10-junction. The size of the test structure is 50um * 500um, but it is not limited to this size). Generally, when calculating the total joint leakage current, the joint area, joint long-term yield, and the product of the edge length and the number of contacts and their respective leakage currents are added to ^. Therefore, the 'Structure Design of Figure 1' enlarges the joint area effect. The leakage current caused by δ area is the main cause of leakage current.

試的。 个疋ΤΓ /只JTry it.疋 ΤΓ / J only

第2圖為本發明之一場緣型(field edge type)接合測 試結構的剖面示意圖。與第!圖相似,若干隔離元件"位 於井10中:若干第一摻雜區域12,例如一N型重摻雜區域 ,形成於隔離7G件1 4之一側的井1 〇中,且任兩個第一摻雜 區域12之間由隔離元件14間隔,並且每個第一摻雜區^12 可連接於一外部正伏特,例如+ 3 · 6伏特的電壓。此外,第 二摻雜區域16,形成於隔離元件η之相反另一側的井1〇中 ’並可連接於一外部接地電壓。在此實施例中,第二摻雜 區域16與隔離元件14是相鄰的,同時與隔離元件14與井 皆形成接合。而測試結構的尺寸為5um*5〇〇U[n,數目為5〇〇 條’但不侷限於此大小及數目。這樣的結構設計,放大接Figure 2 is a schematic cross-sectional view of a field edge type junction test structure according to the present invention. With Cap! The figure is similar, and several isolation elements are located in the well 10: several first doped regions 12, such as an N-type heavily doped region, are formed in the well 10 that isolates one side of the 7G part 14 and any two The first doped regions 12 are separated by an isolation element 14, and each of the first doped regions 12 can be connected to an external positive volt, for example, a voltage of + 3.6V. In addition, the second doped region 16 is formed in the well 10 on the opposite side of the isolation element η and can be connected to an external ground voltage. In this embodiment, the second doped region 16 is adjacent to the isolation element 14 and forms a joint with both the isolation element 14 and the well. The size of the test structure is 5um * 500U [n, the number is 500 bars', but it is not limited to this size and number. Such a structural design, enlarged connection

第8頁 1220285Page 8 1220285

合邊緣效應乂針對接合邊緣所導致之漏電流為主要 發生原因,來進行測試的。 參照第3圖為本發明之—多晶緣型(p〇ly edge “Μ) 接合測試結構的剖面示意圖。與第丨圖類似的,第二摻雜 區域1 6與隔離元件1 4是分離的。與第2圖類似的,含有若 干個第一摻雜區域12,但任兩個第—摻雜區域12之間/以 位於井1 0上之若干個多晶矽結構丨8相間隔,並且每個第一 摻雜區域12可連接於一外部正伏特,例如+ 3· 6伏特的電壓 。這樣的結構設計,放大多晶矽邊緣效應,針對多晶矽邊 緣於多晶矽蝕刻時所導致之漏電流為主要漏電流發生原因 ,來進行測試的。 接著,第4圖為本發明之一面型氧化層測試結構的剖 面示意圖。與第1圖類似的是,第一摻雜閘極22,例如一N 型重摻雜閘極,形成於隔離元件14之一側的井1〇上,並可 連接於一外部負伏特,例如—3· 6伏特的電壓。第二摻雜區 域16,例如一p型重摻雜區域’形成於隔離元件14之相反 另側的井1 〇中’並可連接於一外部接地電壓。此外,一 氧化層2 0介於第一摻雜閘極2 2與井1 0之間。 一般計算總氧化層漏電流時,由氧化層面積、氧化層 長f、氧化層邊緣長度與接觸數目和各自的漏電流乘積相 加侍到二因此,第4圖的結構設計,放大氧化層面積效應 針對氧化層面積所導致之漏電流為主要漏電流發生原因 ’來進行測試的。 參照第5圖為本發明之一場緣型氧化層測試結構的剖Joint edge effect: The leakage current caused by the joint edge is the main cause for testing. Referring to FIG. 3 is a schematic cross-sectional view of a poly edge (M) junction test structure of the present invention. Similar to FIG. 丨, the second doped region 16 and the isolation element 14 are separated. Similar to FIG. 2, it contains several first doped regions 12, but any two first-doped regions 12 are spaced apart / spaced by several polycrystalline silicon structures located on the well 10 and each The first doped region 12 may be connected to an external positive volt, for example, a voltage of +3.6 volts. This structure design amplifies the polysilicon edge effect, and the leakage current caused by the polysilicon edge during polysilicon etching is the main leakage current. The reason is to perform the test. Next, FIG. 4 is a schematic cross-sectional view of a planar oxide test structure according to the present invention. Similar to FIG. 1, the first doped gate electrode 22, such as an N-type heavily doped gate The electrode is formed on the well 10 on one side of the isolation element 14 and can be connected to an external negative volt, for example, a voltage of -3.6 volts. The second doped region 16, such as a p-type heavily doped region ' The well 1 formed on the opposite side of the isolation element 14 And can be connected to an external ground voltage. In addition, an oxide layer 20 is between the first doped gate electrode 22 and the well 10. In general, when calculating the total oxide layer leakage current, the oxide layer area and oxidation The layer length f, the oxide edge length, the number of contacts, and the product of the respective leakage currents add up to two. Therefore, the structure design in Figure 4 enlarges the oxide area effect. The leakage current caused by the oxide area is the main leakage current. Cause 'to test. Refer to Figure 5 for a cross-section of a field-edge oxide test structure of the present invention.

122〇285 五、發明說明(6) 乂面示思圖。若干隔離元件14位於井1〇中,其上覆蓋一層氧 20與第一摻雜閘極22,第一摻雜閘極22並可連接於一 ,負伏特,例如-3· 6伏特的電壓。第二摻雜區域]6,形 ^於隔離元件1 4之相反另一側的井i 〇中9並可連接於一外 ^接地電壓。在此實施例中,第二摻雜區域〗6與隔離元件 =是相鄰的,同時與隔離元件i4與井i〇皆形成接合。這樣 ^構設H大氧化層邊緣效應’針對氧化層邊緣所導 之漏電流為主要漏電流發生原因,來進行測試的。 ^參照第6圖為本發明之一閘極緣型(gate edge type) 2化層測試結構的剖面示意圖。與第3圖類似的,第二摻 =域16與隔離元件14是分離的。含有若干個第一換雜區 或12,但任兩個第一摻雜區域12之間,以位於井1〇上之若 干個多晶碎結構18盘氣化®? η相眩 w > /、乳化層相間隔,並且每個多晶矽結 ^ 於外部負伏特,例如一3 · 6伏特的電壓。這樣 箱所導致之漏二 电肌馮主要漏電流發生原因,來進行測 咸的。 本济=用K漏電流與接觸的數目多寡也有關係,因此 本月利用上述測試結構t清接合或氧化層漏電流發 因日守,亦可設計接觸數目不同的測試結構,例如一:式 結構具有較少數目的接觸’另一種則具有較多&目的接: ’如此達到釐清接觸數目所造成漏電流之效應。 因此,本發明提供_ _ + 電流發生原因,其包含_P剞并,皆 m用以厘Μ馮 3 Ρ型井 第—隔離元件位於Ρ型122〇285 V. Description of the invention A plurality of isolation elements 14 are located in the well 10, and are covered with a layer of oxygen 20 and a first doped gate 22, and the first doped gate 22 may be connected to a negative voltage, such as a voltage of -3.6 volts. The second doped region] 6 is shaped in a well i0 on the opposite side of the isolation element 14 and can be connected to an external ground voltage. In this embodiment, the second doped region 6 is adjacent to the isolation element =, and at the same time forms a joint with the isolation element i4 and the well i0. In this way, the H-large oxide layer edge effect is constructed to test the leakage current induced by the edge of the oxide layer as the main cause of the leakage current. ^ Refer to FIG. 6, which is a schematic cross-sectional view of a gate edge type 2 layer test structure according to the present invention. Similar to FIG. 3, the second doped domain 16 is separated from the isolation element 14. Contains several first doped regions or 12, but between any two first doped regions 12, with several polycrystalline broken structures 18 disks located on the well 10 gasified?? Η phase glare w > / The emulsified layers are spaced apart, and each polycrystalline silicon is connected to an external negative volt, such as a voltage of 3.6 volts. The leakage caused by this box is the main reason for the leakage current of the electric muscle Feng to measure the salt. Capital = The leakage current with K is also related to the number of contacts, so this month using the above test structure t to clear the junction or oxide layer leakage current due to the day, you can also design test structures with different numbers of contacts, such as: Have a smaller number of contacts 'and the other has more & purposes:' This is to clarify the effect of leakage current caused by the number of contacts. Therefore, the present invention provides the cause of the _ _ + current, which includes _P, and is used to make the von 3 P-type well. The first-isolation element is located in the P-type.

第10頁 五、發明說明(γ) 井中,至少一Page 10 V. Description of the invention (γ) In the well, at least one

型重換雜 i推雜區位於第一隔離元件之一側’及一 P 型重離元件之相反另一側的p型井中,p 地電壓。 ^雜展度大於Ρ型井’以及對外連接至一接 r ,i上所迹之實施例僅係為說明本發明之技術思想及特 j =目t在使熟習此項技藝之人士能夠瞭解本發明之内 谷並據以實施,當不能以之限定本發明之專利範圍,即大 ^依本發明所揭示之精神所作之均等變化或修飾,仍應涵 蓋在本發明之專利範圍内。The re-doped region is located on one side of the first isolation element 'and a p-type well on the opposite side of the P-type re-isolated element, with p ground voltage. ^ The degree of miscellaneous spread is greater than that of the P-type well ', and the external connection to a connection r, i is only for explaining the technical ideas and features of the present invention. The purpose is to enable those skilled in the art to understand this technology. The inner valley of the invention is implemented accordingly. When the scope of the patent of the present invention cannot be limited by it, that is, equivalent changes or modifications made in accordance with the spirit disclosed by the present invention should still be covered by the scope of the patent of the present invention.

第11頁 1220285 圖式簡單說明 —_ 第1圖為本發明之一 的剖面示意圖。 面型(area type)接合測試結構 第2圖為本發明^^ _ 測試結構的剖面示意圖y琢緣型(field edge type)接合 弟3圖為本發明夕_ 測試結構的剖面示意圖了夕日日緣型(P〇iy edge type)接合 第4圖為本發明少 圖。 β之一面型氧化層測試結構的剖面示意 弟5圖為本發日月夕 意圖。 乃之一场緣型氧化層測試結構的剖面示 第6圖為本發明夕_ 層測試社糂沾立丨 一閘極緣型(gate edge type)氧化 j °式結構的剖面示意圖。Page 11 1220285 Brief description of the drawings —_ Figure 1 is a schematic cross-sectional view of one of the present inventions. Area type joint test structure Figure 2 is a schematic cross-sectional view of the test structure ^^ _ Field edge type joint test chart 3 is an evening view of the invention Poiy edge type joint Fig. 4 is a diagram of the present invention. The cross-section of a beta-type oxide test structure is shown in Figure 5. A cross-sectional view of a field-edge oxide layer test structure. Figure 6 is a schematic cross-sectional view of a gate edge type oxide j ° structure of the present invention.

第12頁Page 12

Claims (1)

A^U285 六、申請專利範圍 1 · 一種半導體 測試結 半導體測試結構包 一井具有一第一導 一第一隔離元件位 至少一第一摻雜區 一摻雜區具有_ 一第二摻雜區位於 井中,該第二摻 濃度大於 如申請專利 第一摻雜區 (junction) 該井, 範圍第 位於該 ’可用 構,用以釐清漏電流發生原因,# 含: ^ 電性; 於該井中; 位於該第一隔離元件之一側,I亥第 第二導電性;及 該第一隔離元件之相反另一側的兮 雜區具有該第一導電性,且其摻牵隹 以及對外連接至一接地電壓。 1項所述之半導體測試結構,當該 井中,與該井形成一接合 以釐清接合部分的漏電流發生原因 3 ·如申請 該弟二 成一接合 4 ·如申請 該第二 及同時 5 ·如申請 一步包 個第一 離元件 6 ·如申請 ^利範圍第2項所述之半導體測試結構,其中 雜區與該第一隔離元件分離,單獨與該井形 Ο =範圍第2項所述之半導體測試結構,其中 : = 第一隔離元件相鄰形成-接合I /、該井形成一接合。 專利範圍第2項所述之半導辦、、日丨^ 含彼此分離的該複數個第一摻雜構’ *進 摻雜區之間以一第二隔離元日二:亥, 位於該井中。 隔。亥弟一隔 專利範圍第5項所述之半導髀 亍守體須I]試結構,其中A ^ U285 6. Application Patent Scope 1. A semiconductor test junction semiconductor test structure package with a well with a first conduction and a first isolation element at least one first doped region and one doped region with _ one second doped region Located in the well, the second doping concentration is greater than that of the well in the first doped region of the patent application, the range is located in the 'available structure' to clarify the cause of the leakage current, # contains: ^ electrical; in the well; A second conductivity is located on one side of the first isolation element, and a second conductive region on the opposite side of the first isolation element has the first conductivity, and is doped with ions and externally connected to a Ground voltage. In the semiconductor test structure described in item 1, when the well forms a joint with the well to clarify the cause of the leakage current at the joint part 3 · If you apply for the brother 20% joint 4 · If you apply for the second and simultaneous 5 · If you apply One step of the first separation element 6 · The semiconductor test structure described in the second item of the application, wherein the impurity region is separated from the first isolation element, and separate from the well shape 0 = the semiconductor test described in the second item of the range Structure, where: = the first isolation element is formed adjacently-the joint I /, and the well forms a joint. The semi-conductor described in the second item of the patent scope includes the plurality of first doped structures that are separated from each other, and is located between the doped regions with a second isolation element. . Interval. One of the semi-conducting devices described in Item 5 of the patent scope, the guard body must have a test structure, in which 第13頁 ^20285 六、申請專利範圍 14 16 17 18 :以利範圍第丄項所述之半導體測試結構,其中 弟 V電性與該第二導電性相反。 :ί ί導體測試結構,用以釐清漏電流發生原因,該 +導體測試結構包含: 一ρ型井; 一第一隔離元件位於該Ρ型井中; ^少一Ν型摻雜區位於該第一隔離元件之一側丨及 - ρ =摻雜區位於該第一隔離元件之相反另二側的 =51井中,該ρ型重摻雜區的摻雜濃度大於該卩型 开’以及對外連接至一接地電壓。 :型申Λ#「利範圍第15項所述之半導體測試結構,當該 生払雜區位於該Ρ型井中,與該ρ型井形成一接人 C卿ctlGn),可用以釐清接合部分的漏電流發生口原因 t申請專利範圍第16項所述之半導體測試結構, ΪΛ重一摻接雜合區與該第一隔離元件分離,單獨與該ρ型 t申Λ專利範圍第16項所述之半導體測試結構,盆中 生重摻雜區與該第一隔離元件相鄰形一 〃, 以及同時與該ρ型井形成一接合。 口’ 如申請專利範圍第1 6項所述之半導體蜊試結合 步包含彼此分離的該複數個N型摻雜區時田 個N型摻雜區之間以一第二隔離元件相隔;㈣= 19 1220285Page 13 ^ 20285 6. Scope of patent application 14 16 17 18: The semiconductor test structure described in item (1) of the scope of benefit, in which the electrical conductivity of the secondary V is opposite to the second conductivity. : ί The conductor test structure is used to clarify the cause of leakage current. The + conductor test structure includes: a ρ-type well; a first isolation element is located in the P-type well; ^ at least one N-type doped region is located in the first One side of the isolation element and-ρ = doped region is located in the well of the opposite side of the first isolation element = 51, the doping concentration of the ρ-type heavily doped region is greater than that of the 卩 -type opening and the external connection to A ground voltage. : Type Shen Λ # "The semiconductor test structure described in item 15 of the scope of interest. When the heterogeneous region is located in the P-type well, it forms an accessor CtlGn with the ρ-type well. The reason for the leakage current t is to apply for the semiconductor test structure described in item 16 of the patent scope. The ΪΛ heavy hybrid region is separated from the first isolation element, and is separate from the ρ-type t application. In the semiconductor test structure, the raw heavily doped region in the basin is adjacent to the first isolation element, and simultaneously forms a joint with the p-type well. 口 'Semiconductor clams as described in item 16 of the scope of patent application The trial combining step includes the plurality of N-type doped regions separated from each other. The second N-type doped regions are separated by a second isolation element; ㈣ = 19 1220285 第17頁Page 17
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