TW594968B - Fully silicided NMOS device for electrostatic discharge protection - Google Patents

Abstract

A device and method are described for forming a grounded gate NMOS (GGMNOS) device used to provide protection against electrostatic discharge (ESD) in an integrated circuit (IC). The device is achieved by adding n-wells below the source and drain regions. By tailoring the dopant concentration profiles of the p-well and n-wells provided in the fabrication process, peak dopant concentrations are moved below the silicon surface. This moves ESD conduction deeper into the IC where thermal conductivity is improved, thereby avoiding thermal damage occurring with surface conduction. The device does not require a salicidation block or additional implantation and uses standard NMOS fabrication processing steps, making it advantageous over prior art solutions.

Description

594968 V. Description of the invention (1) (1) [Technical field to which the invention belongs] The present invention relates to the manufacture of semiconductor devices, and more particularly to an NMOS device formed by electrostatic discharge (ESD) protection during the manufacture of integrated circuits Method. (II) [Previous Technology] Integrated Circuits (ICs) are susceptible to damage known as electrostatic discharge (esd), which occurs when large electrostatic charges accumulate on their ^ ^ pins during component transmission and processing. ^ 1). If the control is improper, ESD will irreparably damage 1C, just like the dissipation of power during the large-scale temperature gradient caused by the discharge in the component structure. Another problem that solves ESD is the silicon controlled rectifier (SCR) connected to 1 (: near the external chat pad). When the voltage on the pad due to static charge reaches a level that exceeds normal operation, the SCR is turned on, thereby Provides a low-resistance path for discharge and protects the element by using this circuit for circuits in normal operation. There are several methods using scr, US Patent No. 5,369,041 (1) 1 ^ ¥ 11. ) Teaches a method of ESD protection and establishing SCR in MOS process. U.S. Patent No. 5,728,61 No. 2 (Wei et al.) Teaches a method for improving the performance of ESD protection. When opening the element, it is necessary to increase the size of the SCR by making it in the core. US Patent No. 5,843,81 3 (^ 丨 etc.) teaches another method to improve the ESD protection performance of SCR, which also reduces component switching noise. &Amp; Elements also use deeper contact windows, which reduces 594968 when turned on 5. Description of the invention (2) Resistance of SCR. The second method of RSD protection is to use a gate-grounded thin oxide layer (GGNMOS) element to provide a low-resistance discharge path. This is the protection method of the present invention. Now referring to Fig. 1, which shows a cross-sectional view of a typical GGNM0s element, it can be understood that none of the parts in Fig. 丨 are conventional techniques of the present invention. More precisely, this simple diagram Provide a result, provide an improvement, overcome the problem by the present invention, provide a P-type well region or substrate 10, a gate oxide layer 28 overlies the p-type well region or substrate 10, a polycrystalline silicon gate The electrode 30 is connected to the gate oxide layer 28 to provide n + drain and source (14 and 22). A drain electrode 18 is electrically connected to the drain 14 and a source electrode 26 is electrically connected. Connected to source 22, source electrode 26 is connected to gate electrode 30, both of which are connected to ground (as shown in Figure 1), or to 1 (: the most negative voltage potential used, for this The description of the operation of the element is to ground the source electrode 26 and the gate electrode. What is not shown in the figure is also to ground the p-type well area or the substrate 10. In order to use active NMs on 1C A better electrical contact is provided in the device, as shown in FIG. 1, on the n + drain 14 and source 22 Self-aligning silicidation treatment is performed on the surface. Unfortunately, due to localization of the discharge current, self-aligning lithography will reduce the ESD protection performance of GGNM0s elements. US Patent No. 6, 1 00, 1 25 (Hu If actor, etc.) teaches an ESD protection method using a GGNMOS device, which modifies the drain contact window in the device to reduce its conductivity. 'This will change the lightly doped drain (LDD) region and use a mask. This is achieved by preventing the self-aligned silicidation of the drain region. The crash mechanism provides ESD protection in the GGNMOS device.

594968 V. Description of the invention (3) With reference to Figure 1, those mechanisms will now be described. If the voltage on the drain electrode i 8 is slightly increased to exceed the ground potential, the diode formed by the P-type well region 10 and the drain well region will be reverse biased, and an empty region will be formed between the two. between. A second empty region exists between the source region 12 and the p-type substrate or well region 10 under the gate 30. This barrier retains the electrons in the source region 22. Any flowing current is due to Leakage current in biased electrodeless / p-well junction. If the voltage of the dead electrode 18 is increased, the empty region between the p-type substrate or the well region 10 and the drain region will become wider, and it will be moved closer to the source region 22. When the voltage on the electrodeless electrode 18 will cause the drain empty region to contact the source empty region, the connection between the two empty regions will have a low resistance, and the result will be a very high Current, this phenomenon is called "penetration", and the resulting current is called "penetration current". A typical curve of a typical NMOSFET penetration phenomenon is shown in Figure 2. It is known that the nonpolar diode collapses. The second phenomenon is shown in Figure 2. Before the pole-diode collapses, the actual reverse-biased pole-junction current will not saturate. This is due to the hole generated when the diode is reverse-biased t Yes, an argument is always left in the ideal diode equation. Soft collapse is a conduction phenomenon caused by excessive hole pairs. If the electric field reaches a critical level for a hard breakdown, a small increase in the drain voltage will cause a very large increase in current. Figure 3 shows a l-to-I pattern with different source-to-drain well spacings. As the gap decreases, the leakage IDS will increase. This happens because, for example, the two empty regions move closer to each other. , Which leads to the field penetration from the drain to the source. The potential barrier on the source is decreasing, which leads to an increase in the emission of electrons generated by the source, ... the Ids increase.

594968 V. Description of the invention (4) The electrode causes a decrease in the surface potential (DIBL). Furthermore, increasing the IDS will result in empty areas, resulting in penetration. In some cases, a different phenomenon called snapback occurs before the penetration voltage is reached. The present invention uses rebates to provide ESD protection. This phenomenon will be discussed in the detailed description of the present invention. (2). [Summary of the Invention] The main object of the present invention is to provide a semiconductor element, which is to provide electrostatic discharge (ESD) protection. ^ Another object of the present invention is to provide a semiconductor element, which is to provide Electrostatic discharge point (ESD) protection without the need for additional process steps. ', ^ Another object of the present invention is to provide a semiconductor device that provides electrostatic discharge (ESD) protection, which does not need to be aligned to the silicon chemical Blocking step. Another object of the present invention is to provide a semiconductor device that provides electrostatic discharge (ESD) protection, which does not require an additional cloth and ESD protection. Yet another object of the present invention is to The purpose is to provide a semiconductor device, the complex system provides electrostatic discharge (ESD) protection, and the system has a trigger point far from the semiconducting surface. It was obtained by a process under the well region J and the drain region in the GGNMOS device, and the n / p region and the p-well region were modified so that the peak concentration of the well region would be far away from the silicon surface: Will reduce the ambiguity between the source of p and η wells ::: 生 '

Page 8 594968

The increased electric field in the reverse-biased n-well and p-well zones will cause a relatively large current. This ejects more holes into the p-well area to generate a potential / forward biased p-well area / n-well area source junction, and the effect is an effective conducting double carrier. N pn transistor, the low resistance between the pole, Ό electrode quickly removes any electrostatic charge, and conducts away from the surface of silicon, which is where the power has been effectively depleted. (4), [Detailed description of the preferred embodiment] The present invention uses an ESD protection method, which uses a ~ gate NMOS (GGNMOS) element to provide a low-resistance discharge path, and the money region is added to the GGNM0S element Under the source and drain regions, it is to modify the doping profile of the n-well ^ source. The foldback system is used to provide ESD protection. As v2 increases, the potential barrier on the source of the η well area decreases due to the DIBL effect, and the hole pair generated in the empty area of the drain well area also appears. And with the increase of VDS, this result will cause a higher electric field and a higher hole to generate current. This hole current will be injected into the p-well area, and the source of the p-well area / n-well area will be biased forward. Facing surface. The DIBL effect contributes to this by reducing the potential barrier on the source of the n-well region. Once the "well area source junction surface of p-well area is forward biased, this element acts as an NpN transistor, and its drain Ϊ 'generates a low-resistance discharge path. Advanced manufacturing process and LDD junction surface, This conduction trigger is close to the surface of the element, which is at the place where the heat conduction is not good, and the surface will cause damage to the element. Now referring to FIG. 4, it shows a cross-sectional view of the GGNM0s element of the present invention. Well area 10, n well areas 12 and 20 are formed at p

594968 V. Description of the invention (6)-A gate oxide 28 is patterned in the type substrate or well area 10, and is covered on the p-type substrate or well area 10 and !! Wells 12 and 20 are on. A polycrystalline silicon gate electrode 30 is formed on the gate oxide 28 overlying the n-well regions 12 and 20. Lightly doped drain (LDD) regions (15 and 23) are formed by light-weight implantation, and the light-weight implantation uses polycrystalline silicon gate electrode 30 as a mask, and oxide spacers 16 and '17 are formed on On the sidewall of the polysilicon gate electrode 30, those oxide spacers 16 and 17 along the polysilicon gate electrode 30 form a mask for η + source and drain regions 14 and 22, respectively. . The drain electrode 18 is electrically connected to the drain electrode 14 'and the source electrode 26 is electrically connected to the source electrode 22. The source electrode 26 is connected to the gate electrode 30, and both of them are connected to the ground (as shown in FIG. 4), or to the most negative voltage potential used by 1C. For the description of the operation of this element, the source electrode 26 and the gate electrode 30 are grounded, and the p-type substrate or well area 10 is also grounded (not shown in the figure). In order to provide a better electrical contact window in the active NMOS device at 1 (:), as shown in FIG. *, Self-aligned silicidation treatment is performed on the upper surfaces of n +, electrode 14, and source electrode 22. The η well regions 12 and 20 and the P-type substrate or well region 10 are modified so that the peak / degree of the peak reaches a point from the semiconductor surface between 0.5 and 1 · 5 // m. This peak is equivalent to the minimum drain The polar space has a wide width, and it is at the point where the conduction will be triggered to avoid triggering the semiconductor surface, to improve the heat conduction at this thicker peak concentration point. Use 9 X 1012 to 5 X 1013 ions / cm2 (nominal is 2 × 1013inns / cm2) and phosphorus ion implantation at an implantation energy of 400 to 650KeV (nominally 500KeV), forming η well zones 12 and 20, and this planting system Before implantation in the ρ well area and before the shallow trench isolation process, two boron ions are implanted to form a ρ-type substrate or well area 1 〇, one with a range of 7 χ 1 〇12 to 4 χ

594968 V. Description of the invention (7) The implantation energy between the dose of 400KeV (nominal 30KeV) between 1013ions / cm2 (nominal j χ 1〇i3i〇ns / cm2), the second p-well area The implants have a dose between 1 X 1 〇12 and 1 χ 1 〇13 i 〇ns / cm2 (nominal between 4.5 χ and between 100 and 25 keV (nominal 15 keV ), The two planting systems were carried out before the oxide process in the η well area. Junjima ^ Figure 5 shows the results of the present invention, including the rebate phenomenon, with increasing VDS, only the leakage current rises to 6.2 watts. Once it reaches this value, a reversal phenomenon will occur and it will be immediately reduced to 4.3 watts. The negative resistance area will be detected because it is effective to multiply more charge carriers . Modify the impurity distribution so that the retracement occurs before penetration. ^ Figure 6 shows the doping distribution of the η well area of the present invention, one in the range of 1 x 5 to 8 x 8 atoms / cm3 (nominal It is a peak concentration between 7χ 1〇17), which will occur at 0.5 to 1.5 / zm (nominal 0.75) in Table 1C. The doping distribution in the η well area is determined by the dose 2 χ i (Pi〇ns / cm2 It is formed by implanting phosphorous ions at an energy of 500 KeV plus some threshold (Vt) and penetrating implantation. Figure 7 shows the doping distribution of the p-well region of the present invention, one at 1 X 1 0π to 5 χ 1018 atoms / cm3 (nominal peak concentration between 7 χ 1 (F), will occur from 0.5 to 1.5 // m (nominal 0.6 / zm) from the IC surface. P well area doping The heterogeneous distribution is by a dose of 1 × 10i3ions / cm2 and an energy of 300KeV, by a dose of 4.51 X 1012iSn / cra2 and an energy of 150KeV, plus some threshold (vt) and penetration The implantation is formed by implanting boron ions. Several important differences between the present invention and U.S. Patent No. 5,728,61 2 (Wei et al.) Should be mentioned. The patents of Wei et al. Use η in SCR elements. 594968 V. Description of the invention (8) to increase the conduction volume, which will reduce the hot light point and improve the UD well retention. ^ The invention uses a GGNM0S element, and uses the modified 11 well area and p to reduce the distribution. The conduction is removed from the surface, and the ESD trigger is adjusted. In these important points, the two elements and their operating methods are different. The present invention uses a process, which The n-well area is added to the source and drain regions of the Fenfanfan. Modifying the η-well area and the ρ-well area will reduce the doping = the peak concentration of the well area will occur far away from the surface. This result: Pole？: and the empty barrier between the source of the η well area. In addition, with the north θ ϋ, an increased electric field is formed between the forward bias η well area and the poles, and This causes a higher hole to generate a current, which injects more people into the well area to generate a potential, which will be along the Shun area / η well (the result is a type with a drain (collector) and a source. The low-resistance conductive bipolar NPN transistor is connected between silicon and silicon. This conduction will be generated in the silicon watch, which can be effectively dissipated by moving the power of static charge. a However, the present invention has been specifically shown with reference to its preferred embodiments and said: those skilled in the art should understand that various changes in form and detail can be made without departing from the spirit and scope of the present invention . Brief description of drawing number: ίο ρ-type substrate or well region 12 η well region 14 Drain electrode Page 12 594968 V. Description of the invention (9) 15 Lightly doped drain (LDD) region 16 Oxide spacer 17 Oxide gap Wall 18 Drain electrode 2 0 η well region 22 Source 23 Lightly doped drain (1 ^ 0) region 2 6 Source electrode 28 Gate oxide

Chapter 30 Polysilicon Gate Electrode Ends

Page 13 594968 Brief Description of Drawings Figure 1 shows a cross-sectional view of a typical grounded gate NMOS (GGNMOS) device. Figure 2 shows a diagram of a GGNM0S element IDS aVDS. Figure 3 is a graph showing different well-to-drain well spacings. Fig. 4 is a cross-sectional view showing a grounded gate NMOS (GGNMOS) device according to the present invention. Figure 5 shows the test results of the present invention including the phenomenon of snapback (sn a p b a c k). Figure 6 shows the doping profile of the n-well region of the present invention. Figure 7 shows the doping profile of the p-well region of the present invention.

Claims (1)

594968 VI. Application Patent Scope-*-1 · A component that dissipates static charge in an integrated circuit, including a · P region, which is in a semiconductor substrate; a source n well region and a drain n The well region is connected to the p region; the gate oxide covers the p region, which is in the gap between the source ri well region and the gap between the well and the η well; η + source region and a η + Drain region, which is in the source n well region and / or the pole 11 well region, respectively, wherein the surfaces of the n + source region and the n + drain region are silicided; a lightly doped source region And a lightly doped drain, which are respectively in the source n-well region and the non-n-well region; a gate electrode is overlaid on the gate oxide; a dielectric layer is overlaid on the A gate electrode and the source and drain regions; and a conductive contact window passes through the dielectric layer to the silicided η + source region and the silicided η + drain region 'and is electrically connected to the gate electrode to the Shi Xihua's η + source is used to complete the device manufacturing for dissipating static charges. 2. The element according to item 1 of the patent application range, wherein the ρ region has a peak concentration having a depth between 0 · 5 and 1 · 5 // m. 3. The element according to item 2 of the patent application range, wherein the peak concentration in the ρ region is between 1 X 1 01? And 5 X 1 O18 a toms / cm3. 4. The element according to item 3 of the scope of the patent application, wherein the peak concentration in the ρ region is formed by a double distribution of boron ions, one distribution is at a dose of 7 X ιο2 to 4 X 1013i〇ns / cm2 (nominal 1 X ι〇ΐ3 ions / cm2) and energy between 250 and 400KeV (nominal 30 0KeV), the other cloth value is 1 X 1012 to 1 X 1013i〇ns / cm2 (nominal is 594968 VI. The scope of patent application (4.5 × 1012 ions / cm2) and the energy between 100 and 25 OKeV (normally 150 KeV), as well as the threshold value and penetration cloth value. 5. The element according to item 1 of the scope of the patent application, wherein the source n-well region and the drain n-well region have a peak concentration between 0 · 5 and 1 · 5 // m. 6. The element according to item 5 of the scope of the patent application, wherein the peak concentration in the source n well region and the drain n well region is between 1 X 1 (F to 5 X 1018 atoms / cm3 〇7. The element according to item 6 of the scope of patent application, wherein the peak concentration in the η well area is formed by the distribution value of phosphorus ions, and the distribution value is between 9 X 1 012 and 5 X 1 〇13 i 〇ns / cm2 (nominal 2 X 1 013 i ons / cm2) and energy between 400 and 650KeV (normally 500KeV), and the threshold value and penetration cloth value. An element for dissipating static charges in an integrated circuit includes: a P region in a semiconductor substrate; a source n-well region and a drain n-well region in the p region; a gate An oxide covers the ρ region, which is in the source n-well region and the gap between the drain and the n-well interval; a n + source region and a n + drain region, which are respectively at the source In the η well region and the drain η well region, the peak concentration 'of the source ν well region and the drain η well region will occur between 0.5 and 1.5 // m, and the η is silicified. + Source region and the η + non-polar region Surface; a lightly doped source region and a lightly doped drain, which are based on the well source region and the η η polar not well region; Page 16 594968 6 'Application for Special Relay 1' --- A gate electrode is overlaid on the gate oxide; " An electrical layer is overlaid on the gate electrode and the source and non-electrode regions And the conductive contact passes through the dielectric layer to the fragmentation η + source region and the fragmentation ^ + and electrode region, and electrically connects the gate electrode to the lithium oxide + source, thereby The manufacture of the element for dissipating static charges is completed. 9. The element according to item 8 of the patent application range, wherein the ρ region has a peak concentration having a depth between 0.5 and 1.5m. 10. The element according to item 9 of the scope of patent application, wherein the peak concentration in the ρ region is between 1 X 1 0i7 to 5 X 1 0 18 a toms / cm3. 11 The element as described in the item No. 丨 0 of the patent application range, wherein the peak concentration in the ρ region is formed by the double cloth value of boron ions, one cloth value is at a dose of 7 × 10 2 To 4 X 1013ions / cm2 (nominal 1 X 1〇13 ions / cm2) and energy between 250 and 400KeV (normally 300KeV), the other cloth value is between 1 X 1 012 to 1 X 1 〇13 i ons / cm2 (nominal 4.5 x 1012ions / cm2) and energy between 100 and 250 KeV (nominal 150 KeV), and the threshold value and penetration cloth value. 1 2 · The element according to item 8 of the scope of the patent application, wherein the peak concentration in the source n region and the drain n well region is between 1 X 1 017 and 5 X 1 〇18 atoms / cm3. Time 0 1 3 The element according to item 12 of the scope of the patent application, wherein the peak concentration in the source n well region and the drain n well region is formed by the distribution value of phosphorus ions, one distribution value For doses between 9 X 1 012 to 5 X 1 013 ions / cm2 (nominal 2 X 1013 ions / cm2) and energy between 400 and 650 KeV (nominal 500 KeV), and Limits and penetration values. Page 17 594968 14. · A method of forming an element for dissipating an electrostatic charge in an integrated circuit, comprising: providing a semiconductor substrate; providing a ρ region in the semiconductor substrate; forming a source in the ρ region A pole η well zone and a non-pole η well zone; a gate oxide is provided to cover the ρ zone, which is in the source η well zone and the gap between the > and η well intervals; forming an η + Source region and a η + drain region, which form a lightly doped source region and a lightly doped drain region in the source η well region and the non-polar η well region, respectively. Forming a gate electrode overlying the gate oxide in the source n well region and the drain n well region, respectively; forming a conductive contact window to the n + source region and the n + drain region ; And electrically connecting the gate electrode and the conductive contact window to the η + source, thereby completing the device manufacturing for dissipating static charges. 15. The method according to item 14 of the scope of the patent application, wherein the ρ region has a peak concentration between 0.5 and 1.5 #m in depth. 16. The method according to item 15 of the scope of patent application, wherein the peak concentration in the ρ region is between lx 1017 and 5 x 1018 a toms / cm3. 17. The method according to item 16 of the scope of patent application, wherein the peak concentration in the ρ region is formed by a double distribution of boron ions, and a distribution value is between 7x IIP and 4χ i〇i3i〇ns / cm2 (nominal ΐχ 〇i3i〇ns / cm2) and the energy is between 250 and 400KeV (normally 300KeV), and another cloth value is between 1x 1012 and lx 1013 IOns / cm2 ( Nominal is 4 · 5χ 1〇ΐ2 594968 VI. Patent application range (ions / cm2) and energy between 100 and 250KeV (nominal 150KeV), as well as threshold and penetration value. [18] The method according to item 14 of the scope of patent application, wherein the source n well region and the drain n well region have a peak concentration between 0.5 and 1.5 m / ζm. 19. The method as described in item 18 of the scope of patent application, wherein the peak concentration of the source well area and the drain well area is between 1 X 1〇π and 5 χ 1018at〇ms / cm3 20. The method as described in item 19 of the scope of patent application, wherein the peak concentration of the source n well region and the drain n well region is formed by the distribution of phosphorus ions, and the distribution is within a range of one dose. With 9χ 1012 to 5x 1013iOnS / Cffi2 JnniT2 X 10Ul0nS / ⑽2) and energy between 400 and 650KeV (nominal 500KeV), and threshold and penetration Cloth value.