594953 五、發明說明（\ ) 本發明是一種重繞線晶片結構及其製程，且特別是有 關於一種具彈性層且打線焊墊位於元件區之重繞線晶片 結構及其製程。 近年來，隨著電子產業的蓬勃發展，帶動了半導體 的廣泛應用，因此，爲因應電子產業的需求，許多關於 半導體製程的技術亦相當迅速地發展中。半導體製程粗 分爲前段製程與後段製程，前段製程包括半導體基底的 形成，即矽單晶成長及磊晶技術，以及半導體元件製造， 諸如MOS製程、多重金屬內連線等；而後段製程則是封 裝製程。封裝的目的，是將原本脆弱的裸晶穿上衣服， 以防止受到濕氣、熱量、雜訊的影響，並提供晶片與基 板之間信號的連接，以便於使用及測試。封裝過程中的 打線製程（wire bond)，其目的是要將晶片上的訊號接 點，亦即是銲墊，以極細的金線連接到承載器（carrier)的 接點，藉此將積體電路的電路訊號傳輸到外界。而在打 線過程中，因焊接的進行需輔以超音波震動，故銲墊所 在位置之下方區域所受之衝擊能量往往很大，因而在銲 墊下方的區域，一般言之並不佈以積體電路元件，以避 免銲線過程中對晶片造成的損害，而此不佈以積體電路 元件的區域稱之爲非元件區，其他佈以積體電路元件的 區域則稱爲元件區。 請參照第1圖，其所繪示爲習知銲墊配置位置對應 訊號接點位置的示意圖。其中包括：晶片110、銲墊120、 內引腳130及銲線140。以導線架之封裝爲例，晶片110 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項3寫本頁) ----訂---------線j 經濟部智慧財產局員工消費合作社印製 594953 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 五 發明說明（>/) 上之婷塾120配置在和與之訊號_接之內引脚u〇成最 近距離的位置上’銲塾12〇與內引腳n〇之間則以婷線 140連接。 。 一般而言，晶片上銲墊的配窿通常在和與之訊號連 接之接點成最近距離的位置上’以利於打線工作的進行； 而銲塾透過接點及承載器與PCB上的訊號接點連接。但 有時因PCB上訊號接點的腳位定義改變，或者因應不同 客戶之產品需求，造成對應接點與靜墊所在位置違反上 述之最近距離的原則’此時就需以重新繞線的方式，使 晶片上的銲墊位置重新配置，使之能夠因應接點所在位 置的改變。 爲了讓重配置製程（redistribution)的繞線不致過於複 雜，並避免增加晶片面積’最好的解決方式便是使原本 位於非元件區的銲，墊改變其所在位置至元件區。然而， 在打線製程上勢將造成晶片上元件的危害。因此，如何 提出一有效方法，使得經重繞線後的晶片能在打線過程· 中安全無虞，便成爲現今一重要的課題。 因此，本發明係提供一種重繞線封裝’其可有效阻絕 終重繞線後，因銲墊位置由非元件區異位至兀件區，所造 ^打^工作對於半導體晶片所造成的損害，以確保半導體 封裝的品資 本#明提供一種重繞線晶片結構及其衣彳壬，在具有積 體電路^仵的晶片上之元件區及非元件區，覆蓋絕緣層， 此積體電路 可爲金氧半電晶體、雙載子電晶體、電阻、電 ____-r^TcNS)A4 (210 χ 297 本紙張尺度適用中國國麥知 公釐） (請先閱讀背面之注意事項再填寫本頁)594953 V. Description of the invention (\) The present invention relates to a re-wound wafer structure and a process therefor, and more particularly to a re-wound wafer structure with an elastic layer and a wire bonding pad located in a component area and a process therefor. In recent years, with the vigorous development of the electronics industry, the widespread use of semiconductors has been promoted. Therefore, in response to the needs of the electronics industry, many technologies related to semiconductor processes have also been developing rapidly. The semiconductor process is roughly divided into a front-end process and a back-end process. The front-end process includes the formation of a semiconductor substrate, that is, silicon single crystal growth and epitaxial technology, and the manufacture of semiconductor components, such as MOS processes, multi-metal interconnects, etc .; Packaging process. The purpose of encapsulation is to put the original fragile die into clothing to protect it from moisture, heat, and noise, and to provide a signal connection between the chip and the substrate for easy use and testing. The purpose of the wire bond in the packaging process is to connect the signal contacts on the chip, that is, the solder pads, to the contacts of the carrier with ultra-fine gold wires, thereby integrating the chip. The circuit signal of the circuit is transmitted to the outside world. In the process of wire bonding, because the welding needs to be supplemented by ultrasonic vibration, the impact energy under the area where the pad is located is often very large. Therefore, the area under the pad is generally not used as a product. The body circuit components are used to avoid damage to the wafer during the bonding process. The area where the integrated circuit components are not arranged is called a non-element area, and the other areas where the integrated circuit components are arranged are called component areas. Please refer to FIG. 1, which shows a schematic diagram of a conventional solder pad configuration position corresponding to a signal contact position. These include: a wafer 110, a bonding pad 120, an inner pin 130, and a bonding wire 140. Take the leadframe package as an example, the chip 110 3 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the note on the back 3 to write this page) ---- Order- ------- Line j Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 594953 Printed by the Consumers’ Cooperative of the Ministry of Economics and the Intellectual Property of India Printed on the Invention Note (> /) The Ting 配置 120 is configured and connected to the signal__ At the position where the inner pin u0 becomes the closest distance, the welding wire 12o and the inner pin n0 are connected by a ting line 140. . Generally speaking, the bonding pads on the chip are usually located at the closest distance to the contact point connected to the signal, to facilitate the wiring work; and the solder pads are connected to the signal on the PCB through the contact point and the carrier. Click Connect. However, sometimes the pin definition of the signal contact on the PCB is changed, or the position of the corresponding contact and the static pad violates the principle of the shortest distance mentioned above due to the change of the product requirements of different customers. To reposition the pads on the wafer so that they can respond to changes in the position of the contacts. In order to prevent the redistribution winding from being too complicated and avoid increasing the chip area, the best solution is to make the solder which was originally located in the non-component area, and the pad changes its position to the component area. However, in the wire bonding process, the components on the wafer will be harmed. Therefore, how to propose an effective method to make the re-wound chip safe during the wire bonding process has become an important issue today. Therefore, the present invention provides a rewinding package which can effectively prevent the damage caused to the semiconductor wafer due to the eccentricity of the pads from the non-component area to the component area after the final rewinding. In order to ensure that the product package of semiconductor packages # provides a re-wound wafer structure and its clothing, the component area and the non-component area on a wafer with integrated circuits are covered with an insulating layer. This integrated circuit can Metal Oxide Semi-Transistor, Bipolar Transistor, Resistor, Electric ____- r ^ TcNS) A4 (210 χ 297 This paper size is applicable to China's Zhimai) (Please read the precautions on the back before filling in this page)
-裝--------訂---------線I 594953 6173twf.doc/008 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（，） 容、電感，或其組合等。而將多個銲墊，配置於非元件區 的絕緣層上，而銲墊則分別與積體電路元件電性連接。還 有一保護層，覆蓋於絕緣層上及銲墊的部分表面上，此保 護層之材質可爲氧化矽、氮化矽，或其組合等。另有一彈 性層，其材質可爲聚乙醯胺，配置於保護層上及銲墊的部 分表面上，此保護餍及彈性層共同具有多個開口，使得每 個開口分別暴露出每個銲墊之表面。彈性層表面形成有圖 案化金屬層，由多條跡線構成，跡線分別連接暴露出的銲 墊表面，且延伸至元件區，此圖案化金屬層之材質可爲銅、 鎳、銀、鈀、鈀鎳合金、金、鈦、氮化鈦，或其組合等。 還有一封裝材料層，其材質可爲聚乙醯胺，配置於彈性層 上及圖案化金屬層的表面上，此封裝材料層具有多個開 口’使^母個開口分別暴露出延伸至元件區之跡線表面。 本發明在半導體晶片之保護層及金屬層之間，配置一 彈性層’以此彈性餍吸收打線過程中產生的衝擊能量，能 有效避免兀件區之積體電路元件的損害，進而能有助提升 產品的良率。 爲讓本發明重繞線封裝之上述特徵和優點能更明顯易 懂’下文特舉較佳實施例，並配合所附圖式，作詳細說明 如下： 圖式之簡單說明： 第1圖其所繪示爲銲墊配置位置符合PCB上訊號接 點位置的7^意_。 第2圖所繪示爲本發明中銲墊重新配置對應接點位 5 本紙張尺度適用中國國豕標準（C]Sis規格⑵G χ 297公爱） (請先閱讀背面之注意事項 裝--- 寫本頁) — — — — — — 訂 ---!!線. 594953 A7 B7 173twf.doc/008 五、發明說明（L ) 保護層445、彈性層450、開口 455、495、元件區470、 非元件區480、封裝材料層49〇。半導體晶片4〇5係具有 元件區470及非兀件區480，其中元件區470至少含有一 積體電路元件415 ’而本發明之重繞線晶片結構係建構在 半導體晶片405上，半導體晶片4〇5之基底41〇上具有 一積體電路兀件41 5，例如圖中之金氧半電晶體（m〇S )， 或者雙載子電晶體、電阻、電容、電感等。而積體電路 元件415之間還包括一些隔離結構420,例如圖中之淺 溝渠結構等。積體電路元件415上會覆蓋多層絕緣層 425a、425b、425c，而積體電路元件415透過金屬內連 線連接成複雜之電路，金屬內連線則由絕緣層425a、 425b、425c中的金屬插塞430a、430b、430c，及絕緣層 425a、425b、425c間的金屬層435a、435b彼此相連而構 成。在最上層絕緣層42.5c上具有銲墊440，其透過金屬 內連線與積體電路元件415連接，使得外來訊號得以傳 遞至積體電路元件415。銲墊440上及最上層絕緣層425c 上覆蓋有一保護層445，其材質例如是氧化矽、氮化矽， 或其組合等，用以保護下方之元件及金屬連線。本發明 之重繞線晶片結構在保護層445上覆蓋有一彈性層450， 其材質例如是聚乙醯胺、合成橡膠（elastomer)或矽化合 成橡膠（silicone elastomer)等。而保護層445及彈性層450 具有共同開口 455，以暴露出部分銲墊440表面。在彈 性層450表面形成圖案化金屬層，其由多條跡線460(trace) 構成，跡線460配置於開口 455之內表面、銲墊440暴 8 (請先間讀背面之注意事項再填寫本頁)-Installation -------- Order --------- line I 594953 6173twf.doc / 008 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs , Or a combination thereof. A plurality of solder pads are arranged on the insulating layer in the non-element area, and the solder pads are electrically connected to the integrated circuit components respectively. There is also a protective layer covering the insulating layer and part of the surface of the pad. The material of this protective layer can be silicon oxide, silicon nitride, or a combination thereof. Another elastic layer, whose material can be polyethylenamine, is arranged on the protective layer and part of the surface of the pad. The protective layer and the elastic layer have multiple openings in common, so that each opening exposes each pad separately. The surface. A patterned metal layer is formed on the surface of the elastic layer, and is composed of multiple traces. The traces are respectively connected to the exposed pad surface and extend to the component area. The material of the patterned metal layer can be copper, nickel, silver, and palladium. , Palladium-nickel alloy, gold, titanium, titanium nitride, or a combination thereof. There is also a packaging material layer, which can be made of polyethylenamine, and is arranged on the elastic layer and on the surface of the patterned metal layer. This packaging material layer has multiple openings, so that each of the openings is exposed to extend to the component area. Trace surface. According to the present invention, an elastic layer is arranged between the protective layer and the metal layer of the semiconductor wafer, so as to absorb the impact energy generated during the wire bonding process, which can effectively avoid the damage of the integrated circuit elements in the component area, and can further help Improve product yield. In order to make the above-mentioned features and advantages of the re-wound package of the present invention more obvious and easy to understand, hereinafter, a preferred embodiment is described in detail, and in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings: FIG. 1 It is shown that the configuration position of the bonding pads conforms to 7 ^ _ of the signal contact positions on the PCB. Figure 2 shows the corresponding soldering pad reconfiguration in the present invention. The paper size is in accordance with China's national standard (C) Sis specification ⑵ G χ 297 public love. (Please read the precautions on the back first --- (Write this page) — — — — — — Order --- !! line. 594953 A7 B7 173twf.doc / 008 V. Description of the invention (L) Protective layer 445, elastic layer 450, openings 455, 495, element area 470, The non-element region 480 and the packaging material layer 49. The semiconductor wafer 405 has an element region 470 and a non-element region 480, where the element region 470 contains at least one integrated circuit element 415 ', and the re-wound wafer structure of the present invention is constructed on the semiconductor wafer 405. The semiconductor wafer 4 On the substrate 41 of the 〇5, there is an integrated circuit element 515, such as a metal oxysemiconductor (m0S), or a bipolar transistor, a resistor, a capacitor, an inductor, and the like. The integrated circuit elements 415 also include some isolation structures 420, such as the shallow trench structure in the figure. The integrated circuit element 415 is covered with multiple layers of insulating layers 425a, 425b, and 425c. The integrated circuit element 415 is connected to a complex circuit through a metal interconnection, and the metal interconnection is formed by the metal in the insulation layers 425a, 425b, and 425c. The plugs 430a, 430b, and 430c and the metal layers 435a and 435b between the insulating layers 425a, 425b, and 425c are connected to each other. There is a pad 440 on the uppermost insulating layer 42.5c, which is connected to the integrated circuit element 415 through a metal interconnect, so that an external signal can be transmitted to the integrated circuit element 415. A protection layer 445 is covered on the bonding pad 440 and the uppermost insulating layer 425c, and the material is, for example, silicon oxide, silicon nitride, or a combination thereof, for protecting the components below and the metal connections. The rewinded wafer structure of the present invention is covered with an elastic layer 450 on the protective layer 445, and the material is, for example, polyethyleneamine, synthetic rubber (elastomer), or silicon elastomer (silicone elastomer). The protective layer 445 and the elastic layer 450 have a common opening 455 to expose a part of the surface of the bonding pad 440. A patterned metal layer is formed on the surface of the elastic layer 450. The patterned metal layer is composed of multiple traces 460. The traces 460 are arranged on the inner surface of the opening 455, and the bonding pad 440 is 8 (please read the precautions on the back before filling in (This page)
-ϋ n ϋ. ϋ n I n^-r^JI n ϋ I ϋ l I f I 經濟部智慧財產局員工消費合作社印製 ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 一 "" 594953 經濟部智慧財產局員工消費合作社印製 五、 A7 6173twf.doc/008 取 - ~ ----------- 發明說明〇 ) 露出之表面，並延伸至元件區47〇。圖案化金屬層之材 質例如是銅、鎳、銀、鈀、鈀鎳合金、金、鈦、氮化欽， 或其組合等，比如利用電鍍的方式形成。 ' 本發明之重繞線線晶片結構還可以包栝一封裝材料胃 490,例如是聚乙醯胺，此封裝材料層490配置於彈性層45〇 上及圖案化金屬層的表面上，且此封裝材料層490具 口· 495，使得每個開口 495分別暴露出延伸至元件區47〇 之跡線460表面。進行打線製程時，導線5Ό0係連接跡、糸泉 460位於兀件區470的一端，其中導線500比如是金線。 上述之重繞線晶片結構由於具有彈性層450,因此能丨吏得 打線過程對於元件區470中的積體電路元件415不至造成 損害。 綜上所述，本發明至少具有下列優點： 1.單一形式的半導體晶片設計，因重繞線可以使銲墊 的位置重新分佈，故得以與具有不同腳位訊號的各式接 點組接合。亦即對於單一種晶片可以有多種焊墊腳位配 置，以因應各種產品需求，因此可有效降低半導體晶片 的庫存成本。 2·彈性層以及圖案化金屬層的配置均可在後段製程中 使用較低成本的設備及無塵室完成，無須經由前段製程重 新更改半導體晶片的設計與重新製造，可有效降低成本。 3·經重繞線後的銲墊下方具有彈性層，將能避免於銲 線過程中對於元件區中積體電路元件的損害。 雖然本發明已以一較佳實施例揭露如上，然其並非用 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項3寫本頁) I!裝 訂---------線 594953 五、發明說明（名） 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項51填寫本頁) »裝 寫士 訂---------線一 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）-ϋ n ϋ. ϋ n I n ^ -r ^ JI n ϋ I ϋ l I f I Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ Paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ) 594953 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, A7 6173twf.doc / 008 Take-~ ----------- Description of the invention 〇) The exposed surface and extend to Element area 47. The material of the patterned metal layer is, for example, copper, nickel, silver, palladium, palladium-nickel alloy, gold, titanium, nitride, or a combination thereof, for example, formed by electroplating. '' The re-wound wire wafer structure of the present invention can also include a packaging material stomach 490, such as polyethylenamine. This packaging material layer 490 is disposed on the elastic layer 45 and the surface of the patterned metal layer, and this The packaging material layer 490 has openings 495, so that each opening 495 exposes the surface of the trace 460 extending to the element area 470, respectively. During the wire bonding process, the wire 5Ό0 is a connecting trace, and the spring 460 is located at one end of the element area 470. The wire 500 is, for example, a gold wire. Because the above-mentioned re-wound wafer structure has the elastic layer 450, the wiring process can not cause damage to the integrated circuit element 415 in the element region 470. To sum up, the present invention has at least the following advantages: 1. The single-form semiconductor wafer design can re-distribute the positions of the bonding pads due to rewinding, so that it can be joined with various contact groups with different pin signals. That is to say, there can be multiple pad configurations for a single wafer to meet the needs of various products, so it can effectively reduce the inventory cost of semiconductor wafers. 2. The configuration of the elastic layer and the patterned metal layer can be completed in the later stage using lower-cost equipment and a clean room. There is no need to change the design and remanufacturing of the semiconductor wafer through the previous stage, which can effectively reduce costs. 3. There is an elastic layer under the re-wound bonding pad, which can avoid damage to the integrated circuit components in the component area during the bonding process. Although the present invention has been disclosed as above with a preferred embodiment, it does not use 9 paper sizes and applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the note on the back 3 to write this page) I! Binding --------- line 594953 V. Description of the invention (name) To limit the present invention, anyone skilled in the art can make some changes without departing from the spirit and scope of the present invention. Retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. (Please read the note on the back 51 to fill out this page first) »Writing and ordering --------- Line 1 Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with Chinese National Standard (CNS) A4 Specifications (210 X 297 mm)