TW594895B - Method for forming redistribution layer on semiconductor device - Google Patents

Method for forming redistribution layer on semiconductor device Download PDF

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Publication number
TW594895B
TW594895B TW092116020A TW92116020A TW594895B TW 594895 B TW594895 B TW 594895B TW 092116020 A TW092116020 A TW 092116020A TW 92116020 A TW92116020 A TW 92116020A TW 594895 B TW594895 B TW 594895B
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Taiwan
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layer
patterned
forming
semiconductor device
aluminum
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TW092116020A
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Chinese (zh)
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TW200428540A (en
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Hsin-Lun Chang
Chih-Hsiang Hsu
Tai-Yuan Huang
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Advanced Semiconductor Eng
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for forming a redistribution layer on a semiconductor device is disclosed. First, a titanium layer is formed on a surface provided with a plurality of contact pads of the semiconductor device, an aluminum layer is formed on the titanium layer and a copper layer is formed on the aluminum layer. Then, the copper layer, the aluminum layer and titanium layer are patterned to form a patterned copper layer, a patterned aluminum layer and a patterned titanium layer. Then, the patterned copper layer is removed but the patterned aluminum layer and the patterned titanium layer are left intact to form a plurality of conductive traces, wherein each conductive trace has one end connecting with one contact pad of the semiconductor device. A dielectric layer is formed on the semiconductor device and conductive traces. A plurality of blind vias are formed on the dielectric layer and correspond to the other end of the conductive traces. A plurality of bumps are formed on the conductive traces through the blind vias and electrically connected with the conductive traces.

Description

594895 五、發明說明(1) 【發明所屬之技術領域】 本發明係有關於一種用以於一半導體裝置上形成一重佈 層之方法。 【先前技術】 傳統上’積體電路(integrated circuits)已形成於石夕 基材(silicon substrate)之表面上並且具有導電接墊 (conductive pads)形成於該矽基材之周圍邊緣 (periphery)。一般而言,打線連接(wire b〇nds)係連接 於該導電接墊藉此使該導電接墊電性連接至該封裝基板 (package substrate) 〇 包含於積體電路之電子電路越來越複雜,該積體電路之 輸入連接(input C〇nnection)以及輸出連接(〇utput connection)的數目也隨之增加。由於輸出連接以及輸入 連接的I目增要求積體電路的輸入以及輸出I電接墊 (】npU'and output conductive ρ&(〇 彼此分佈地更靠 ί門:Γ.:用Λ作為積體電路輸入或輸出之導電接墊之間 的間距(PUch)要隨著電路的複雜化而減少。 绫ί L! ί輸入或輸出之導電接墊之間的間距下降使得打 構=接,dlngwire)之寬度要更狹窄且: 接:距並不足夠,而且增加的輸出以 電路的周Iflm + 要更夕列的連接設在該積體 包格妁周圍因此需要更長的連接線。 連接線長度的增加會使得該車 械性的限制。首先,長連接線受電性以及機 安深逋吊包含相當大的電感 594895 五'發明說明(2) (inductance) 〇增力口該連接 之電子訊號傳遞的速度。此 動或是至少暫時地在它們之 機械穩定度。該電性連接的 上之「銲錫突塊」取代打線 之機械穩定度大致上比打線 線連接需要更大的導電接墊 是,打線連接通常可比該銲 此,難以將銲錫突塊形成於 提供電性連接於該導電接墊 設於該石夕基材表面之内部比 物理上間隔較遠。因此,與 塊的數目可以增加。然而, 電接墊設在該矽基材的周圍 本的設計以及原先的製程, 端重佈層(I/O redistribut 性連接至設在該矽基材表面 然而,形成埠端重佈層的 材表面形成多個分別與該導 金屬線路。由於該導電接墊 多由鋁形成。在形成鋁線路 一 >儿積於该發基材表面的|呂 暴露在空氣中時極容易形成 易與蝕刻劑作用,造成蝕刻 線的電感會降低通過該連接線 外,增加連接線的長度會因抖 間發生短路而降低該連接線的 電感可藉由形成於該導電接墊 連接而降低。此外,輝 連接好'然而,銲锡突 空間(spacing)或間隔。即 錫突塊形成地更為密集。因 原本預設形成給該打線連接以 之導電接墊上。將該導電接墊< 設在周圍能允許該導電接墊在 該積體電路電性連接之銲錫突 許多積體電路的設計都將該導 邊緣。為了不更改積體電路原 可在該矽基材之表面形成一埠 ion layer),使該導電接墊電 之内部的銲錫突塊。 一個重要步驟,便是在該矽基 電接墊以及該銲錫突塊連接之 多為銘接墊,因此該金屬線路丨 的衣耘中需要以蝕刻的方式對 金屬進行圖案化。但是由於鋁 一層氧化層,且鋁的氧化層不 困難。因此在蝕刻鋁金屬時,594895 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for forming a redistribution layer on a semiconductor device. [Prior art] Traditionally, integrated circuits have been formed on the surface of a silicon substrate and have conductive pads formed on the periphery of the silicon substrate. Generally speaking, wire bOnds are connected to the conductive pads so that the conductive pads are electrically connected to the package substrate. The electronic circuits included in the integrated circuit are becoming more and more complicated. , The number of input connections (input connection) and output connections (out connection) of the integrated circuit also increases. Due to the increase in the output connection and the input connection, the input and output I electrical pads of the integrated circuit () npU 'and output conductive ρ & (〇 are distributed closer to each other: Γ .: Use Λ as the integrated circuit The distance between the conductive pads of the input or output (PUch) should be reduced as the circuit becomes more complicated. 绫 ί L! Ί The distance between the conductive pads of the input or output is reduced to make the structure = connect, dlngwire). The width should be more narrow and: The connection: the distance is not enough, and the increased output is based on the circuit's circumference Iflm + the connection should be set around the package bag, so a longer connection line is required. Increasing the mechanical limit of the vehicle. First, the long-distance cable's electrical properties and the safety of the machine include considerable inductance. 594895 5'Inventance (2) (inductance) 〇 Zenglikou's electronic signal transmission Speed. This movement may be at least temporarily their mechanical stability. The mechanical stability of the soldering bumps instead of wire bonding on the electrical connection is generally greater than the conductive pads required for wire bonding. even It is usually comparable to this soldering, and it is difficult to form solder bumps that provide electrical connection to the inside of the conductive pad provided on the surface of the Shi Xi substrate than the physical distance. Therefore, the number of blocks can be increased. However, The electrical pads are designed around the silicon substrate and the original manufacturing process. The end redistribution layer (I / O redistribut is connected to the surface of the silicon substrate. However, the material surface forming the port end redistribution layer is formed. A plurality of conductive lines are formed separately from the conductive metal. Since the conductive pads are mostly formed of aluminum. When forming aluminum circuits, the surface of the hair substrate is easily formed when exposed to air. The inductance of the etching line will be reduced by passing through the connection line, and the increase of the length of the connection line will be reduced due to a short circuit between the jitters. The inductance of the connection line can be reduced by forming on the conductive pad connection. In addition, the good connection is good 'However, the solder bumps are spaced or spaced. That is, the solder bumps are formed more densely. Because the solder pads are originally formed on the conductive pads. The conductive pads < Allow the conductive pads to protrude from the solder that is electrically connected to the integrated circuit. Many integrated circuit designs have this conductive edge. In order not to change the integrated circuit, a port layer could be formed on the surface of the silicon substrate). An important step is to electrically connect the conductive pads with solder bumps. An important step is to connect the silicon-based electrical pads and the solder bumps as inscribed pads. Therefore, the clothing of the metal circuit needs to be The metal is patterned by means of etching. However, since aluminum has an oxide layer and the aluminum oxide layer is not difficult. Therefore, when etching aluminum metal,

第9頁 594895 五、發明說明(3) 常有蝕刻進行緩慢且蝕刻不均勻的問題。 【發明内容】 本發明之主要目的係提供一種用以形成一鋁線路於一半 導體裝置之方法,以克服或是改善前述之問題。 根據本發明之一種用以於一半導體裝置上形成一重佈層 之方法。首先,將一鈦層形成於該半導體裝置具有複數個 接塾之表面上、形成一銘層於該鈦層上以及形成一銅層於 该铭層上’使得該铭層直接接觸該鈦層以及該銅層直接接 觸該鋁 圖案化 圖案化 阻層於 共同利 該圖案 圖案化 欽層。 以及已 線的一 電層於 成複數 複數個 適用 釋之硝 acid)、 層。然後,圖 銅層、'一已圖 該銅層、鋁層 該銅層上,該 用該圖案化之 化銅層、铭層 銅層以及該已 之後,除去該 圖案化鈦層保 端部連接至該 該半導體裝置 個盲孔分別對 凸塊透過該盲 於圖案化該銅 酸溶液。該稀 1去離子水(d e 案化鋁層以 以及鈦層之 圖案化銅層 光阻層為遮 之步驟之後 圖案化鋁層 已圖案化銅 持完整以形 半導體晶片 以及該引線 應於該引線 孔電性連接 層以及除去 釋之確酸溶 ionized wa 、鋁層和鈦層以形成一已 及一已圖案化之鈦層。當丨 前’會形成一圖案化之光 、鋁層以及鈦層之步驟可 罩而進行。此外,亦可在 移去該光阻層,使用該已 作為遮罩(mask )圖案化該 層但是使該已圖案化鋁層 成複數條引線,其中該引 之接墊。然後,形成一介 的表面。於該介電層上形 的另一端部。最後,形成 於該引線。 该銅層的餘刻劑可為一稀 液主要由石肖酸(n i t r i c ter)、酷酸(aceticPage 9 594895 V. Description of the invention (3) There are often problems with slow etching and uneven etching. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for forming an aluminum circuit on a semi-conductor device to overcome or improve the aforementioned problems. A method for forming a redistribution layer on a semiconductor device according to the present invention. First, a titanium layer is formed on a surface of the semiconductor device having a plurality of contacts, a inscription layer is formed on the titanium layer, and a copper layer is formed on the inscription layer, so that the inscription layer directly contacts the titanium layer and The copper layer directly contacts the aluminum patterned patterned resist layer to benefit the patterned patterned layer. And an electric layer that has been wired is formed into a plurality of layers. Then, after the copper layer, the copper layer, the aluminum layer and the copper layer have been mapped, the patterned copper layer, the copper layer of the Ming layer and the copper layer are removed, and then the patterned titanium layer is removed to secure the end connection. The blind holes of the semiconductor device pass through the blind patterned copper acid solution to the bumps. The dilute 1 deionized water (the aluminum layer and the patterned copper layer of the titanium layer are covered by the photoresist layer), and the patterned aluminum layer has been patterned and the copper is completely formed to form the semiconductor wafer and the lead should be on the lead. Porous electrical connection layer and removing the acid-soluble ionized wa, aluminum layer and titanium layer to form a patterned and a patterned titanium layer. At the moment, a patterned light, aluminum layer and titanium layer will be formed The steps can be performed by masking. In addition, the photoresist layer can be removed, and the layer can be patterned using the mask but the patterned aluminum layer can be formed into a plurality of leads. Pad. Then, a dielectric surface is formed. The other end of the dielectric layer is shaped. Finally, it is formed on the lead. The remaining etchant of the copper layer may be a dilute liquid mainly composed of nitric ter, Cool acid

594895 五、發明說明(4) ac id)以及過氧化氫(hydrogen peroxide)組成。此外,亦 可以電化學蝕刻的方式除去該已圖案化銅層但是使該已圖 案化鋁層以及鈦層保持完整。 適用於圖案化該鋁層的蝕刻劑可為一稀釋之填酸溶液。 ^亥稀釋之鱗酸溶液主要由碟酸(phosphoric acid)、去離 子水(deionized water)以及醋酸(acetic acid)。 用以钱刻該鈦層之蝕刻液,主要係由氫氧化銨 (ammonium hydroxide)、過氧化氫以及去離子水所組成。 ^匕外亦了以主要係由氟化氫(hydrogen fluoride)、過 氧化氫以及去離子水所組成之蝕刻液,蝕刻該鈦層。 钱 本發明係利用一銅層保護半導體裝置上重佈層中之鋁 ::之表面不至於暴露於空氣中,藉此順利韻刻 =以及該鋁層,最後再將該已圖案 設=圖案化的I線路。由於該罐在該銅層: 保遵下,因此不至於產生阻礙蝕 曰扪 钱刻該銘層並且得到姓刻均勻的銘線4台’月匕有效率地 =明亦二供一種用以形成— 之方法。百先,形成-銘層於該半 牛^體名置 保護金屬層(例如銅層)於該鋁層上,你二^以及形成一 接接觸該鋁層。然後,β案化;雀使付該保護金屬層直_ -已圖案化保護金屬層以金屬層和銘層以形成 該已圖案化保護金屬層但是使心銘層。最後,除去 當該保護金屬層係為銅層時,' j案化銘層保持完整。 除去該銅層的蝕刻劑可為一 # =於圖案化該銅層以及 稀釋之石肖酸溶液。該稀釋之硝 第11頁 594895594895 V. Description of the invention (4) ac id) and hydrogen peroxide. In addition, the patterned copper layer can also be removed by electrochemical etching, but the patterned aluminum layer and titanium layer can be kept intact. The etchant suitable for patterning the aluminum layer may be a diluted acid-filled solution. The dilute scale acid solution is mainly composed of phosphoric acid, deionized water, and acetic acid. The etching solution for engraving the titanium layer is mainly composed of ammonium hydroxide, hydrogen peroxide, and deionized water. ^ The titanium layer is also etched with an etching solution mainly composed of hydrogen fluoride, hydrogen peroxide, and deionized water. The present invention uses a copper layer to protect the aluminum in the redistribution layer on the semiconductor device: the surface is not exposed to the air, so that it can be engraved smoothly and the aluminum layer, and finally the pattern is set to be patterned. I line. Because the tank is under the copper layer: under the guarantee, it will not hinder the corrosion. You can save money by engraving the inscription layer and get uniform inscription lines. 4 sets of moon daggers are effective = Ming Yi Er is used to form — The method. One hundred years ago, a protective layer was formed on the aluminum layer, such as a copper layer, on the aluminum layer, and a metal layer (such as a copper layer) was formed on the aluminum layer. Then, β is patterned; the protective metal layer is made straight-the patterned protective metal layer is formed of the metal layer and the indentation layer to form the patterned protective metal layer but the inscription layer is formed. Finally, when the protective metal layer is a copper layer, the case layer remains intact. The etchant for removing the copper layer may be a patterned copper layer and a diluted stone acid solution. The diluted nitrate page 11 594895

酸溶液主要由硝酸(nitric acid)、去離子水、贈酸以及 過氣化氫組成。此外,亦可以電化學姓刻的方式除去今已 圖案化銅層但是使該已圖案化鋁層以及鈦層保持完整。/ 適用於圖案化該铭層的#刻劑可為一稀釋之磷酸溶液。 该稀釋之磷酸溶液主要由填酸(phosphoric acid)、去離 子水(deionized water)以及醋酸(acetic acid)組成。 本發明所提供之方法,可另包含在鋁層形成步驟之前, 形成一鈦層於該半導體裝置上。當圖案化該保護金屬層、 紹層以及欽層之前’會形成一圖案化之光阻層於該保護金 屬層上’該圖案化保護金屬層、銘層以及鈦層之步驟可共_ 同利用该圖案化之光阻層為遮罩而進行。此外,亦可在今 圖案化銅層、鋁層之步驟之後移去該光阻層,並且使用該 已圖案化保護金屬層以及該已圖案化鋁層作為遮罩(mask) 而餘刻該鈦層。用以姓刻該鈦層之餘刻液,主要係由氫氧 化銨(ammonium hydroxide)、過氧化氫以及去離子水所組 成。此外,亦可以主要係由氟化氫(hydrogen f luor i de)、過氧化氫以及去離子水所組成之蝕刻液,餘 刻該欽層。 【實施方式】 第1 a - 1 d圖係圖示根據本發明一實施例形成一導電線路_ 於一半導體裝置之主要步驟。參照第1 a圖,首先將一鋁層 108形成於該半導體裝置丨〇〇上。該半導體裝置丨〇〇包含一9 基片102、複數個金屬接墊1〇4(通常是鋁接墊或銅接墊)以 及一介電層(例如護層106)。該基片102可以包含一層半The acid solution is mainly composed of nitric acid, deionized water, acid donating, and hydrogenated gas. In addition, the patterned copper layer can also be removed in an electrochemical manner, but the patterned aluminum layer and titanium layer can be kept intact. / The #etching agent suitable for patterning the layer may be a diluted phosphoric acid solution. The diluted phosphoric acid solution is mainly composed of phosphoric acid, deionized water, and acetic acid. The method provided by the present invention may further include forming a titanium layer on the semiconductor device before the aluminum layer forming step. When patterning the protective metal layer, the shao layer and the Chin layer, a patterned photoresist layer will be formed on the protective metal layer. The patterned protective metal layer, Ming layer and titanium layer can be used together. The patterned photoresist layer is performed as a mask. In addition, the photoresist layer can also be removed after the step of patterning the copper layer and the aluminum layer, and the patterned protective metal layer and the patterned aluminum layer can be used as a mask to etch the titanium. Floor. The remaining etching solution for engraving the titanium layer is mainly composed of ammonium hydroxide, hydrogen peroxide, and deionized water. In addition, it can also be an etching solution mainly composed of hydrogen fluoride (hydrogen fluoride), hydrogen peroxide, and deionized water. [Embodiment] Figures 1 a-1 d illustrate the main steps of forming a conductive circuit in a semiconductor device according to an embodiment of the present invention. Referring to FIG. 1a, an aluminum layer 108 is first formed on the semiconductor device. The semiconductor device includes a 9 substrate 102, a plurality of metal pads 104 (usually aluminum pads or copper pads), and a dielectric layer (such as a protective layer 106). The substrate 102 may include a layer and a half

第12頁 594895 五、發明說明(6) 導體材料(例如矽、砷化鎵、碳化矽、鑽石或是其他業界 熟知的基片材料)。護層1 0 6可以是一聚醯亞胺層 (polyimide layer)、二氧化矽層、氮化矽層或是由其他 業界熟知的護層材料形成。如圖所示,該護層1 〇 6較佳覆 盖5亥基片102的整個上表面且具有複數個開孔對應於該些 接墊1 0 4之位置’使得該些接墊1 〇 4係裸露於該護層1 〇 6而 直接與該鋁層1 0 8接觸。然後,形成一保護金屬層例如一 銅層110於该IS層108上’使得該|g層1〇8完全被覆蓋而不 至於曝露於空氣中,藉此防止該鋁層1〇8產生表面氧化的 現象。下一步,塗佈一層光阻層11 2並且使該光阻層丨丨2形_ 成圖案結構(patterning)。 參照第1 b圖’以該光阻層11 2之圖案結構為遮罩 (mask),餘刻該銅層11〇和鋁層丨〇8以形成一已圖案化銅層 11 0 a以及一已圖案化鋁層1 〇 8 a。此時,該已圖案化銘層 1 0 8a係具有預先設定之導電線路之圖案。在本實施例之此 步驟中,用於圖案化該銅層與該鋁層之蝕刻劑分別可為一 稀釋之硝酸溶液與一稀釋之磷酸溶液。該稀釋之確酸溶液 主要由硝酸(nitric acid)、去離子水、醋酸以及過氧化 氫組成。在本實施例中,該稀釋之硝酸溶液的各主要成分 之比例係為去離子水84 %、醋酸5 %、過氧化氫} %以及硝· 酸1 〇 %並且將該蝕刻劑加熱至50。〇進行蝕刻。用於圖案化 該銘層之飯刻劑可為一稀釋之磷酸溶液。該稀釋之磷酸溶 液主要由磷酸(phosphoric acid)、去離子水(dei〇nized water)以及醋酸(acetic acid)組成。在本實施例中,該Page 12 594895 V. Description of the invention (6) Conductor materials (such as silicon, gallium arsenide, silicon carbide, diamond, or other well-known substrate materials). The protective layer 106 can be a polyimide layer, a silicon dioxide layer, a silicon nitride layer, or another protective layer material known in the industry. As shown in the figure, the protective layer 106 preferably covers the entire upper surface of the substrate 50 and has a plurality of openings corresponding to the positions of the pads 104, so that the pads 104 are It is exposed on the protective layer 106 and directly contacts the aluminum layer 108. Then, a protective metal layer such as a copper layer 110 is formed on the IS layer 108, so that the | g layer 108 is completely covered without being exposed to the air, thereby preventing the aluminum layer 108 from generating surface oxidation. The phenomenon. In the next step, a photoresist layer 112 is coated and the photoresist layer 2 is patterned. Referring to FIG. 1 b ′, using the pattern structure of the photoresist layer 112 as a mask, the copper layer 110 and the aluminum layer 08 are formed to form a patterned copper layer 11 0 a and Patterned aluminum layer 108a. At this time, the patterned surface layer 108a has a pattern of a predetermined conductive line. In this step of this embodiment, the etchant used to pattern the copper layer and the aluminum layer may be a diluted nitric acid solution and a diluted phosphoric acid solution, respectively. The diluted acid solution is mainly composed of nitric acid, deionized water, acetic acid, and hydrogen peroxide. In this embodiment, the ratio of each main component of the diluted nitric acid solution is 84% of deionized water, 5% of acetic acid, 5% of hydrogen peroxide, and 10% of nitric acid, and the etchant is heated to 50%. 〇Etching. The patterned food engraver can be a dilute phosphoric acid solution. The diluted phosphoric acid solution is mainly composed of phosphoric acid, deionized water, and acetic acid. In this embodiment, the

594895 五、發明說明(7) 稀釋之磷酸溶液的各主要成分之比例係為去離子水6 %、 醋酸1 1 %、以及磷酸83 %,並且將該蝕刻劑加熱至6〇 t進 行姓刻。 參照第lc圖,除去銅層11 〇a上之光阻層丨丨2。 參照第1 d圖,接著以圖案化該銅層之蝕刻劑除去該已圖 案化銅層ll〇a,但是使該已圖案化鋁層1083保持完整,藉 此得到餘刻均勻之鋁線路。在本實施例中,亦可以電化學 1虫刻的方式進行此步驟。該電化學钱刻製程所使用之電解 質溶液主要由硫酸鉀(KlS0.)以及甘油(glycer〇1)組成。 在本實施例中,該電解質溶液包含〇 · 4M硫酸鉀以及1. 5 Μ甘_ 油。 參照第2a-2e圖,本發明另提供一種利用第la —ld圖所述 之方法,在一半導體晶片2 〇 〇上形成一重佈層 (redistribution layer)的製程。參照第2a圖,首先將一 鈦層20 6、一鋁層2 08以及一銅層210依序濺鍍沉積在該晶 片200具有銘接墊202的表面上。該鈦層2〇6之厚度約為 lkA,而該鋁層2 08之厚度約為4女戲。 參照第2 b圖’選擇性钱刻該鈦層2 〇 6、該銘層2 0 8以及該 銅層2 1 0以形成一引線2 1 2。該引線2 1 2的一端部連接至鋁_ 接墊20 2,其另一端部則係延伸於該護層2〇4上。在本實施· 例中’係利用前述之稀釋硝酸溶液I虫刻該銅層2 1 〇以及利 用前述之稀釋磷酸溶液蝕刻該鋁層2 〇 8,然後以原有的光 阻層為遮罩或是以圖案化後之該銅層21〇a以及該鋁層2〇8a 為遮罩蝕刻該鈦層2 0 6。用以蝕刻該鈦層2 〇 6之蝕刻液,主594895 V. Description of the invention (7) The ratio of each main component of the diluted phosphoric acid solution is 6% of deionized water, 11% of acetic acid, and 83% of phosphoric acid, and the etchant is heated to 60 t for the last name engraving. Referring to FIG. 1c, the photoresist layer 2 on the copper layer 110a is removed. Referring to FIG. 1d, the patterned copper layer 110a is then removed by an etchant patterning the copper layer, but the patterned aluminum layer 1083 is kept intact, thereby obtaining a uniform aluminum circuit at the remaining time. In this embodiment, this step can also be performed in an electrochemical manner. The electrolytic solution used in the electrochemical coining process is mainly composed of potassium sulfate (K1SO.) And glycerol (glycer0). In this embodiment, the electrolyte solution contains 0.4 M potassium sulfate and 1.5 M glycan oil. Referring to FIGS. 2a-2e, the present invention further provides a process for forming a redistribution layer on a semiconductor wafer 2000 by using the method described in FIGS. 1a to 1d. Referring to FIG. 2a, first, a titanium layer 206, an aluminum layer 208, and a copper layer 210 are sequentially sputter-deposited on the surface of the wafer 200 having the bonding pad 202. The thickness of the titanium layer 206 is about lkA, and the thickness of the aluminum layer 208 is about 4 women. Referring to FIG. 2b ', the titanium layer 206, the inscription layer 208, and the copper layer 2 10 are selectively etched to form a lead 2 1 2. One end portion of the lead 2 1 2 is connected to the aluminum pad 20 2, and the other end portion thereof extends on the protective layer 204. In this example, "the copper layer 2 10 is etched by using the aforementioned diluted nitric acid solution I and the aluminum layer 208 is etched by using the aforementioned diluted phosphoric acid solution, and then the original photoresist layer is used as a mask or The titanium layer 206 is etched with the patterned copper layer 21a and the aluminum layer 208a as a mask. An etching solution for etching the titanium layer 206, the main

第14頁 594895 五、發明說明(8) 要係由氫氧化銨(ammoni um hydroxi de)、過氧化氫以及去 離子水所組成。另外亦可以主要係由I化氫(hydrogen f luori de)、過氧化氫以及去離子水所組成之蝕刻液,蝕 刻該欽層2 0 6。 參照第2 c圖,先將該已圖案化銅層2 1 〇 a除去,使該已圖 案化紹層2 0 8 a以及鈦層2 0 6 a保持完整。然後將一介電層 214 (較佳係以聚醯亞胺(p〇iyimide)製成)覆蓋於該引線 212以及護層204上,並且於該介電層214上形成一個光界 定盲孔(口11〇1:〇-(16以116(11)1111(1-¥13)2143對應於該引線212 遠離鋁接墊202之端部。 . 參照第2d圖’一突塊下金屬層216覆蓋於該盲孔214a。 该一突塊下金屬層216較佳包含一鎳/飢層2i6a作為阻障層 (barrier layer),覆蓋於該盲孔214a與該引線212之鋁層 208a接;以及一銅層216b作為潤濕層(wetting layer), 設於該鎳/釩層2 1 6 a上。 參照第2e圖,一銲錫凸塊218設於該銅層216b上。該銲 錫凸塊2 1 8亦可以一金凸塊取代。 本發明係利用一銅層保護半導體裝置上之鋁層,使該鋁 層之表面不至於暴露於空氣中,藉此順利同時餘刻該銅層 以及該鋁層,最後再將已圖案化銅層移去,以得到預先設_ 定之圖案化的銘線路。由於該I呂層係在該銅層的保護下, 因此不至於產生阻礙蝕刻的氧化層,能有效率地蝕^該鋁 層並且付到钮刻均勻的銘線路。此外,亦可以金或是其他 貴重金屬取代銅層用以保護鋁層,並且可達到相同之^ 594895Page 14 594895 V. Description of the invention (8) It should be composed of ammoni um hydroxi de, hydrogen peroxide and deionized water. In addition, an etching solution mainly composed of hydrogen f luori de, hydrogen peroxide, and deionized water may be used to etch the chin layer 206. Referring to FIG. 2c, the patterned copper layer 2 10a is removed first, so that the patterned copper layer 208a and the titanium layer 206a are kept intact. Then, a dielectric layer 214 (preferably made of polyimide) is covered on the leads 212 and the protective layer 204, and a light-defining blind hole is formed on the dielectric layer 214 ( Mouth 11〇1: 〇- (16 to 116 (11) 1111 (1- ¥ 13) 2143 corresponds to the end of the lead 212 away from the aluminum pad 202.... Refer to FIG. 2d 'A bump under the metal layer 216 cover In the blind hole 214a. The under bump metal layer 216 preferably includes a nickel / starved layer 2i6a as a barrier layer covering the blind hole 214a and the aluminum layer 208a of the lead 212; and The copper layer 216b serves as a wetting layer on the nickel / vanadium layer 2 1 6a. Referring to FIG. 2e, a solder bump 218 is provided on the copper layer 216b. The solder bump 2 1 8 It can also be replaced by a gold bump. The invention uses a copper layer to protect the aluminum layer on the semiconductor device, so that the surface of the aluminum layer is not exposed to the air, thereby smoothly and simultaneously engraving the copper layer and the aluminum layer, Finally, the patterned copper layer is removed to obtain a pre-set patterned inscription circuit. Since the ILu layer is under the protection of the copper layer, it does not As for the oxide layer that hinders the etching, the aluminum layer can be efficiently etched and uniformly patterned. In addition, the copper layer can also be replaced by gold or other precious metals to protect the aluminum layer, and the same can be achieved. Of ^ 594895

如上所述,本發明所提供之形成導電線路之方法,可用 以形成一埠端重佈層,將分散於半導體裝置周圍的導電 墊電性連接至陣列分布於該半導體裝置内部的對外接點 (例如銲錫突塊)。此外,參照第3a —3c圖,本發明所提供 之形成導電線路之方法,亦可用於將分佈於一半導體褒置 3/0中央區域之複數個導電接墊3 〇2(如第3a圖所示)利用以 第la-Id圖所述之方法形成之導電線路3〇4電性連接至分佈 在該半導體裝置30 0周圍區域之對外接點3〇6(如第3b圖所 示),再以打線的方式將該半導體裝置3〇〇電性連接於一美 板308。在本實施例中,原先不利於打線接合“卜❻ 土 之接塾配置(亦即第3a圖所示集中在該半導體裝 $ I央區域之接墊302)係被重佈為可以進行打線接合 置(亦即第3b圖所示分佈該半 區域之接點3 0 6 )。 例揭示,然其並非用以限 在不脫離本發明之精神和 改。因此本發明之保護範 定者為準。 雖然本發明已以前述較佳實施 定本發明,任何熟習此技藝者, 範圍内,當可作各種之更動與修 圍當視後附之申請專利範圍所界 594895 圖式簡單說明 【圖式簡單說明】 為了讓本發明之上述和其他目的、特徵、和優點处 顯特徵’下文特舉本發明較佳實施例,並配合所$ —明 作詳細說明如下。 闺不, 第1 a-Id圖:以剖視圖圖示根據本發明一實施例 導,線路形成於一半導體裝置之主要步驟;以及; e圖:以剖視圖圖示根據本發明另一實施 一^3a線路形成於一半導體裝置之主要步驟;以及 導電圖^以上視圖示根據本發明另一實施例之將一 、、、 开》成於一半導體裝置之主要步驟。 圖號說明: 100 半導體裴置 10 4 接墊 10 8 鋁層 110 銅層 112 光阻層 2 0 0 半導體晶片 204 護層 2 0 6 鈦層 2 0 8 鋁層 210 銅層 212 引線 214 介電層 102 基片 106 護層 108a已圖案化鋁層 110a已圖案化鋼層 2 02 鋁接墊 206a圖案化之鈦層 2 0 8 β已圖案化|呂層 210a已圖案化銅層 214a盲孔 594895 圖式簡單說明 216 216a 218 300 304 308 突塊下金屬層 鎳/釩層 銲錫凸塊 半導體裝置 導電線路 基板 2 1 6b銅層2 30 2 導電接墊 30 6 對外接點As described above, the method for forming a conductive circuit provided by the present invention can be used to form a port-side redistribution layer to electrically connect conductive pads scattered around a semiconductor device to external and external points of an array distributed inside the semiconductor device ( (Such as solder bumps). In addition, referring to Figures 3a-3c, the method for forming a conductive circuit provided by the present invention can also be used to distribute a plurality of conductive pads 3 02 (as shown in Figure 3a) distributed in a central area of a semiconductor array 3/0. (Shown) The conductive line 304 formed by the method described in the la-Id diagram is electrically connected to the external connection point 306 (as shown in FIG. 3b) distributed in the area around the semiconductor device 300, and then The semiconductor device 300 is electrically connected to a US board 308 in a wired manner. In the present embodiment, the wiring configuration "that is not conducive to wire bonding" (that is, the pad 302 concentrated in the semiconductor device's central region shown in Figure 3a) is redistributed to allow wire bonding. (That is, the contacts 3 0 6 that distribute the half area shown in Figure 3b). The example reveals, but it is not intended to be limited to the spirit and modification of the present invention. Therefore, the protection scope of the present invention shall prevail. Although the present invention has been formulated with the foregoing preferred implementation, anyone skilled in the art can make various changes and repairs within the scope of the scope of patents attached to the application. 594895 Description] In order to make the above and other objects, features, and advantages of the present invention obvious, the following describes the preferred embodiments of the present invention in cooperation with the following descriptions. Detailed description is as follows. No. 1 a-Id diagram : A cross-sectional view illustrating the main steps of forming a circuit in a semiconductor device according to an embodiment of the present invention; and e diagram: a cross-sectional view illustrating the main steps of forming a ^ 3a circuit in a semiconductor device according to another implementation of the present invention; And the conductive diagram ^ The above view shows the main steps of forming a semiconductor device into a semiconductor device according to another embodiment of the present invention. Description of the drawing number: 100 semiconductor substrate 10 4 pad 10 8 aluminum layer 110 Copper layer 112 Photoresist layer 2 0 0 Semiconductor wafer 204 Protective layer 2 6 Titanium layer 2 0 8 Aluminum layer 210 Copper layer 212 Lead 214 Dielectric layer 102 Substrate 106 Protective layer 108a Patterned aluminum layer 110a Patterned steel Layer 2 02 Aluminum pad 206a patterned titanium layer 2 0 8 β patterned | Lu layer 210a Patterned copper layer 214a Blind hole 594895 Brief description of the diagram 216 216a 218 300 304 308 Metal layer under the bump nickel / vanadium Layer solder bump semiconductor device conductive circuit substrate 2 1 6b copper layer 2 30 2 conductive pad 30 6 external point

第18頁Page 18

Claims (1)

594895 六、申請專利範圍 1、 一種用以於一半導體裝置上形成一重佈層 (redistribution layer)之方法’其包含下列步驟: 形成一鈦層於該半導體裝置之一表面上,其中該半導體 裝置具有複數個接墊設於該表面; 形成一鋁層於該鈦層上使得該鋁層直接接觸該鈦層; 形成一銅層於該鋁層上使得該銅層直接接觸該鋁層; 圖案化該銅層、銘層以及鈦層以形成一已圖案化銅層、 一已圖案化鋁層以及一已圖案化之鈦層; 除去該已圖案化銅層但是使該已圖案化之|呂層以及已圖 案化鈦層保持完整以形成複數條引線,其中每一引線的一 _ 端部係連接至該半導體晶片之接墊之一; 形成一介電層於該半導體裝置以及該引線的表面; 於該介電層上形成複數個盲孔分別對應於該引線的另一 端部;以及 複數個凸塊透過該盲孔形成於該引線上並且電性連接於 舌亥引線。 、 ,α申凊專利範圍第1項所述之用以於一半導體裝置」 之方法’其中該銅層之圖案化步二該 第二餘二二二去步驟包含以一第一飯刻劑餘刻該銅層, ac i d)、Χ^為一稀釋之硝酸溶液包含硝酸(n i tr i c 玄雖子水、醋酸以及過氧化氫。 如申凊專利範圍第1項所述之用以於一半導體裝置上594895 VI. Application Patent Scope 1. A method for forming a redistribution layer on a semiconductor device, which includes the following steps: forming a titanium layer on a surface of the semiconductor device, wherein the semiconductor device has A plurality of pads are disposed on the surface; forming an aluminum layer on the titanium layer so that the aluminum layer directly contacts the titanium layer; forming a copper layer on the aluminum layer so that the copper layer directly contacts the aluminum layer; patterning the Copper layer, layer, and titanium layer to form a patterned copper layer, a patterned aluminum layer, and a patterned titanium layer; remove the patterned copper layer but make the patterned | Lu layer and The patterned titanium layer remains intact to form a plurality of leads, wherein one end of each lead is connected to one of the pads of the semiconductor wafer; forming a dielectric layer on the semiconductor device and the surface of the leads; and A plurality of blind holes are formed on the dielectric layer respectively corresponding to the other ends of the leads; and a plurality of bumps are formed on the leads through the blind holes and are electrically connected to the leads. . The method for applying to a semiconductor device described in item 1 of the patent application scope "wherein the patterning of the copper layer is performed in step two, and the second remaining two two two to two steps include the use of a first food engraving agent. Carved the copper layer, ac id), X ^ is a dilute nitric acid solution containing nitric acid (ni tr ic black water, acetic acid, and hydrogen peroxide. It is used in a semiconductor as described in the first item of the patent scope On device 第19頁 594895 六、申請專利範圍 形成一重佈層之方法,其中該铭層之圖案化步驟包含以一 第二餘刻劑蚀刻該铭層’該第二鍅刻劑係為一稀釋之磷酸 溶液包含碟酸(phosphoric acid)、去離子水(deionized water)、醋酸(acetic acid) 〇 4、如申請專利範圍第1項所述之用以於一半導體裝置上 幵> 成一重佈層之方法,其中該已圖案化銅層除去步驟係利 用一電化學蝕刻製程達成。 5如申請專利範圍第1項所述之用以於一半導體梦f上 形成一重佈層之方法,豆中兮姑Μ 、 刻劑進行勉刻,該第三飾步驟係以-第三银 hydroxide) ^ i5 ir ^ ^ 』已 3 氣氧化銨(ammon i um hydroxide)過虱化氫以及去離子水。 6、 如申請專利範圍货Ί s ^ 形成一重佈層之方=第1項所述之用以於一半導體裝置上 刻劑進行蝕刻,該塗丄其中該鈦層蝕刻步驟係以一第三蝕 f luoride)、過氧各^一蝕刻劑包含氟化氫(hydrogen 乳化氧以及去離子水。 7、 如申請專利範^ j 形成一重佈層之方法弟1豆項所述之用以於一半導體裝置上^ 含形成一圖案化之#,其中在圖案化該銅層之步驟之前包 層以及鈦層之步驟总層於忒銅層上,該圖案化銅層、銘 行。 驟係利用該圖案化之光阻層為遮罩而進Page 19 594895 VI. Method for forming a heavy cloth layer in the scope of patent application, wherein the patterning step of the inscription layer includes etching the inscription layer with a second etchant, the second etchant is a diluted phosphoric acid solution Containing phosphoric acid, deionized water, acetic acid 〇4, as described in the scope of the first patent application for a semiconductor device > method of forming a redistribution layer The step of removing the patterned copper layer is achieved by an electrochemical etching process. 5. The method for forming a heavy cloth layer on a semiconductor dream f as described in item 1 of the scope of the patent application, the bean paste and the engraving agent are engraved, and the third decoration step is-the third silver hydroxide ) ^ i5 ir ^ ^ 『ammon i um hydroxide has been treated with hydrogen peroxide and deionized water. 6. According to the scope of the patent application, the method of forming a heavy distribution layer = as described in item 1 is used for etching on a semiconductor device, in which the etching step of the titanium layer is a third etching. f luoride), peroxy, and each etchant contains hydrogen fluoride (hydrogen emulsified oxygen and deionized water. 7. As described in the patent application method ^ j method of forming a heavy cloth layer) used on a semiconductor device ^ Contains forming a patterned #, wherein the step of cladding and the titanium layer before the step of patterning the copper layer is layered on the copper layer, and the patterned copper layer and inscription are used. The step is to use the patterned Photoresist layer for mask 第20頁 594895Page 594 895 8、如申請專利笳图给! κ 形成-重佈層之方:第述之用以於-半導體裝置上 含形成一圖案化之/朵阳^在圖案化該銅層之步驟之前包 層、鋁層之步驟之德二=°亥鋼層上,以及在該圖案化銅 係使用該已圖案化;=層,制案化鈦層之步驟 (mask)而進行。 曰 μ已圖案化銘層作為遮罩 9、如申請專利範圍第 形成一重佈層之方法, 成該介電層。 1項所述之用以於一半導體裝置上 其中係以聚酸亞胺(Ρ 〇 1 y i m i d e )形8. If you apply for a patent, please give us a picture! κ Forming-re-layout layer: The first method used to form a patterned semiconductor layer on a semiconductor device is described in the first step of cladding and aluminum layer before the step of patterning the copper layer = ° On the Hai steel layer, and on the patterned copper system, the patterned copper layer is used to perform the step of masking the titanium layer. Said μ has a patterned layer as a mask. 9. The method of forming a redistribution layer as described in the scope of the patent application, to form the dielectric layer. Item 1 is used on a semiconductor device in the form of polyimide (P 〇 1 y i m i d e) 10、 一種用以形成一 其包含下列步驟: 導電線路於一 半導體裝置之方法 形成一鋁層於該半導體裝置上 使得該保護金屬層直接接10. A method for forming a semiconductor device comprising the following steps: forming a conductive layer on a semiconductor device to form an aluminum layer on the semiconductor device so that the protective metal layer is directly connected 形成一保濩金屬層於該鋁厣 觸該鋁層; 9 以形成一已圖案化保護金 但是使該已圖案化鋁層保 圖案化該保護金屬層和鋁層 層以及一已圖案化鋁層;以^ 除去該已圖案化保護金屬; 完整。 q 11Forming a metal retaining layer on the aluminum to contact the aluminum layer; 9 to form a patterned protective gold but to pattern the protective aluminum layer and the protective metal layer and the aluminum layer and a patterned aluminum layer ; Remove the patterned protective metal with ^; complete. q 11 594895 六 '申請翻範目 — 該圖案化該銅層步驟以及該已圖案化銅層除去步驟包含以 二,一餘刻劑蝕刻該銅層,該第一蝕刻劑係為一稀釋1硝 酸溶液包含硝酸(nitric acid)、去離子水、醋酸以及過 氧化氫。 t 1 2、如申請專利範圍第1 0項所述之用以形成一導電線路 =一半導體裝置之方法,其中該圖案化鋁層步驟包含以一 第二敍刻劑蝕刻該鋁層之步驟,該第二蝕刻劑係為一稀釋 之碟酸溶液包含磷酸(phosphoric acid)、去離子水 (deionized water)、醋酸(acetic acid)。 13、如申請專利範圍第1 0項所述之用以形成一導電線路 於一半導體裝置之方法,其中該已圖案化保護金屬層除去 步驟係利用一電化學I虫刻製程達成。 14、如申請專利範圍第10項所述之用以形成一導電線路 於一半‘體裝置之方法,另包含在鋁層形成步驟之前,形 成一鈦層於該半導體裝置上,並且使用該已圖案化保護金 屬層以及該已圖案化鋁層作為遮罩(mask)而蝕刻該鈦層。_ 15、如申請專利範圍第10項所述之用以形成一導電線路 於一半導體裝置之方法,另包含在鋁層形成步驟之前,形 成一鈦層於該=導體裝置上,並且其中在圖案化該保護金 屬層之步驟之别包含形成一圖案化之光阻層於該保護金屬594895 Six 'application reversal — The step of patterning the copper layer and the step of removing the patterned copper layer include etching the copper layer with two or one etchant, the first etchant is a diluted 1 nitric acid solution containing Nitric acid, deionized water, acetic acid, and hydrogen peroxide. t 1 2. The method for forming a conductive line = a semiconductor device as described in item 10 of the scope of patent application, wherein the step of patterning the aluminum layer includes the step of etching the aluminum layer with a second etching agent, The second etchant is a diluted dish acid solution containing phosphoric acid, deionized water, and acetic acid. 13. The method for forming a conductive circuit in a semiconductor device as described in item 10 of the scope of patent application, wherein the step of removing the patterned protective metal layer is achieved by an electrochemical I-etching process. 14. The method for forming a conductive circuit on a half-body device as described in item 10 of the scope of patent application, further comprising forming a titanium layer on the semiconductor device before the aluminum layer forming step, and using the patterned The protective metal layer and the patterned aluminum layer serve as a mask to etch the titanium layer. _15. The method for forming a conductive circuit on a semiconductor device as described in item 10 of the scope of patent application, further comprising forming a titanium layer on the conductive device before the aluminum layer forming step, and in which The step of patterning the protective metal layer includes forming a patterned photoresist layer on the protective metal. 594895 六、申請專利範圍 層上,該圖案化保護金屬層、鋁層以及欽層之步驟係利用 該圖案化之光阻層為遮罩而進行。 16、 如申請專利範圍第1 4或1 5項所述之用以形成一導電 線路於一半導體裝置之方法,其中該欽層餘刻步驟係以一 第三I虫刻劑進行|虫刻,該第三颠刻劑包含氫氧化銨 (ammonium hydroxide)、過氧化氫以及去離子水。594895 6. Scope of patent application On the layer, the step of patterning the protective metal layer, the aluminum layer, and the layer is performed by using the patterned photoresist layer as a mask. 16. The method for forming a conductive circuit on a semiconductor device as described in item 14 or 15 of the scope of the patent application, wherein the remaining step of the thin layer is performed with a third I insect engraving agent | insect engraving, The third etching agent includes ammonium hydroxide, hydrogen peroxide, and deionized water. 17、 如申請專利範圍第1 4或1 5項所述之用以形成一導電 線路於一半導體裝置之方法,其中該鈦層餘刻步驟係以一 第三蝕刻劑進行蝕刻,該第三蝕刻劑包含氟化氢 ” (hydrogen fluoride)、過氧化氫以及去離子水。17. The method for forming a conductive circuit in a semiconductor device as described in item 14 or 15 of the scope of the patent application, wherein the remaining step of the titanium layer is etched with a third etchant, and the third etch The agent contains hydrogen fluoride, hydrogen peroxide, and deionized water.
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