TW591734B - IC tester system for eliminating electrostatic discharge damage - Google Patents
IC tester system for eliminating electrostatic discharge damage Download PDFInfo
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- TW591734B TW591734B TW92108280A TW92108280A TW591734B TW 591734 B TW591734 B TW 591734B TW 92108280 A TW92108280 A TW 92108280A TW 92108280 A TW92108280 A TW 92108280A TW 591734 B TW591734 B TW 591734B
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591734 五、發明說明(l) 發明所屬之技術領域 本發明係提供一種IC元件測試系統,尤指一種可防 靜電破壞之I C元件電性電量測試系統。 先前技術 在I C晶片製造過程中,產品的「可靠性 (reliability)」為非常重要的考量因素之一,可靠性可 簡單描述為產品在正常使用條件下,能順利工作的使用 期限。I C製造業者為了能在短時間内得知產品的使用壽 命,通常會使用「加速壽命測試實驗」(Accelerated 1 i feti me test)來預測產品的平均使用壽命,其方式是 利用比正常工作條件更嚴格的工作環境,例如在較高的 環境溫度、電壓、電流或壓力下進行產品壽命測試,求 得產品在惡化條件下的壽命,再利用生命期模型 (Lifetime Model)計算出產品在正常使用條件下的壽 命。一般I C廠的可靠性測試依其測試方法可以分為「晶 圓層次」(Wafer-Level Reliability, WLR)及「封裝層 次」(Package-Level Reliability,PLR)二種,前者是 將晶圓直接放入一般生產線上的測試機台做測試,而後 者則是先將晶圓切割封裝成一顆顆的測試樣本,然後將 這些樣本插入測試板,再將其放置於特殊的高溫^内做 測試。其_「封裝層次」可靠性測試的壽命測試實驗條591734 V. Description of the invention (l) The technical field to which the invention belongs The present invention provides an IC component test system, and more particularly, an IC power component test system capable of preventing electrostatic damage. Prior Technology In the IC chip manufacturing process, the "reliability" of a product is one of the most important considerations. Reliability can be simply described as the life span of a product under normal use conditions. In order to know the service life of a product in a short time, IC manufacturers usually use the "Accelerated 1 i feti me test" to predict the average service life of the product by using more than normal working conditions. Strict working environment, such as product life test under high ambient temperature, voltage, current or pressure, to determine the life of the product under deteriorating conditions, and then use the Lifetime Model to calculate the product under normal use conditions Life. The reliability test of general IC factories can be divided into "Wafer-Level Reliability (WLR)" and "Package-Level Reliability (PLR)" according to their test methods. The former is to directly place the wafer The test is performed on a test machine on a general production line, and the latter first cuts and packages the wafer into test samples, then inserts these samples into the test board, and then places them in a special high temperature for testing. Its_ "packaging level" life test experiment strip for reliability test
591734 五、發明說明(2) " " 件(stress c〇nditi〇n)較接近產品正常工作條件,結果 也較為業界所接受。 ^ 目A 1 C晶片廠最常使用的封裝層次I C晶片電性測試 ,,係如圖一所示,圖一為習知一丨c測試設備i 0的外觀 示忍圖丄1 C晶片測試設備1 0包含一溫度控制爐體1 2、以 及一耐^溫材料1 6,如橡膠,固定地設於爐門1 4内外兩 側。耐南溫材料丨6係用於隔絕溫度控制爐内外之溫度, 其上有數個切開之細長開口 18,供測試板(DUT b〇ard)3〇 穿過而插於爐門i 4上。測試板3 〇包含有一待測元件插槽 (socket) 34,用以放置一待測元件32,例如一待測ic, 一測試導線3 6,以及一測試介面(或稱為金手指)3 8,用 以連接一測試單元之連接埠(未顯示)。在進行測試時, 將封裳成/則试樣本的待測元件(d e v丨c e u n d e r t e s t, DUT) 32裝置於測試元件插槽34上,並將測試板3〇以人工 方式插入爐門1 4上耐高溫材料之細長開口 1 8 ,接著將爐 =1 4關閉’然後利用溫度控制爐提供可靠性測試所需之 高溫環境,測試線路提供電流、電壓以進行測試。 然而’習知I C晶片電性測試設備1 〇的設計上有無法 防止靜電破壞待測元件之缺失:當操作人員將測試板3 0 穿過耐高溫材料之細長開口 1 8插於爐門1 4上(1 oad i ng DUT boards)時,測試板30上的測試介面38及板面導電處 與該耐高溫材料1 6會相互摩擦產生靜電現象,破壞待測591734 V. Description of the invention (2) " " Pieces (stress c〇nditi〇n) are closer to the normal working conditions of the product, and the results are more acceptable to the industry. ^ Head A 1 C chip factory's most commonly used package level IC chip electrical test, shown in Figure 1, Figure 1 shows the appearance of conventional test equipment i 0 丄 1 C chip test equipment 10 includes a temperature-controlling furnace body 12 and a temperature-resistant material 16 such as rubber, which are fixedly arranged on the inner and outer sides of the furnace door 14. South temperature resistant material 丨 6 is used to isolate the temperature inside and outside the temperature control furnace. There are several slits 18 which are cut open for the test board (DUT b〇ard) 30 to pass through and insert on the furnace door i 4. The test board 3 includes a socket 34 for testing a component, such as a test IC, a test lead 36, and a test interface (also referred to as a gold finger) 38. , Used to connect a port (not shown) of a test unit. During the test, a device under test (dev 丨 ceundertest (DUT)) 32 is mounted on the test element slot 34, and the test board 30 is manually inserted into the furnace door 14 to withstand the test. The slender opening of the high-temperature material is 18, then the furnace is turned off, and the temperature control furnace is used to provide the high-temperature environment required for reliability testing. The test circuit provides current and voltage for testing. However, the design of the conventional IC chip electrical test equipment 10 cannot prevent static electricity from damaging the component under test: when the operator inserts the test board 3 0 through the slender opening of the high temperature resistant material 1 8 into the furnace door 1 4 (1 oad i ng DUT boards), the test interface 38 on the test board 30 and the conductive surface of the board and the high temperature resistant material 16 will rub against each other to generate static electricity, which will destroy the test.
591734591734
五、發明說明(3) 元件,導致在尚未正式測試電性時’元件就已遭靜電破 壞而失去正常功能。同樣地’在測試完成後’操作人員 將測試板30從爐門14取下(unloading)時’也會因為與摩 擦產生靜電破壞元件,造成莫大之損失。 目前針對習知I C晶片電性測試設備之缺失的補救方 法,一般是使用由測試設備原廠所提供的特殊夾具,在 將測試樣本放置於測試元件插槽時,先以該特殊夾具封 閉每一顆I C待測元件,使操作人員將測試板插於爐門上 時不會有靜電產生,然後在進行電性測試前,再將每—V. Description of the invention (3) The component has caused that the component has been damaged by static electricity and lost its normal function before the electrical test has been formally tested. Similarly, "after the test is completed," when the operator unloads the test board 30 from the furnace door 14, the element is destroyed by static electricity due to friction, which causes a great loss. The current remedy for the lack of conventional IC chip electrical test equipment is generally to use a special fixture provided by the original test equipment factory. When placing the test sample in the test component slot, each special fixture is first used to close each An IC to be tested, so that the operator will not generate static electricity when inserting the test board on the furnace door, and then before conducting the electrical test,
顆待測元件上之夾具--拆下,才能進行測試;測試完 畢’操作人員欲將測試板取下之前,同樣也必須先裝上 原廠所附之防靜電夹具,才能取下測試板。此利用夾具 的方法雖然可以防止靜電產生,但在執行電性測試時必 須花費很多時間裝設、取下夾具,步驟也非常麻煩,甚 至當操作人員在裝設夾具時,也可能因為步驟之繁複導 严人為疏失而破壞了待測元件,仍然無法有效提昇電性 巧試之成本與效果。因此一種操作步驟簡單的防靜電破 壞之I C晶片電性測試設備實為當前丨c製造廠所急切需要Remove the fixture on the component to be tested before testing; after the test is completed, the operator must also install the anti-static fixture attached to the factory before removing the test board. Although this method using a fixture can prevent the generation of static electricity, it must take a lot of time to set up and remove the fixture when performing electrical tests, and the steps are very cumbersome. Even when the operator sets up the fixture, the steps may be complicated. The stringent man-made negligence has damaged the device under test, and it still cannot effectively improve the cost and effect of electrical testing. Therefore, an IC chip electrical test equipment with simple anti-static damage operation steps is an urgent need for current c manufacturers.
發明内容 本發明之主要目的在於提供一種可防靜電破壞之IcSUMMARY OF THE INVENTION The main object of the present invention is to provide an Ic which can prevent electrostatic damage.
591734 五、發明說明(4) 元件測試系 在本發明之申請專利範圍中,揭露了 一種防靜電破 壞之I C測試系統,該I C測試系統包含有一溫度控制爐與 至少一 I C元件測試板。該溫度測試爐包含有一溫度控製 爐體、一爐門以及一設置於該爐門上之耐高溫材料。該 I C元件測試板包含有一電路板體、至少一待測元件插 槽、一測試介面、一接地介面、一測試導線及一虛置導 線。其中在該I C元件測試板載入/載出過程中,該測試導 線與該耐高溫材料因摩擦所產生之靜電,可利用該虛置 導線連接至該接地介面接地導出。 本發明之防靜電破壞I C測試系統,設置有一虛置導 線及一接地介面,能夠將因測試導線與耐高温材料摩擦 所產生之靜電在測試前預先接地導出,避免靜電破壞IC 待測元件,有效改善習知設備之缺陷,進而提升I C電性 電量測試之準確度。 徵 發 特附本 之與對 明明來 發說用 本細非 解詳並 了之, 步明用 1發明 進本說 更關與 能有考 員下參 委以供 杳一閱僅 審參式 貴請圖。 ,附者 使容所制 了内而限 為術然以 技。加 及圖明591734 V. Description of the invention (4) Component testing system In the scope of the patent application of the present invention, an antistatic-damaged IC test system is disclosed. The IC test system includes a temperature control furnace and at least one IC component test board. The temperature test furnace includes a temperature-controlled furnace body, a furnace door, and a high-temperature resistant material disposed on the furnace door. The IC component test board includes a circuit board body, at least one slot for a component under test, a test interface, a ground interface, a test lead, and a dummy lead. During the loading / unloading process of the IC component test board, the static electricity generated by the test lead and the high temperature resistant material due to friction can be connected to the ground interface through the dummy lead to be grounded. The anti-static destruction IC test system of the present invention is provided with a dummy wire and a ground interface, which can pre-earth the static electricity generated by the friction between the test wire and the high temperature resistant material before the test, so as to prevent the static electricity from damaging the IC test component, which is effective. Improve the defects of the conventional equipment, and then improve the accuracy of the IC electrical power test. The collection of the special appendix and the explanation of the use of Mingming to explain the details, step by step into the book with 1 invention is more relevant and able to have an examiner under the commission for review. Illustration. The affiliate made Rongsuo's internal and limited skills to be technical skills. Plus
第8頁 591734Page 8 591734
請參考圖二,圖二為本發明IC元件測試系統5 〇之示 意圖。如圖二所示,本發明丨c元件測試系統5 〇包含有二 溫度控制爐60與一 1C元件測試板70二部分。溫度控制爐 6 0包含有一溫度控制爐體62,用以提供κ待測元件適當 的測試溫度,一連接於溫度控制爐體上之爐門64,以^ 一耐高溫材料6 6,如橡膠,固定設置於爐門6 4上,用以 隔絕控制爐内外之溫度,其上具有數個切開之細長開口 6 8。I C元件測試板7 0包含有一電路板體7 1,一待測元件 插槽72設置於電路板體71上,用以裝置一 IC待測元件 以,一測試介面73,用以連接一測試單元之連接埠(未顯 示),一接地介面74,用以連接一接地之連接埠8〇,一^ 試導線75,用以連接待測元件插槽72與測試介面73,以、 及一虛置導線76,用以連接測試導線75與接地介面74。 其中在本實施例中為了簡化說明,IC元件測試系統5〇僅 包含有一 I C元件測試板7 0,而I c元件測試板7 〇亦僅包含 有一 I C待測元件插槽7 2。然而依實際狀況需要本發明j c 測試系統50可包含有複數個ic元件測試板7〇,且每一 κ 凡件測試板70均可包含有複數個待測元件插槽72,可 納複數個1C待測元件78進行測試。 在進行測試時,首先將1C待測元件78之接腳插入待 々π件插槽7 2之相對應孔洞中,使j c待測元件固定於待 測疋件插槽72上,接著將接地介面74與一接地之連接埠Please refer to FIG. 2, which is a schematic diagram of the IC component test system 50 of the present invention. As shown in FIG. 2, the c-component test system 50 of the present invention includes two temperature control furnaces 60 and a 1C-component test board 70. The temperature-controlling furnace 60 includes a temperature-controlling furnace body 62 for providing an appropriate test temperature for the κ component to be tested, a furnace door 64 connected to the temperature-controlling furnace body, and a high-temperature resistant material 66, such as rubber, It is fixed on the furnace door 64 to isolate and control the temperature inside and outside the furnace. The IC component test board 70 includes a circuit board body 71, and a socket 72 to be tested is provided on the circuit board body 71 for mounting an IC to be tested, and a test interface 73 for connecting a test unit. A connection port (not shown), a grounding interface 74 for connecting a grounding connection port 80, a test lead 75 for connecting the component under test socket 72 and the test interface 73, and a dummy The lead 76 is used to connect the test lead 75 and the ground interface 74. In this embodiment, in order to simplify the description, the IC component test system 50 only includes an IC component test board 70, and the IC component test board 70 only includes an IC test component slot 72. However, according to the actual situation, the jc test system 50 of the present invention may include a plurality of ic component test boards 70, and each of the κ test boards 70 may include a plurality of test component slots 72, which may accommodate a plurality of 1C. The device under test 78 is tested. When testing, first insert the pins of the 1C device under test 78 into the corresponding holes in the socket 7 2 of the device to be tested, fix the jc device under test on the device socket 72, and then connect the ground interface 74 and a grounded port
591734 五、發明說明(6) |連接80,,將待測元件測試板7〇以人工方式由 側載入耐尚溫材料66之細長開口 68, 70固定於爐門64上,此時因 T牛:則试板 與耐高溫材料66摩捧所產生 < 靜電合p f,貝,"式導線75 過與接地介面虛== bt接Ϊ =除並關閉爐門64,再將測試介面73與一 測试早π之連接埠(未顯示)電連接, 進行電性電量測試。 V彳余仔下 當測試完成後,首先將測試單元之連接埠(未顯示) 自測試介面73拔除,接著開啟爐門64並將接地介面74與 一接地之,接埠8 0連接,然後以人工方式將丨〇元件測試 |板7 0由耐咼溫材料6 6載出,此時因摩擦所產生之靜電會 |經由虛置導線76透過與接地介面74連接之接地之連接埠 8 0接地導出,最後將接地之連接埠8 〇拔除,並將! c待測 元件78自待測元件插槽72取下,即完成1C元件之測試工 丨作。 相較於習知I C元件測試設備,本發明I c元件測試系 統於I C元件測試板上設計了 一虛置導線與一接地介面, 能將因I C元件測試板上之測試導線與溫度控制爐門上之 高耐熱材料摩擦所產生之靜電直接接地導出,避免靜電 |破壞I C待測元件’故可有效改善習知設備之缺點,提升 I C電性測試之準確率。 1^· 第10頁 591734 五、發明說明(7) 以上所述僅為本發明之較佳實施例,凡依本發明申 請專利範圍所做之均等變化與修飾,皆應屬本發明專利 之涵蓋範圍。591734 V. Description of the invention (6) | Connect 80, and manually load the test board 70 of the device under test into the slender openings 68, 70 of the refractory material 66 from the side, and fix it on the furnace door 64. Bull: Then the test plate and the high-temperature resistant material 66 are combined to produce <static electrostatic pf, shell, " type wires 75. The ground interface is imaginary == bt is connected. = The furnace door 64 is closed and the test interface 73 Electrically connected to a test port (not shown) for early electrical testing. V. When Yu Zi finished the test, first unplug the test unit's port (not shown) from the test interface 73, then open the furnace door 64 and connect the ground interface 74 to a ground, port 80, and then Test the component manually by manual method | The board 70 is carried by the high temperature resistant material 66. At this time, the static electricity generated by friction will be grounded through the dummy wire 76 through the grounding port 80 connected to the grounding interface 74. Export, and finally unplug the grounded port 〇! c The component to be tested 78 is removed from the component to be tested socket 72, and the test of the 1C component is completed. Compared with the conventional IC component test equipment, the IC component test system of the present invention is designed with a dummy wire and a ground interface on the IC component test board. The static electricity generated by the friction of the high heat-resistant material is directly grounded to avoid static electricity | destroying the IC test component ', so it can effectively improve the shortcomings of the conventional equipment and improve the accuracy of the electrical test of the IC. 1 ^ · Page 10 591734 V. Description of the invention (7) The above description is only a preferred embodiment of the present invention. Any equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall be covered by the patent of the present invention. range.
第11頁 591734 圖式簡單說明 圖式之簡單說明 圖一為習知IC元件測試設備之示意圖。 圖二為本發明I c元件測試系統之示意圖。 圖式之符號說明Page 11 591734 Brief description of the drawings Brief description of the drawings Figure 1 is a schematic diagram of a conventional IC component test equipment. FIG. 2 is a schematic diagram of the IC component testing system of the present invention. Schematic symbol description
第12頁 10 1C元 件 測 試 設 備 12 溫度 控 制 爐 體 14 爐門 16 而才南 溫 材 料 18 财高 溫 材 料 上 之細長開 σ 30 I C測 試 板 32 im 測 元 件 34 1C待 測 元 件 插 槽 36 測試 導 線 38 測試 介 面 50 1C元 件 測 試 系統 60 溫度 控 制 爐 62 溫度 控 制 爐 體 64 爐門 66 耐南 溫 材 料 68 而ί南 溫 材 料 上 之灸 3長開 α 70 I C測 試 板 71 電路 板 體 72 1C待 測 元 件 插 槽 73 測試 介 面 74 接地 介 面 75 測試 導 線 76 虛置 導 線 78 1C待 測 元 件 80 接地 連 接 埠Page 12 10 1C component testing equipment 12 Temperature control furnace body 14 Furnace door 16 Nannan material 18 Slender opening on high temperature material 30 IC test board 32 im Test element 34 1C Test element slot 36 Test lead 38 Test interface 50 1C component test system 60 Temperature control furnace 62 Temperature control furnace body 64 Furnace door 66 South temperature resistant material 68 And the moxibustion on South temperature material 3 Long open α 70 IC test board 71 Circuit board body 72 1C component under test Slot 73 Test interface 74 Ground interface 75 Test lead 76 Dummy lead 78 1C DUT 80 Ground connection port
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10041995B2 (en) | 2015-01-15 | 2018-08-07 | Amazing Microelectronic Corp. | Test method for eliminating electrostatic charges |
CN108414911A (en) * | 2018-03-01 | 2018-08-17 | 上海华岭集成电路技术股份有限公司 | The wide temperature test method of semiconductor |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US10041995B2 (en) | 2015-01-15 | 2018-08-07 | Amazing Microelectronic Corp. | Test method for eliminating electrostatic charges |
CN108414911A (en) * | 2018-03-01 | 2018-08-17 | 上海华岭集成电路技术股份有限公司 | The wide temperature test method of semiconductor |
CN108414911B (en) * | 2018-03-01 | 2020-04-14 | 上海华岭集成电路技术股份有限公司 | Semiconductor wide temperature testing method |
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