TW589738B - ONO flash memory array for alleviating interference of adjacent memory cells - Google Patents

Abstract

There is provided an ONO flash memory array for alleviating interference of adjacent memory cells, in which a pocket is implanted at the vicinity of single channel side of each memory cell, or pockets of different concentrations are implanted at the vicinity of two channel sides, so that each memory cell has asymmetrical pockets. Therefore, when performing pocket-to-pocket programming or erasing, the memory array is not interfered by the adjacent memory cells. In addition, it is able to reduce the interference of adjacent memory cells in reading.

Description

589738 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a flash memory, and more particularly to a 0 N 0 flash memory array for improving the interference of adjacent memory cells. The first diagram of the prior art shows two flash memory arrays 100, 102 and 104, including a substrate 106, an ONO (Oxide-Nitride-Oxide) layer 108, polysilicon 1 10, and 1 1 2, bit lines 1 1 4, 1 1 6 and 1 1 8, buried diffusion regions 120, 122, and 124, oxide layer 126, word line 128, and channels 130 and 132. As shown in the figure, the 0N0 layer 108 is on the substrate 106, the polycrystalline silicon 110, 112, and the oxide layer 1 2 6 are on the 0 Ν 0 layer 108, and the bit line 1 1 4 is in the substrate on the right side of the polycrystalline silicon 1 1 0. Element line 1 1 6 is in the substrate between polycrystalline silicon 1 1 0 and 1 12, bit line 1 1 8 is in the substrate on the left side of poly silicon 1 12, and the buried diffusion regions are covered by 2 0, 122, and 124, respectively. Around bit lines 114, 116, and 118, word line 128 is two polycrystalline silicons 10 and 12; channel 13 is between buried diffusion regions 120 and 122; channel 132 is between buried diffusion regions 22 and 124. between. When the conventional flash memory array 100 uses band-to-band programming and erasing a certain memory cell, such as the data in the first-middle: 0: 108 data 136, it may interfere with its adjacent The data 134 in the memory cell ΓΛΛ cell 102 is also stylized or erased. "Similarly" in the item fetching § self-memory cell 丨 〇4, when it is 6 and 6, it is disturbed, and the correct data. This is to reduce the d = the flash memory, the series is to reduce the stray generated by the stylization and erasure by adding an extra bias to the source [for example, the cell in the first figure

Page 6 589738 V. Description of the invention (2) '-Yuan 1〇2_, which is supplied with a voltage of _5V to the word line 128, a voltage of + 5V to the bit line 116, and an additional bias of + 3V Press to bit line U4. However, adding an extra bias voltage will increase the energy consumption and the complexity of the control circuit. Therefore, a flash memory array that does not require additional bias voltage and can avoid interference with adjacent cells during programming and erasure. Expect it. SUMMARY OF THE INVENTION The object of the present invention is to disclose a 0 N 0 flash memory array for improving the interference of adjacent memory cells. Another object of the present invention is to provide an asymmetric flash memory cell. According to a first embodiment of the present invention, a 0 N 0 flash memory array for improving interference of adjacent memory cells includes a substrate, a 10 N0 layer on the substrate, and a gate on the 0 N0 layer. Word lines are on the gate, a first and a first bit line are respectively in the base on both sides of the gate, and a first and a second buried diffusion area respectively cover the first and the first in the base. In the two-bit line, a channel is between the first and second buried diffusion regions, and a first and second pocket are adjacent to the first and second buried diffusion regions near the sides of the channel, respectively. According to a second embodiment of the present invention, an ON0 flash memory array for improving interference of adjacent memory cells includes a substrate, a ON0 layer on the substrate, a gate on the ON0 layer, and a word line in On the gate, a first and a second bit line are respectively in the base on both sides of the gate, and a first and a second buried diffusion area respectively cover the first and second bit lines in the base. ,

Page 7 589738 V. Description of the invention (3) A channel is between the first and second buried diffusion regions, and a pocket is adjacent to the first buried diffusion region near one side of the channel ^. The present invention utilizes the asymmetry of the concentration of the unilateral pockets or the pockets on both sides of the channel, so that the memory array does not interfere with its neighboring cells when using the band-to-band programming and erasing memory cells. The memory cell can also suppress interference during reading. The second diagram of the embodiment is a 0N0 flash memory array 200 of the present invention for improving the interference of adjacent memory cells, which shows two memory cells 2 0 2 and 2 04. The memory array 2 0 0 includes a substrate 2 0 6, 100N0 layer 20 8. Polycrystalline silicon 210 and 212 as gates, bit lines 214, 216, and 218, buried diffusion regions 2 2 0, 222, and 2 24, oxide layer 2 2 6, word lines 228 , Pockets 2 3 0 and 2 3 2 and channels 234 and 236. As shown in the figure, the ON0 layer 208 is on the substrate 206, the polycrystalline silicon 210, 212, and the oxide layer 2 2 6 are on the ON0 layer 208, and the bit line 214 is in the substrate on the right side of the polycrystalline silicon 2 1 0, and the bit line 2 1 6 In the substrate between polycrystalline silicon 2 1 0 and 2 1 2, bit line 218 is in the substrate on the left side of polycrystalline silicon 212, and buried diffusion regions 220, 222, and 224 surround the bit lines 214, 216, and 218, respectively. The word line 2 2 8 connects the two polycrystalline silicon gates 2 10 and 212. The channel 2 34 is between the buried diffusion regions 2 2 0 and 2 2 2 and the channel 2 3 6 is between the buried diffusion regions 2 2 2 and 2 24. In between, pocket 2 3 0 is adjacent to the buried diffusion area 2 2 0 near the right side of the channel 2 34, and pocket 232 is adjacent to the buried diffusion area 22 2 near the right side of the channel 236. The third figure is the second embodiment in use Tape-to-belt stylization or erasure of the hole injection current on both sides of the common bit line (h 〇1 einjecti ο η

589738 V. Description of the invention (4) current) Taking bit line 216 as an example, the waveforms 2 3 8 and 240 are the hole injection currents generated on the left and right sides of bit line 2 1 6 respectively. Since the bit line 2 1 6 has a pocket 2 3 2 on the left side, when a voltage is applied to the bit line 2 1 6 to program or erase the cell 2 0 4, the hole generated on the left side of the bit line 2 1 6 The injection current is larger 'as shown by the waveform 2 38 in the third figure' and the hole injection current generated on the right side of the bit line 2 1 6 is smaller as shown by the waveform 2 40 in the third figure. Since the pocket 232 is provided on the right side of the channel 236, a larger hole is injected during programming or erasing. The larger the hole injection current, the faster the programming and erasing speed. Therefore, the cell 2 0 4 is programmed. And the speed of erasing data is high, so when cell 204 is stylized or erased, it does not affect neighboring cells 202. When reading the data of cell 202, there is no implanted pocket on the left side, so the probability of collision of ions is reduced, thereby reducing the interference generated during reading. In addition, an additional bias voltage can be added to the bit line 2 1 4 to obtain better results. The embodiment of the second diagram is the second diagram. When programming or erasing data, the drain voltage and Current relationship diagram, where curve 2 4 2 is the relationship between the drain voltage and current when the buried diffusion area is adjacent to a pocket. Curve 2 4 4 is the drain voltage and current when there is no pocket near the buried diffusion area. The relationship between the ife line and the curve 2 4 6 is the relationship between the drain voltage and the current under the shape of a pocket with no pocket near the buried diffusion area and an additional 3V bias added to the source of the memory cell. In the case of implant = bag, the surge current generated is greater than that without implant in the pocket, and the source increase / extra bias of the remembered cell can obtain a better result. Δ 'The memory array 3 0 shown in the fifth figure is the second implementation of the present invention

589738 V. Description of the invention (5) Example, which shows two memory cells 3 202 and 3 04. The memory array 300 also includes the substrate 206, ONO layer 208, polycrystalline silicon 210 and 212, bit line 214, 216 and 218, buried diffusion regions 2 2 0, 2 2 2 and 2 24, oxide layer 2 2 6, character lines 2 2 8, pockets 2 3 0 and 2 3 2 and channels 2 34 and 2 3 6. The difference between the memory array 300 and the memory array 2000 of the second figure is that pockets 3 06 and 3 0 8 are also implanted near the left side of channels 2 34 and 2 3 6 in the memory array 3, but pocket 3 The concentrations of 0 6 and 3 0 8 are lower than those of the pockets 2 3 0 and 2 3 2 respectively, so that when the cell 304 is stylized or erased, the hole generated by the bit line 216 or the left side of the buried diffusion region 222 is implanted. The current is higher than the right side, so it will not affect cell 302 '. When reading the data of cell 302, the concentration of the left pocket is low, so the probability of ion collision is reduced, which reduces the interference generated during reading. . The above description of the preferred embodiment of the present invention is for the purpose of clarification, and is not intended to limit the present invention to the precise form disclosed. Modifications or changes are possible based on the above teachings or learning from the embodiments of the present invention. The embodiments are selected and described in order to explain the principle of the present invention and allow those skilled in the art to use the present invention in practical applications in various embodiments. The technical idea of the present invention is intended to be based on the scope of the following patent applications and their equivalents. Decision 0

589738 Schematic description for those skilled in the art, from the following detailed description and accompanying drawings, the present invention will be more clearly understood, its above and other objectives and advantages will become It is more obvious, in which: the first picture is a conventional flash memory array; the second picture is a first embodiment of the present invention; the third picture is shared by the present invention when using tape-to-tape programming or erasing cells The holes on both sides of the bit line inject current; the fourth diagram is a diagram of the relationship between the drain voltage and the current when the present invention is stylized; and the fifth diagram is a second embodiment of the present invention. DESCRIPTION OF Schematic Symbols 100 Flash Memory Membrane Array 102 Memory Cells 104 Memory Cells 106 Substrate 108 ION layer 110 Polycrystalline silicon 112 Polycrystalline silicon 114 bit lines 116 bit lines 118 bit lines 120

589738 Brief description of the diagram 124 Buried diffusion area 126 Oxidation layer 128 Word line 130 Channel 132 Channel 134 Data 136 Data 200 Flash memory array 202 Memory cell 204 Memory cell 206 Base 208 ONO layer 210 Polycrystalline silicon 212 Polycrystalline silicon 214 bit Line 216 bit line 218 bit line 220 buried diffusion area 222 buried diffusion area 224 buried diffusion area 226 oxide layer 228 word line 230 pocket 232 pocket

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589738 Diagram brief description 2 34 Channel 2 3 6 Channel 2 3 8-bit line 2 1 6 Hole injection current on the left 2 4 0 Bit line 2 1 6 Hole injection current on the right 24 2 Drain voltage with pocket Curve with current 244 Drain voltage vs. current curve without pocket 2 4 6 Curve with no pocket voltage and current when extra bias is added to the source 3 0 0 Flash memory array

3 0 2 Memory Cell 3 04 Memory Cell 306 308 Pocket Pocket

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Claims (1)

58-9738 VI. Scope of patent application 1. A NAND flash memory array for improving interference of adjacent memory cells, comprising: a substrate having a first and a second buried diffusion region; a channel in the first And a second buried diffusion area; a ON0 layer above the channel for storing data; a first pocket on one side of the channel adjacent to the first buried diffusion area, having a first concentration; and A second pocket, on the other side of the channel, is adjacent to the second buried diffusion region and has a second concentration. 2. The memory array according to item 1 of the patent application, wherein the first concentration is greater than the second concentration. 3. A kind of ONO flash memory array for improving the interference of adjacent memory cells, comprising: a substrate with a first and a second buried diffusion region; a channel in the first and the second buried diffusion region; A 0N0 layer on the channel for storing data; and a pocket on one side of the channel adjacent to the first buried diffusion zone. Page 14