02405twf2.doc/006 修正日期92.7.9 玖、發明說明： 本發明是有關於一種用於多値邏輯與類比式快閃記憶 體之操作方法，且特別是有關於一種多値邏輯/類比式之 快閃記憶體操作方法，使其臨限電壓與汲極編碼時間之線 性關係。 習知之快閃記憶體，其爲一種可抹除可編碼唯讀記憶 體（Erasable Programmable Read-Only Memory ; EPROM)。 通常EPROM有兩個閘極，其中一個爲多晶矽（Polysmcon) 製成的浮置閘，以及一控制資料存取的控制閘。浮置閘極 位於控制閘下方且處於浮置狀態沒有與任何線路連接，控 制閘則連接到字元線。 在操作一快閃記憶體電晶體時。於控制閘極施一閘極 電壓，並且同時於汲極施一汲極電壓，藉此得以編碼該快 閃記憶體。請參考第1圖，其繪示的是上述快閃記憶體電 晶體在編碼期間，快閃記憶體電晶體之臨限電壓 VTH(Thresh〇ld Voltage)與編碼時間之分佈示意圖。在編碼 時間q、t2、t3、t4，其對應的臨限電壓分別是VTH1、VTH2、 VtH3 ' VTH4 ° 在時段如期間，臨限電壓則分佈較鬆； 在時段如t3〜t4期間，臨限電壓則分佈較密。故習知之臨限 電壓係一非線性分佈，若欲得到等間距分布之VTH，則編 02405twf2.doc/006 修正日期92.7,9 碼時間爲非等間距分布，造成設計與製造上的不便。 再者，習知之快閃記憶體陣列中分享同一字元線之數 個記憶體胞，在一閘極編碼電壓作用期間，上述之各個記 憶體胞僅能儲存或寫入相同的數據。因此，必須多次給予 閘極電壓來使各記憶體胞能儲存或寫入不同數據。因此要 以多個閘極電壓來達到多値邏輯的目的。並且，欲達m値 邏輯的目的，最少需要m-l次編碼操作。因此，習知的快 閃記憶體會有速度慢，費功率以及需要複雜的電壓產生電 路的缺點。 因此’本發明的主要目的就是在提供一種快閃記憶體 的操作方法，其臨限電壓與汲極編碼作用時間具有線性關 係，並且可做多値邏輯/類比式之操作模式。 爲讓本發明之上述和其他目的，提出一種快閃記憶體 的操作方法，此操作方法簡述如下：於快閃記憶體的閘極， 施一線性斜坡形或相似階梯式閘極編碼電壓，上述之線性 斜坡形或相似階梯式閘極編碼電壓之作用時間爲閘極編碼 時間。同時於快閃記憶體的汲極施一汲極編碼電壓，汲極 編碼電壓之作用時間爲汲極編碼電壓作用時間。其中汲極 編碼電壓作用時間，係將該閘極編碼時間做一線性分割， 使具有多重期間的特性，其中線性分割係將閘極編碼時間 做整數次分割，再取整數倍作爲該汲極編碼電壓作用時 間，用以對快閃記憶體做多値邏輯之操作。 588365 02405twf2.doc/006 修正日期 92.7.9 再者，對包含一主位元線、多數個字元線，以及多數 個次位元線之快閃記憶體陣列內的各字元線，施一線性斜 坡形閘極編碼電壓，線性斜坡形閘極編碼電壓之作用時間 爲閘極編碼時間。同時於該快閃記憶體陣列內的每一次位 元線施一汲極編碼電壓，汲極編碼電壓作用時間係將該閘 極編碼時間做一線性分割，使具有多重期間的特性。其中 該線性分割係將該閘極編碼時間做整數次分割，再取整數 倍作爲該汲極編碼電壓作用時間。故可對快閃記憶體陣列 做多値邏輯之操作。 綜上所述，本發明提供一快閃記憶體操作法，使快閃 記憶體電晶體的臨限電壓與汲極編碼作用時間是一線性關 係，並且有較緊密的臨限電壓分佈。又因僅需要單一閘極 電壓，配合具多重期間之汲極編碼電壓，便可有多値邏輯 的結果，因此更具有省時，省功率之優點。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉四個較佳實施例，並配合所附圖式，作 詳細說明如下： 圖式之簡單說明： 第1圖繪示習知之快閃記憶體其輸出臨限電壓與汲極 編碼作用時間之示意圖； 第2a圖繪示依照本發明之一種用於多値邏輯與類比 式快閃記憶體之操作方法，其適用施加於閘極的一些閘極 編碼電壓波形； 第2b圖繪示本發明之一種用於多値邏輯與類比式快 6 02405twf2.doc/006 修正臼期92.7.9 閃記憶體之操作方法，其閘極編碼時間與汲極編碼作用時 間之間的關係圖； 第3a圖繪示在一閘極編碼電壓下，不同汲極編碼電 壓所對應的有效閘極編碼電壓値； 第3b圖繪示在不同斜率之閘極編碼電壓與汲極編碼 電壓之關係圖； 第3c圖繪示本發明之用於多値邏輯與類比式快閃記 憶體之操作方法，其臨限電壓與閘極電壓關係之實驗結果 圖； 第3d圖繪示本發明之用於多値邏輯與類比式快閃記 憶體之操作方法，其臨限電壓與汲極編碼作用時間關係之 實驗結果圖； 第4a圖繪示本發明之用於多値邏輯與類比式快閃記 憶體之操作方法之第一實施例所用的一 P型通道快閃記憶 體之剖面圖； 第4b圖繪示本發明之用於多値邏輯與類比式快閃記 憶體之操作方法之第一實施例的時脈圖； 第4c圖繪示本發明之第一實施例之一結果圖； 第5a圖繪示本發明之用於多値邏輯與類比式快閃記 憶體之操作方法的第二實施例所用的一 P型通道快閃記憶 體之剖面圖； 第5b圖繪示本發明之用於多値邏輯與類比式快閃記 憶體之操作方法之第二實施例的時脈圖； 第6a圖繪示本發明之用於多値邏輯與類比式快閃記 02405twf2.doc/006 修正日期92.7.9 憶體之操作方法之第三實施例所用的一 N型通道快閃記憶 體之剖面圖； 第6b圖繪示本發明一種用於多値邏輯與類比式快閃 記憶體之操作方法之第三實施例的時脈圖； 第7a圖繪示本發明之用於多値邏輯與類比式快閃記 憶體之操作方法之第四實施例所用的一 P型通道快閃記憶 體之頗面圖； 第7b圖繪示本發明一種用於多値邏輯與類比式快閃 記憶體之操作方法之第四實施例的時脈圖； 第7c圖繪是本發明第四實施例之一結果圖； 第8A圖繪示的是控制汲極電壓之施加時間來使閘極 電壓呈現線性斜坡形式之實際電路圖； 第8B圖繪示的是控制汲極電壓之施加時間來使閘極 電壓呈現線性斜坡形式之實際電路圖中，觸發信號與電晶 體閘極與汲極間之電壓關係圖； 第9圖繪示的是控制汲極電壓之施加時間來使閘極電 壓呈現線性斜坡形式之實際電路圖中，閘極電壓產生器之 部份電路圖；以及 第1〇圖繪是的示控制汲極電壓之施加時間來使閘極 電壓呈現線性斜坡形式之實際電路圖中，汲極電壓產生器 之部份電路圖。 圖式中標示之簡單說明： 588365 02405twf2.doc/006 修正日期92.7.9 I、II、III :輸入閘極之不同的斜坡型編碼電壓 40 : 50 : N型基底 41，51，61，71 :源極區 42，52，62，72 :汲極區 43，53，63，73 :控制閘 44，54，64，74 :浮置閘 60，70 : P型基底 410，510，610，710 :編碼時期 411，511 :閘極編碼電壓 412，512，613，713 :閘極編碼時間 413，513，614，714 :汲極編碼電壓 414，514，615，715 :汲極編碼作用時間 420，520，620，720 :抹除時期 421，521，621，721 :閘極抹除電壓 422，522，622，722 :閘極抹除時間 611，711 :閘極電壓之上升邊緣電壓 612，712 :閘極電壓之下降邊緣電壓 623 :源極抹除電壓 624 :源極抹除時間 902 :計數器 02405twf2.doc/006 修正日期92.7.9 C :電容 D :汲極 G :閘極 NOR :反或閘 S :源極 T1 :電晶體 實施例 在對一快閃記憶體電晶體執行編碼操作時’在其閘極 施加一閘極編碼電壓（Gate Programming Voltage，簡稱 VGPI^g)以及在汲極施加一汲極編碼電壓（Drain Programming Voltage，簡稱VDpn)g)，用以編碼快閃記憶體。其中施於閘 極之閘極編碼電壓VCpn3g爲具有線性遞增或線性遞減之電 壓。第2a圖繪示一些適用於本發明之電壓波形，但非用 以對本發明設限。而施加於汲極的汲極編碼電壓VDpmg具 有多重期間（multi-duration)的特性。 請參考第2b圖說明汲極編碼作用時間的多重期間特 性，其繪示兩種不同之汲極電壓方波波形。圖中之tc20與 tc20’爲相對應的閘極編碼時間。 將tG20做m次分割，以得tD21〜tD2m，爲m個汲極 編碼作用時間，其中tD2m與tc20相等，且兩者具有下之 588365 02405twf2.doc/006 修正日期 92.7.9 關係：02405twf2.doc / 006 Revised date 92.7.9 发明 Description of the invention: The present invention relates to a method for operating multi-logic logic and analog flash memory, and more particularly to a method of multi-logic logic / analog. The flash memory operation method makes the threshold voltage and the drain coding time linear relationship. The conventional flash memory is an erasable and programmable read-only memory (EPROM). EPROM usually has two gates, one of which is a floating gate made of polysmcon, and a control gate that controls data access. The floating gate is located under the control gate and is floating and not connected to any line. The control gate is connected to the character line. When operating a flash memory transistor. A gate voltage is applied to the control gate and a drain voltage is applied to the drain at the same time, thereby encoding the flash memory. Please refer to FIG. 1, which shows a schematic diagram of the distribution of the threshold voltage VTH (Threshold Voltage) of the flash memory transistor and the encoding time during the encoding of the flash memory transistor. At the coding times q, t2, t3, and t4, the corresponding threshold voltages are VTH1, VTH2, and VtH3 'VTH4 ° During the period, such as the period, the threshold voltage is loosely distributed; During the period, such as t3 ~ t4, the threshold is The voltage is more densely distributed. Therefore, the conventional threshold voltage is a non-linear distribution. If you want to obtain the VTH with an equal interval, you can edit 02405twf2.doc / 006 to modify the date 92.7, and the 9-yard time is a non-equidistant distribution, causing inconvenience in design and manufacturing. Furthermore, in the conventional flash memory array, several memory cells sharing the same word line. During the application of a gate code voltage, each of the above memory cells can only store or write the same data. Therefore, the gate voltage must be given multiple times to enable each memory cell to store or write different data. Therefore, multiple gate voltages must be used to achieve the purpose of multiple logic. And, to achieve the purpose of m 値 logic, at least m-1 coding operations are needed. Therefore, the conventional flash memory has the disadvantages of slow speed, high power consumption and complicated voltage generation circuit. Therefore, the main purpose of the present invention is to provide a flash memory operation method, in which the threshold voltage has a linear relationship with the drain coding time, and can be operated in multiple logic / analog mode. In order to make the above and other objects of the present invention, a method for operating a flash memory is proposed. The operation method is briefly described as follows: a linear ramp or a similar stepped gate code voltage is applied to the gate of the flash memory. The action time of the linear ramp or similar stepped gate-coded voltage is the gate-code time. At the same time, a drain coding voltage is applied to the drain of the flash memory, and the drain coding time is the drain coding voltage time. The drain-coded voltage action time is a linear division of the gate-coded time, so that it has the characteristics of multiple periods. The linear division system divides the gate-coded time by an integer number of times, and then takes an integer multiple as the drain-coded The voltage application time is used to perform multiple logic operations on the flash memory. 588365 02405twf2.doc / 006 Amendment date 92.7.9 Furthermore, a line is applied to each character line in a flash memory array including a major bit line, a plurality of character lines, and a plurality of minor bit lines. The ramp ramp gate code voltage, the linear ramp gate code voltage acts as the gate code time. At the same time, a drain-coded voltage is applied to each bit line in the flash memory array. The drain-coded voltage action time is a linear division of the gate-coded time so as to have the characteristics of multiple periods. The linear division is performed by dividing the gate encoding time by an integer number of times, and then taking an integer multiple as the drain encoding time. Therefore, multiple logic operations can be performed on the flash memory array. In summary, the present invention provides a flash memory operation method, so that the threshold voltage of the flash memory transistor and the drain coding time have a linear relationship, and there is a tighter threshold voltage distribution. In addition, because only a single gate voltage is needed, and the drain-coded voltage with multiple periods is used, there can be multiple logic results, so it has the advantages of saving time and power. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, four preferred embodiments are given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: Section 1 Figure 2 shows a schematic diagram of a conventional flash memory output threshold voltage and drain coding time; Fig. 2a shows a method for operating multi-logic logic and analog flash memory according to the present invention. Applies to some gate-coded voltage waveforms applied to the gate; Figure 2b shows a method for multi-logic logic and analog fast 6 02405twf2.doc / 006 to modify the 92.7.9 flash memory operation method of the present invention, Figure 3a shows the relationship between the gate coding time and the drain coding time; Figure 3a shows the effective gate coding voltages corresponding to different drain coding voltages under a gate coding voltage; Figure 3b shows Relationship between gate-coded voltage and drain-coded voltage at different slopes; Figure 3c shows the operation method of the present invention for multi-logic logic and analog flash memory. The relationship between the threshold voltage and the gate voltage Experiment Result diagram; FIG. 3d shows an experimental result diagram of the operation method for multi-logic logic and analog flash memory according to the present invention, and the relationship between the threshold voltage and the drain coding time; FIG. 4a shows the present invention A cross-sectional view of a P-type flash memory used in the first embodiment of the method for operating multi-logic logic and analog flash memory; FIG. 4b illustrates the present invention for multi-logic logic and analogy. Clock diagram of the first embodiment of the flash memory operation method; FIG. 4c shows a result diagram of one of the first embodiments of the present invention; FIG. 5a shows the invention for multi-block logic and analogy Sectional view of a P-type flash memory used in the second embodiment of the flash memory operation method; FIG. 5b illustrates the operation method of the present invention for multi-logic logic and analog flash memory Clock diagram of the second embodiment; FIG. 6a shows the third embodiment of the method of operating the memory for the multi-logic logic and analog flash memory 02405twf2.doc / 006 of the present invention. Sectional view of an N-type flash memory; Section 6b FIG. 7 is a clock diagram of a third embodiment of a method for operating multi-logic logic and analog flash memory according to the present invention; FIG. 7a is a diagram illustrating a multi-logic logic and analog flash memory according to the present invention; A schematic diagram of a P-type flash memory used in the fourth embodiment of the method of operation; FIG. 7b illustrates a fourth implementation of an operation method for multi-logic logic and analog flash memory according to the present invention Fig. 7c shows a result diagram of a fourth embodiment of the present invention; Fig. 8A shows an actual circuit diagram for controlling the application time of the drain voltage to make the gate voltage take the form of a linear ramp; Figure 8B shows the actual circuit diagram of controlling the application time of the drain voltage to make the gate voltage take a linear slope. The relationship between the trigger signal and the voltage between the gate and the drain of the transistor; Figure 9 shows The actual circuit diagram that controls the application time of the drain voltage to make the gate voltage take the form of a linear ramp, part of the circuit diagram of the gate voltage generator; and Figure 10 shows the application time to control the application of the drain voltage to make the gate Extremely The actual pressure circuit diagram presented in the form of a linear ramp, portion of a circuit diagram of the drain voltage generator. Brief description marked in the figure: 588365 02405twf2.doc / 006 Date of revision 92.7.9 I, II, III: Different ramp-type coding voltage of the input gate 40: 50: N-type base 41, 51, 61, 71: Source regions 42, 52, 62, 72: Drain regions 43, 53, 63, 73: Control gates 44, 54, 64, 74: Floating gates 60, 70: P-type substrates 410, 510, 610, 710: Encoding period 411, 511: Gate encoding voltage 412, 512, 613, 713: Gate encoding time 413, 513, 614, 714: Drain encoding voltage 414, 514, 615, 715: Drain encoding time 420, 520 620, 720: erasing period 421, 521, 621, 721: gate erasing voltage 422, 522, 622, 722: gate erasing time 611, 711: rising edge voltage of the gate voltage 612, 712: gate Falling edge voltage of electrode voltage 623: Source erase voltage 624: Source erase time 902: Counter 02405twf2.doc / 006 Correction date 92.7.9 C: Capacitor D: Drain G: Gate NOR: Reverse OR gate S : Source T1: Transistor Example When performing a coding operation on a flash memory transistor, 'gate programming voltage is applied to its gate (Gate Programming Voltage (referred to as VGPI ^ g) and a Drain Programming Voltage (VDpn) g) applied to the drain to encode the flash memory. The gate-coded voltage VCpn3g applied to the gate is a voltage having a linear increase or a linear decrease. Figure 2a shows some voltage waveforms applicable to the present invention, but is not intended to limit the present invention. The drain-coded voltage VDpmg applied to the drain has a multi-duration characteristic. Please refer to Fig. 2b to illustrate the multi-period characteristics of the drain coding time, which shows two different square waveforms of the drain voltage. In the figure, tc20 and tc20 'are the corresponding gate encoding times. Divide tG20 m times to get tD21 ~ tD2m, which is the time for m drain coding, where tD2m and tc20 are equal, and both have the following 588365 02405twf2.doc / 006 correction date 92.7.9 relationship:
同理，將tG20’做m’次分割，以得tD21’〜tD2mf，爲m’ 個汲極編碼作用時間，其中tD2m’與tQ20’相等，兩者具有 下之關係： t 9n，_n tG20’ t D 2 η — n ，n=l 〜m’ m 在受同一閘極編碼電壓作用的數個快閃記憶體 電晶體，於閘極編碼電壓作用期間在不同的快閃記憶體電 晶體之汲極施與對應不同之汲極編碼電壓，而各汲極編碼 作用時間具有上文所述之關係。因此，每個記憶體得以在 一閘極編碼時間可儲存或寫入不同的數據，藉以達到多値 邏輯的目的。 請參考第3a圖，其所繪示的是在一閘極編碼電壓Vc 的作用下，所對應的幾個汲極編碼電壓VD1〜VD3。在VD1〜VD3 的上升邊緣對應到閘極電壓V。的分別是，乂⑺，VC3, 稱爲有效閘極編碼電壓（effective gate programming voltage)。上述各個有效閘極編碼電壓VG1 ，VG2 ，VG3， 又有一對應之臨限電壓値 VTHi ’ VTH2 ’ Vth3。 上述各電 壓具有下列關係： 11 588365 02405twf2.doc/006 修正0期92.7.9 VGi_ VTH1= VG2_ VTH2二 VG3_ VTH3=AV 其中AV之値與閘極編碼電壓Vc的斜率有關。 請參考第3c圖，其爲上述之實驗結果圖。其中橫軸 表示有效閘極電壓VCeff，縱軸代表相對應的臨限電壓VTH。 圖示中曲線I〜III分別表示輸入閘極之不同的斜坡型編碼 電壓。曲線I〜III的斜率分別對應至〇.28V/ms，0.57V/ms， 1.02V/ms 〇 請參考第3b圖，其所繪示爲不同斜率之閘極編碼電 壓與不同汲極編碼作用時間之汲極電壓關係。從圖中可看 出在不同的汲極編碼作用時間tD1，tD2對應到不同斜率的 閘極編碼電壓V。，但有相同之有效閘極編碼電壓VC1 = Vu。因此，在相同的有效閘極編碼電壓下，可明顯看出 閘極編碼電壓的斜率越小，其對應之汲極編碼作用時間tD 也就越長。 再者，由上述之有效閘極電壓vCeff與臨限電壓VTH之 差爲一定値，故知當汲極編碼電壓作用時間tD越長，其所 對應之臨限電壓的斜率也越小。因此，汲極編碼電壓作用 時間tD與其相對應之臨限電壓兩者之間的關係爲一線性關 係。 第3d圖繪示在不同的有效閘極電壓VCtiff之下，其相 12 588365 02405twf2.doc/006 修正日期 92.7.9 對應的臨限電壓VTH與汲極編碼電壓作用時間。的一實驗 結果圖。其中橫軸表示汲極編碼電壓作用時間tD而縱軸代 表臨限電壓vTH。圖示中曲線I〜III分別表示輸入閘極之不 同的斜率編碼電壓。其斜率對應至I〜III分別爲l.〇2V/ms， 0.51V/ms，0.32V/ms。由上述得知，於編碼期間，汲極編 碼電壓作用時間與其相應的臨限電壓係一線性關係。 第一實施例 請參照第4a圖，其爲一快閃記憶體的結構，包括一 半導體做爲N型基底40，兩個p型摻雜區分別做爲上述 快閃記憶體的源極41與汲極區42，以及一堆疊閘極，其 包括一控制閘43與浮置閘44。以上爲一習知之P型通道 快閃記憶體結構，其編碼機制爲通道熱電子注入（channel hot electron injection)，其抹除機制爲通道F-N穿遂效應 (Fowler-Nordheim tunneling effect ) 〇 將上述快閃記憶體之源極連接至一源極電壓Vs()，汲 極連接至一汲極電壓VD〇，控制聞極連接至一閘極電壓 v6Q，以及在基底連接至一基底電壓vB()。以上各電壓乃爲 一相對之基準値，並不特別限制，若各減去某固定電壓値， 其仍屬本實施例之範疇。在第一實施例中，上述之電壓可 爲3V〜6V。 13 588365 02405twf2.doc/006 修正日期92.7.9 請參考第4b圖，其所繪示爲在實施本發明之操作方 法時，其各該源極電壓VS()，汲極電壓Vd()，閘極電壓v〇〇 與基底電壓VB。之時脈圖。從該圖中可明顯區分在操作期 間分爲編碼時期（Program phase)410與抹除時期（erase phase)420。以下將以該圖來說明本發明之操作方法。 在編碼時期，在閘極施一聞極編碼電壓（Gate Programming Voltage)VGprGg411，該閘極編碼電壓 vG^g411 加在快閃記憶體的期間稱爲閘極編碼時間（Gate Programming Time)tGprQg412 ;對應在閘極編碼時間（Drain Programming Voltage) tGprQg412 的期間，在汲極施一汲極 編碼電壓VDpn)g413以編碼該快閃記憶體，該汲極編碼電 壓VDpnDg413加在汲極的期間稱爲汲極編碼作用時間（Drain Programming Time)tDprog414 〇 上述加在閘極之閘極編碼電壓411爲一斜坡電 壓(ramp)，而非習知之方形電壓。其電壓分布範圍爲3〜6V， 且其相應的閘極編碼時間爲〜50μδ。對應在該閘極 編碼時間所加在汲極之汲極編碼電壓脈衝爲3〜6V。 上述之閘極編碼時間tCpn3g與汲極編碼作用時間tDpr(Dg 具有以下的關係。本發明中，將聞極編碼時間做m次分割， 其中m爲正整數，各該對應至一閘極編碼電壓。其所對應 14 588365 02405twf2.doc/006 修正日期92.7·9In the same way, tG20 'is divided m times to obtain tD21' ~ tD2mf, which is the m ′ drain coding time, where tD2m 'is equal to tQ20', and the two have the following relationship: t 9n, _n tG20 ' t D 2 η — n, n = l ~ m 'm. Several flash memory transistors are affected by the same gate code voltage, and they are drawn from different flash memory transistors during the action of the gate code voltage. The pole application corresponds to different drain-coded voltages, and the action time of each drain-code has the relationship described above. Therefore, each memory can store or write different data at a gate encoding time, thereby achieving the purpose of multiple logic. Please refer to FIG. 3a, which depicts several drain-coded voltages VD1 to VD3 corresponding to a gate-coded voltage Vc. The rising edges of VD1 to VD3 correspond to the gate voltage V. The difference is that 乂 ⑺, VC3, is called effective gate programming voltage. Each of the effective gate-coded voltages VG1, VG2, and VG3 has a corresponding threshold voltage 値 VTHi ′ VTH2 ′ Vth3. The above voltages have the following relationship: 11 588365 02405twf2.doc / 006 Amendment 0 92.7.9 VGi_ VTH1 = VG2_ VTH2 two VG3_ VTH3 = AV where AV AV is related to the slope of the gate code voltage Vc. Please refer to Fig. 3c, which is a graph of the above experimental results. The horizontal axis represents the effective gate voltage VCeff, and the vertical axis represents the corresponding threshold voltage VTH. Curves I to III in the figure respectively indicate different ramp-type coding voltages of the input gates. The slopes of the curves I ~ III correspond to 0.28V / ms, 0.57V / ms, and 1.02V / ms, respectively. ○ Please refer to Figure 3b, which shows the gate-coded voltage and the drain-coded time of different slopes. The drain voltage relationship. It can be seen from the figure that the gate coding voltage V with different slopes corresponds to the different drain coding time tD1 and tD2. , But have the same effective gate code voltage VC1 = Vu. Therefore, under the same effective gate code voltage, it can be clearly seen that the smaller the slope of the gate code voltage, the longer the corresponding drain code time tD. Furthermore, since the difference between the effective gate voltage vCeff and the threshold voltage VTH is constant, it is known that as the drain coded voltage application time tD is longer, the corresponding threshold voltage slope is smaller. Therefore, the relationship between the drain-coded voltage application time tD and its corresponding threshold voltage is a linear relationship. Fig. 3d shows the corresponding threshold voltage VTH and drain-coded voltage action time under different effective gate voltages Vctiff 12 588365 02405twf2.doc / 006 Modified date 92.7.9. An experimental result graph. The horizontal axis represents the time tD of the drain-coded voltage and the vertical axis represents the threshold voltage vTH. The curves I ~ III in the figure respectively show the different slope-encoded voltages of the input gates. Its slopes correspond to I ~ III of 1.02V / ms, 0.51V / ms, and 0.32V / ms, respectively. It is known from the above that during the coding period, the drain coding time has a linear relationship with its corresponding threshold voltage. For the first embodiment, please refer to FIG. 4a, which shows the structure of a flash memory, including a semiconductor as the N-type substrate 40, and two p-type doped regions as the source 41 and the flash memory, respectively. The drain region 42 and a stacked gate include a control gate 43 and a floating gate 44. The above is a conventional P-type channel flash memory structure. Its encoding mechanism is channel hot electron injection, and its erasure mechanism is the channel FN tunneling effect (Fowler-Nordheim tunneling effect). The source of the flash memory is connected to a source voltage Vs (), the drain is connected to a drain voltage VD0, the control electrode is connected to a gate voltage v6Q, and the substrate is connected to a substrate voltage vB (). Each of the above voltages is a relative reference 値, and is not particularly limited. If a fixed voltage 减去 is subtracted from each, it still belongs to the scope of this embodiment. In the first embodiment, the above voltage may be 3V to 6V. 13 588365 02405twf2.doc / 006 Revised date 92.7.9 Please refer to Figure 4b, which shows the source voltage VS (), the drain voltage Vd (), the gate voltage when implementing the operation method of the present invention. The pole voltage v00 and the base voltage VB. Clock diagram. From this figure, it can be clearly distinguished that the operation period is divided into a programming phase 410 and an erasing phase 420. The operation method of the present invention will be described below with this figure. During the coding period, a gate programming voltage (VGprGg411) is applied to the gate, and the period during which the gate coding voltage vG ^ g411 is added to the flash memory is called a gate programming time (Gate Programming Time) tGprQg412; corresponding During the gate programming voltage (tGprQg412), a drain encoding voltage (VDpn) g413 is applied to the drain to encode the flash memory. The period during which the drain encoding voltage VDpnDg413 is applied to the drain is called the drain. Coding time (Drain Programming Time) tDprog414 〇 The gate coding voltage 411 added to the gate is a ramp voltage instead of the conventional square voltage. Its voltage distribution range is 3 ~ 6V, and its corresponding gate coding time is ~ 50μδ. The drain-encoded voltage pulse corresponding to the drain applied at the gate encoding time is 3 to 6V. The above gate coding time tCpn3g and the drain coding time tDpr (Dg have the following relationship. In the present invention, the smell coding time is divided m times, where m is a positive integer, each corresponding to a gate coding voltage Corresponding to 14 588365 02405twf2.doc / 006 Date of amendment 92.7 · 9
Dprog ηDprog η
Gprog 的汲極編碼作用時間tDpn)g可爲Gprog's drain coding time tDpn) g can be
Dprog ηDprog η
Gprog tGprog相等。藉此’ 其中n爲整數’其値爲l〜m，最大値跑 本發明可在一個閘極編碼時間內，^ _有多重即汲極編碼電 藉此，本發明可改 壓輸入汲極，以達到多値邏輯的自的 善習知的缺點。 在抹除時期，在閘極施予一_極抹 Voltage)VGers 421 其値可爲 18〜20V， 除電壓（Gate Erase 該閘極抹除電壓VCers 加在快閃記憶體的期間稱爲閘極p 〜坏除時間（Gate Erase 422，其値可爲 10〜l〇〇ms ’對應在該閘極抹除時 間期間，在汲極不施予汲極電_， 用以進行抹除動作。 其操作方式與習知相似。 請參考第4c圖，其爲第一寶偷你 貝力也例之一特例。在快閃 記憶體之源極電壓VS()，汲極電壓v & D〇 ’閘極電壓VG。以及 基底電壓VBG分別各爲6 V。在編碼期間加在蘭極之鬧極編 碼電壓VGpr(3g爲6V，對應的閘極編碼時間tCf_g爲5〇μ3。 15 588365 02405twf2.doc/006 修正日期 92.7.9 若將閘極編碼時間tCpn)g分割16等份，對應於於該閘極編 碼時間所施加在汲極之汲極編碼電壓爲vDF_g= 6V，其相 應的複數個汲極編碼作用時間爲 , 50 tDprog « = n 其中η爲整數，n=l〜16。其輸出之臨限電壓VTH在編碼期 間之分佈爲-1〜-5V，其爲一線性關係，並可達到多値邏輯 的目的。於抹除期間，在閘極施加一抹除電壓乂^,爲-14¥， 對應的閘極抹除時間t(^s爲10ms ;此時汲極不加電壓， 用以抹除該快閃記憶體。 第二實施例 請參照第5a圖，其爲一快閃記憶體的結構，具有一 半導體做爲N型基底50，兩個p型摻雜區分別做爲快閃 記憶體的源極51與汲極區52，以及一堆疊閘極，其包括 一控制閘53與浮置閘54。以上爲一習知之P型通道快閃 記憶體結構，其編碼機制爲價帶-對-導帶熱電子注入 (band-to-band tunneling induced hot electron injection) 9 而 其抹除機制爲通道F-N穿遂效應。 將上述之快閃記憶體的源極連接至一源極電壓VS0, 汲極連接至一汲極電壓VD()，控制閘極連接至一閘極電壓 VGQ，以及在其基底連接至一基底電壓VBG。以上各電壓乃 16 588365 02405twf2.doc/006 修正Θ期92.7.9 爲一相對之基準値，並不特別限制，若各減去某固定電壓 値，其仍屬本實施例之範疇。在第二實施例中，上述之電 壓可爲3V〜6V。 請參考第5b圖，其所繪示爲在實施本發明之操作法時， 其源極電壓Vs。，汲極電壓VD。，閘極電壓V⑽與基底電壓 VB。之時脈圖。從該圖中可明顯區分在操作期間分爲編碼 時期510與抹除時期520，以下將以該圖來說明本發明之 操作方法。 在編碼時期，在聞極施一閘極編碼電壓VCpr(Dg511，聞 極編碼電壓VCprc)g511加在快閃記憶體的期間稱爲閘極編 碼時間tCpnDg512;對應在該閘極編碼時間tCpn3g512的期間， 在汲極施一汲極編碼電壓VDpn)g513以編碼該快閃記憶體， 該汲極編碼電壓VDpn)g施在汲極的期間稱爲汲極編碼作用 時間 tDp^g514。 上述加在閘極之閘極編碼電壓VCpn)g511爲一斜坡電 壓（ramp)，而非習知之方形電壓。其電壓値可爲 V〇Pn3g=3〜8V，且其相應的閘極編碼時間爲〜25ps。 對應在該閘極編碼時間所加在汲極之汲極編碼電壓脈衝爲 VDprog=3〜8V。 上述之閘極編碼時間tCpn3g512與汲極編碼作用時間 17 588365 修正日期92.7.9 〇2405twf2.doc/006 tDpug514具有以下的關係。本發明中，將閘極編碼時間做 m次分割，其中m爲整數，各該對應至一閘極編碼電壓。 其所對應的汲極編碼作用時間tDpn)g可爲 t η - n G^g 其中n爲整數，其値爲1〜m，最大値與tap_相等。藉此， 本發明可在一個閘極編碼時間內，擁有多重即汲極編碼電 壓輸入汲極，以達到多値邏輯的目的。藉此，本發明可改 善習知的缺點。 在抹除時期，在閘極施予一閘極抹除電壓Vc_521其 値可爲18〜20V，閘極抹除電壓Vc_521加在快閃記憶體 的期間稱爲閘極抹除時間tc_522其値可爲10〜100ms ;對 應在該閘極抹除時間期間，在汲極不加汲極電壓，用 以抹除該快閃記憶體。其操作方式與習知相似。 第三實施例 請參照第6a圖，其爲一快閃記憶體的結構，具有一 半導體做爲P型基底60，有兩個n型摻雜區分別做爲快閃 記憶體的源極61與汲極區62，以及一堆疊閘極，包括一 控制閘63與浮置閘64。以上爲一習知之Ν型通道快閃記 憶體結構，其編碼機制爲通道熱電子注入（channel hot 18 588365 02405twf2.doc/006 修正日期92.7.9 electron injection)，而其抹除機制爲源極邊通道F-N穿遂 效應。 將上述快閃記憶體的該源極連接至一源極電壓V%， 該汲極連接至一汲極電壓VDQ，該閘極連接至一閘極電壓 VCQ，以及在該基底連接至一基底電壓VB()。以上各電壓乃 爲一相對之基準値，並不特別限制，若各減去某固定電壓 値，其仍屬本實施例之範疇。在第三實施例中，該些電壓 可爲0V。 請參考第6b圖，其所繪示爲在實施本發明之操作方 法時，其源極電壓Vs()，汲極電壓VD()，閘極電壓VC()與基 底電壓VB()之時脈圖。從該圖中可明顯區分在操作期間分 爲編碼時期610與抹除時期620。以下將以該圖來說明本 發明之操作方法。 在編碼時期，在控制閘極施一閘極編碼電壓VCpmg， 閘極編碼電壓Vepn)g加在快閃記憶體的期間稱爲閘極編碼 時間tCpnDg613 ;對應在閘極編碼時間的期間，在 汲極施一汲極編碼電壓VDpnDg614以進行編碼動作，該汲 極編碼電壓VDpn3g614加在汲極的期間稱爲汲極編碼作用 時間 tD_g 615。 在第三實施例中，上述加在閘極之閘極編碼電壓VCpnig 19 588365 02405twf2. doc/006 修正日期92.7.9 爲一梯形斜坡電壓（Trapezium ramp)，而非習知之方形電 壓。在閘極編碼電壓之上升邊緣其電壓爲611，其 電壓値可爲VGpr()gl 611=4〜5V，且下降邊緣的電壓爲 VCpn)g2612，其電壓値可爲 ^Gprog2 612=7〜10V ;且其相應的 閘極編碼時間爲tGi_g=l〜10μδ。對應在該閘極編碼時間所 加在汲極之汲極編碼電壓爲VDpn)g=3〜6V。 上述之閘極編碼時間tCpn)g613與汲極編碼作用時間 tDpr。/〗5具有以下的關係。本發明中，將閘極編碼時間做 m次分割，其中m爲正整數，各該對應至一閘極編碼電壓。 其所對應的汲極編碼作用時間tDl_g可爲 tDprog = « m 其中n爲整數，其値爲1〜m，最大値與tGpug相等。藉此， 本發明可在一個閘極編碼時間內，擁有多重即汲極編碼電 壓輸入汲極，以達到多値邏輯的目的。藉此，本發明可改 善習知的缺點。 在抹除時期，在閘極施予一閘極抹除電壓V&U621， 其値可爲-10〜-15V，該閘極抹除電壓Vc_621加在快閃記 憶體的期間稱爲閘極抹除時間te_622，其値可爲 10〜100ms ;對應在該閘極抹除時間tc_期間，在源極施予 一源極抹除電壓Vs_623其値可爲3〜6V，其對應的時間 20 588365 02405twf2.doc/006 修正日期 92.7.9 稱爲源極抹除時間ts_624其値可爲10〜100ms，與閘極抹 除時間一致，用以抹除該快閃記憶體。 在第三實施例中，斜坡電壓不是從基準點開始是因爲 在VG<VGfm)g時並不編碼該快閃記憶體。 在第三實施例中，該汲極編碼電壓不一定要與該閘極 編碼電壓同步加之於汲極上，只要在該閘極編碼時間內施 於汲極上，即可編碼該快閃記憶體。 在第三實施例中，其抹除期間之抹除機制除了使用源 極邊F-N穿遂效應將電子從浮動閘拉出以達抹除功能外， 尙可利用通道F-N穿遂效應將電子從浮置閘極移出至通道 來達成。 第四實施例 請參照第7a圖，其爲一快閃記憶體的結構，具有一 半導體做爲P型基底70，有兩個η型摻雜區分別做爲該快 閃記憶體的源極71與汲極區72，以及一堆疊閘極，包括 一控制閘73與一浮置閘74。以上爲一習知之Ν型通道快 閃記憶體結構，其編碼機制爲汲極邊F-N穿遂效應，而其 抹除機制爲通道F-N穿遂效應。 將上述快閃記憶體之源極連接至一源極電壓VSQ，汲 極連接至一汲極電壓VD()，控制閘極連接至一閘極電壓 21 588365 修正0期92.7.9 02405twf2.doc/006 VCQ，以及在基底連接至一基底電壓VBQ。以上各電壓乃爲 一相對之基準値，並不特別限制’若各減去某固定電壓値， 其仍屬本實施例之範疇。在第四實施例中，上述之電壓可 爲0V 〇 請參考第7b圖，其所繪示爲在實施本發明之操作方 法時，其源極電壓VS()，汲極電壓VD()，閘極電壓V⑽與基 底電壓VBQ之時脈圖。從該圖中可明顯區分在操作期間分 爲編碼時期710與抹除時期720。以下將以該圖來說明 本發明之操作方法。 在編碼時期，在控制閘極施一閘極編碼電壓， 該閘極編碼電壓VCi_g加在快閃記憶體的期間稱爲閘極編 碼時間tCfm)g713;對應在該閘極編碼時間tCf_g713的期間， 在汲極施一汲極編碼電壓VD_g7l4得以編碼該快閃記憶 體，上述之汲極編碼電壓VD_g加在汲極的期間稱爲汲極 編碼作用時間tDfU()g715。 在第四實施例中，上述加在控制閘極之閘極編碼電壓 Vc_g爲一梯形斜坡電壓，而非習知之方形電壓，藉此得 一線性的臨限電壓（VTH)關係。在上述之閘極編碼電壓之上 升邊緣其電壓爲VGpnDgl 711，其電壓値可爲vGprc)gi 711= -7〜_9V，且下降邊緣的電壓爲Vc_g2 712，其電壓値可爲 22 588365 02405twf2.doc/006 修正B期92.7.9 VGprog2 712=-10〜-14V ;且其相應的閘極編碼時間爲 tCf^g=〇.1〜l〇ms。對應該閘極編碼時間加在汲極之汲極編 碼電壓爲VDpn3g=4〜6V。 上述之閘極編碼時間tCpn3g713與汲極編碼作用時間 tD_g715具有以下的關係。本發明中，將閘極編碼時間做 m次分割，其中m爲正整數，各該對應至一閘極編碼電壓。 其所對應的編碼時間tDpn)g可爲 tGprog=n*tGprog/m tDprog - η· m 其中n爲整數，其値爲1〜m，最大値與tCp_相等。 藉此，本發明可在一個閘極編碼時間內，擁有多重即汲極 編碼電壓輸入汲極，以達到多値邏輯的目的。藉此，本發 明可改善習知的缺點。 在抹除時期，在閘極施一閘極抹除電壓Vc_721，其 値可爲18〜20V，該閘極抹除電壓Vc_加在快閃記憶體的 期間稱爲閘極抹除時間tc_722，其値可爲10〜100ms ;對 應在該閘極抹除時間期間，在源極與汲極均不加電 壓，藉由通道F-N穿遂效應得以抹除該快閃記憶體。 23 588365 02405twf2.doc/006 修正日期92.7·9 請參考第7c圖，其繪示於第四實施例中，在編碼期 間其臨限電壓與汲極編碼作用時間之關係圖，以及在抹除 期間其臨限電壓與閘極抹除時間之關係圖。很明顯可看出 其臨限電壓與汲極編碼作用時間爲一線性關係，可改進習 知之缺點。 此外，本發明實施例之在同一時間中，以控制汲極電 壓之施加時間來使閘極電壓呈現線性斜坡形式，然而汲極 與閘極間之電壓關係爲線性部分，請參考第8A與8B圖 之實際電路圖形與波形圖說明。第8A圖中以一觸發信號 (Trigger)來啓動，然後同時分別送入到兩個不同線路的 GVG(Gate Voltage Generator)與 DVG(Drain Voltage Generator)中，其結構在下面第9圖與第l〇圖將做進一步 解說。第8B圖中，可看出在電晶體T1的汲極D與閘極 G上，所產生波形汲極與閘極間之電壓關係爲線性關係。 而第9圖之GVG結構與產生波形及第10之DVG結 構與產生波形爲：首先在第9圖中的GVG結構中，以計 數器（Counte〇902分別由觸發信號（Trigger)、重設信號 (Reset)以及時脈信號（CLK)來控制，然後透過複數條線路 連接到短路電晶體之閘極，其中短路電晶體如圖所示以源 極連接汲極方式依序連接，其上下兩端則分別連接到一高 電壓Vpp與一接地電壓，同時在每一個短路電晶體之間連 接一電阻以行程一電阻分割結構，最後再最下面的一個電 24 588365 02405twf2.doc/006 if IE 臼期 92.7.9 阻上產生一電壓輸出Vout，並以一電容C連接，就可以產 生如右圖的波形輸入到第8A圖中的電晶體T1之閘極G， 而此種電路亦常用於數位類比的線路中。接著在第1 〇圖 中計數器（c〇unter)902分別由觸發信號（Trigger)、預設信 號（Preset)、時脈丨目號（CLK)以及向下|十數f目號Count) 來控制，然後以複數條輸出線連接到一控制閘NOR來輸 出而產生右邊的波形，我們可以看出經由觸發信號（Tngger) 產生波形變化（由高到低），其DVG之tDprQg由計數器902 控制，而時間則由預設信號將記數輸入，在受到觸發信號 之後開始向下計數，直到計數器902之輸出線輸出爲全部 爲〇爲止，然後才由NOR輸出爲1，因此時間可經經由計 數器902來達到準確控制。 綜上所述，雖然本發明已以四個較佳實施例揭露如 上，然其並非用以限定本發明，任何熟習此技藝者’在不 脫離本發明之精神和範圍內，當可作各種之更動與潤飾’ 因此本發明之保護範圍當視後附之申請專利範圍所界定者 爲準。 25Gprog tGprog is equal. Hereby, 'where n is an integer', where 値 is l ~ m, the maximum running time of the present invention is that in one gate coding time, there are multiple, ie, drain coding codes. With this, the present invention can change the input drain, In order to achieve the shortcomings of logical self-knowledge. In the erasing period, the gates are given a voltage of VGers 421, which can be 18 ~ 20V, and the gate erasure voltage (VCers) is added to the flash memory during the period called the gate p ~ Erase time (Gate Erase 422, which can be 10 ~ 100ms' corresponding to the gate erasure time, the drain electrode is not applied to the drain electrode, for erasing action. The operation method is similar to the conventional one. Please refer to Figure 4c, which is a special case of the first treasure stealing your Pali. In the flash memory source voltage VS (), the drain voltage v & D0 'gate The pole voltage VG. And the base voltage VBG are each 6 V. The encoding voltage VGpr (3g is 6V) is applied to the blue pole during the encoding period, and the corresponding gate encoding time tCf_g is 50 μ3. 15 588365 02405twf2.doc / 006 Correction date 92.7.9 If the gate encoding time tCpn) g is divided into 16 equal parts, the corresponding drain encoding voltage applied to the drain is vDF_g = 6V, and its corresponding plural drains The coding action time is 50 tDprog «= n where η is an integer and n = l ~ 16. The threshold voltage VTH of its output is between The distribution during the code period is -1 to -5V, which is a linear relationship and can achieve the purpose of multiple logic. During the erasing period, an erase voltage 乂 ^ is applied to the gate, which is -14 ¥, corresponding to the gate. The erasing time t (^ s is 10ms; at this time, no voltage is applied to the drain electrode to erase the flash memory. For a second embodiment, please refer to FIG. 5a, which shows the structure of a flash memory. The semiconductor serves as the N-type substrate 50, the two p-type doped regions serve as the source 51 and the drain regions 52 of the flash memory, and a stacked gate, which includes a control gate 53 and a floating gate 54. The above is a conventional P-channel flash memory structure. The encoding mechanism is valence band-to-band tunneling induced hot electron injection. 9 The erasure mechanism is channel FN wear. The source of the flash memory is connected to a source voltage VS0, the drain is connected to a drain voltage VD (), the control gate is connected to a gate voltage VGQ, and at its base is connected to A base voltage VBG. The above voltages are 16 588365 02405twf2.doc / 006 and the correction Θ period 92.7.9 is a relative The reference 値 is not particularly limited. If a fixed voltage 値 is subtracted from each, it still belongs to the scope of this embodiment. In the second embodiment, the above voltage may be 3V ~ 6V. Please refer to FIG. 5b, where It is shown as the source voltage Vs when implementing the operation method of the present invention. , Drain voltage VD. , The gate voltage V⑽ and the base voltage VB. Clock diagram. It can be clearly distinguished from the figure that the operation period is divided into a coding period 510 and an erasing period 520, and the operation method of the present invention will be described below with this figure. During the encoding period, the gate encoding voltage VCpr (Dg511, VCprc) g511 is applied to the flash memory during the encoding period, which is called the gate encoding time tCpnDg512; corresponding to the gate encoding time tCpn3g512 A drain encoding voltage VDpn) g513 is applied to the drain to encode the flash memory, and a period during which the drain encoding voltage VDpn) g is applied to the drain is referred to as a drain encoding time tDp ^ g514. The gate-encoded voltage VCpn) g511 applied to the gate is a ramp voltage instead of the conventional square voltage. Its voltage 値 can be V0Pn3g = 3 ~ 8V, and its corresponding gate coding time is ~ 25ps. The drain-encoded voltage pulse corresponding to the drain applied at the gate encoding time is VDprog = 3 ~ 8V. The above gate code time tCpn3g512 and drain code time 17 588365 correction date 92.7.9 〇 2405twf2.doc / 006 tDpug514 has the following relationship. In the present invention, the gate coding time is divided into m times, where m is an integer, each corresponding to a gate coding voltage. The corresponding drain coding time tDpn) g can be t η-n G ^ g where n is an integer, and 値 is 1 to m, and the maximum 値 is equal to tap_. In this way, the present invention can have multiple, ie, drain-coded voltage input drains within one gate coding time, to achieve the purpose of multi-block logic. By this, the present invention can improve the known disadvantages. During the erasing period, a gate erasing voltage Vc_521 is applied to the gate, which can be 18-20V. The period when the gate erasing voltage Vc_521 is added to the flash memory is called a gate erasing time tc_522, which is 10 ~ 100ms; corresponding to that during the gate erase time, no drain voltage is applied to the drain to erase the flash memory. Its operation is similar to the conventional one. For a third embodiment, please refer to FIG. 6a, which shows the structure of a flash memory. It has a semiconductor as the P-type substrate 60, and two n-type doped regions as the source 61 and the flash memory. The drain region 62 and a stacked gate include a control gate 63 and a floating gate 64. The above is a conventional N-type channel flash memory structure. Its coding mechanism is channel hot electron injection (channel hot 18 588365 02405twf2.doc / 006 revision date 92.7.9 electron injection), and its erasure mechanism is source side Channel FN tunneling effect. The source of the flash memory is connected to a source voltage V%, the drain is connected to a drain voltage VDQ, the gate is connected to a gate voltage VCQ, and the substrate is connected to a substrate voltage VB (). Each of the above voltages is a relative reference 値, and is not particularly limited. If a fixed voltage 减去 is subtracted from each, it still belongs to the scope of this embodiment. In the third embodiment, these voltages may be 0V. Please refer to FIG. 6b, which shows the clocks of the source voltage Vs (), the drain voltage VD (), the gate voltage VC () and the base voltage VB () when implementing the operation method of the present invention Illustration. It can be clearly distinguished from this figure that the operation period is divided into a coding period 610 and an erasing period 620. The operation method of the present invention will be described below with the figure. During the encoding period, a gate encoding voltage VCpmg is applied to the control gate, and the gate encoding voltage Vepn) g is added to the flash memory during a period called gate encoding time tCpnDg613; corresponding to the gate encoding time, A drain encoding voltage VDpnDg614 is applied to perform the encoding operation. A period during which the drain encoding voltage VDpn3g614 is applied to the drain is referred to as a drain encoding time tD_g 615. In the third embodiment, the gate-encoded voltage VCpnig 19 588365 02405twf2.doc / 006 added to the gate is a trapezium ramp instead of the conventional square voltage. At the rising edge of the gate code voltage, its voltage is 611, its voltage 値 may be VGpr () gl 611 = 4 ~ 5V, and its falling edge voltage is VCpn) g2612, its voltage 値 may be ^ Gprog2 612 = 7 ~ 10V ; And its corresponding gate coding time is tGi_g = 1 ~ 10μδ. The voltage corresponding to the drain coding voltage applied to the drain during the gate coding time is VDpn) g = 3 ~ 6V. The gate coding time tCpn) g613 and the drain coding time tDpr described above. / 〖5 has the following relationship. In the present invention, the gate coding time is divided m times, where m is a positive integer, and each should correspond to a gate coding voltage. The corresponding drain coding time tDl_g may be tDprog = «m where n is an integer, and 値 is 1 to m, and the maximum 値 is equal to tGpug. In this way, the present invention can have multiple, ie, drain-coded voltage input drains within one gate coding time, to achieve the purpose of multi-block logic. By this, the present invention can improve the known disadvantages. During the erasing period, a gate erasing voltage V & U621 is applied to the gate, which can be -10 ~ -15V. The period when the gate erasing voltage Vc_621 is applied to the flash memory is called a gate erasing. The division time te_622 can be 10 ~ 100ms; corresponding to the gate erasure time tc_, a source erasure voltage Vs_623 is applied to the source, which can be 3 ~ 6V, and its corresponding time is 20 588365 02405twf2.doc / 006 The revision date 92.7.9 is called the source erase time ts_624, which can be 10 ~ 100ms, which is consistent with the gate erase time, and is used to erase the flash memory. In the third embodiment, the ramp voltage does not start from the reference point because the flash memory is not encoded at VG < VGfm) g. In the third embodiment, the drain encoding voltage does not have to be added to the drain in synchronization with the gate encoding voltage. The flash memory can be encoded as long as it is applied to the drain during the gate encoding time. In the third embodiment, in addition to the erasing mechanism during the erasing process, in addition to using the source side FN tunneling effect to pull the electrons out of the floating gate to achieve the erasing function, the channel FN tunneling effect can be used to pull the electrons from the floating gate. The gate is moved out to the channel to achieve it. For a fourth embodiment, please refer to FIG. 7a, which shows the structure of a flash memory. It has a semiconductor as the P-type substrate 70, and two n-type doped regions as the source 71 of the flash memory. The drain region 72 and a stacked gate include a control gate 73 and a floating gate 74. The above is a conventional N-channel flash memory structure. The encoding mechanism is the F-N tunneling effect on the drain side, and the erasing mechanism is the channel F-N tunneling effect. Connect the source of the flash memory to a source voltage VSQ, the drain to a drain voltage VD (), and the control gate to a gate voltage 21 588365 Amendment 0 92.7.9 02405twf2.doc / 006 VCQ, and the substrate is connected to a substrate voltage VBQ. Each of the above voltages is a relative reference 値, and is not particularly limited. ′ If a fixed voltage 减去 is subtracted from each, it still belongs to the scope of this embodiment. In the fourth embodiment, the above voltage may be 0V. Please refer to FIG. 7b, which is shown as the source voltage VS (), the drain voltage VD (), and the gate when implementing the operation method of the present invention. Clock diagram of the pole voltage V⑽ and the base voltage VBQ. It can be clearly distinguished from this figure that the operation period is divided into a coding period 710 and an erasing period 720. The method of operation of the present invention will be described below with this figure. During the encoding period, a gate encoding voltage is applied to the control gate. The period during which the gate encoding voltage VCI_g is added to the flash memory is called gate encoding time tCfm) g713; corresponding to the period of the gate encoding time tCf_g713, A drain encoding voltage VD_g7l4 is applied to the drain to encode the flash memory. The period during which the above-mentioned drain encoding voltage VD_g is added to the drain is referred to as a drain encoding time tDfU () g715. In the fourth embodiment, the gate-coded voltage Vc_g applied to the control gate is a trapezoidal ramp voltage instead of the conventional square voltage, thereby obtaining a linear threshold voltage (VTH) relationship. On the rising edge of the above gate-coded voltage, its voltage is VGpnDgl 711, its voltage 値 may be vGprc) gi 711 = -7 ~ _9V, and its falling edge voltage is Vc_g2 712, its voltage 値 may be 22 588365 02405twf2.doc / 006 Revised Phase B 92.7.9 VGprog2 712 = -10 ~ -14V; and its corresponding gate coding time is tCf ^ g = 0.1 ~ 10ms. Corresponding to the gate coding time, the drain coding voltage added to the drain is VDpn3g = 4 ~ 6V. The gate coding time tCpn3g713 and the drain coding time tD_g715 have the following relationship. In the present invention, the gate coding time is divided m times, where m is a positive integer, and each should correspond to a gate coding voltage. The corresponding encoding time tDpn) g may be tGprog = n * tGprog / m tDprog-η · m where n is an integer, and 値 is 1 to m, and the maximum 値 is equal to tCp_. In this way, the present invention can have multiple, ie, drain, coded voltage input drains within one gate coding time to achieve the purpose of multi-channel logic. By this, the present invention can improve the conventional disadvantages. During the erasing period, a gate erasing voltage Vc_721 is applied to the gate, which can be 18-20V. The period during which the gate erasing voltage Vc_ is added to the flash memory is called gate erasing time tc_722, It can be 10 to 100 ms; corresponding to that during the gate erase time, no voltage is applied to the source and the drain, and the flash memory can be erased by the channel FN tunneling effect. 23 588365 02405twf2.doc / 006 Revision date 92.7 · 9 Please refer to Figure 7c, which is shown in the fourth embodiment, the relationship between the threshold voltage and the drain coding time in the coding period, and the erasing period The relationship between the threshold voltage and the gate erase time. It is obvious that the threshold voltage and the drain coding time have a linear relationship, which can improve the conventional disadvantages. In addition, in the embodiment of the present invention, at the same time, the gate voltage is controlled to have a linear ramp shape by controlling the application time of the drain voltage. However, the voltage relationship between the drain and the gate is a linear part. Please refer to Sections 8A and 8B. The actual circuit diagram and waveform diagram of the figure are illustrated. Figure 8A is activated by a trigger signal and then sent to two different lines of GVG (Gate Voltage Generator) and DVG (Drain Voltage Generator) at the same time. The structure is shown in Figure 9 and Figure 1 below. 〇 The picture will be further explained. In Fig. 8B, it can be seen that on the drain D and the gate G of the transistor T1, the voltage relationship between the generated drain and the gate is linear. The GVG structure and generated waveform in FIG. 9 and the DVG structure and generated waveform in FIG. 10 are as follows: First, in the GVG structure in FIG. 9, a counter (Counte 902 is composed of a trigger signal (Trigger) and a reset signal ( Reset) and clock signal (CLK) to control, and then connected to the gate of the short-circuit transistor through a plurality of lines, where the short-circuit transistor is connected sequentially in the form of a source-connected drain, and its upper and lower ends are Connected to a high voltage Vpp and a ground voltage respectively, while connecting a resistor between each short-circuit transistor with a stroke-resistance division structure, and finally the bottom one 24 588365 02405twf2.doc / 006 if IE mortar period 92.7 .9 generate a voltage output Vout on the resistor and connect it with a capacitor C to generate the waveform as shown in the figure on the right and input it to the gate G of transistor T1 in Figure 8A. This circuit is also commonly used for digital analog In the circuit, the counter (cunter) 902 in Fig. 10 is composed of a trigger signal (Trigger), a preset signal (Preset), a clock number (CLK), and a downward number. ) To control and then plural An output line is connected to a control gate NOR to output and generate the right waveform. We can see that the trigger signal (Tngger) generates a waveform change (high to low). The tDprQg of its DVG is controlled by the counter 902, and the time is controlled by the counter 902. The preset signal will be counted. After receiving the trigger signal, it starts to count down until the output of the output line of the counter 902 is all 0, and then the output of the NOR is 1. Therefore, the time can be accurately controlled by the counter 902. . In summary, although the present invention has been disclosed as above with four preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various modifications without departing from the spirit and scope of the present invention. Changes and Retouches' Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application. 25