TW587321B - Structure of bonding pad region - Google Patents
Structure of bonding pad region Download PDFInfo
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- TW587321B TW587321B TW91134171A TW91134171A TW587321B TW 587321 B TW587321 B TW 587321B TW 91134171 A TW91134171 A TW 91134171A TW 91134171 A TW91134171 A TW 91134171A TW 587321 B TW587321 B TW 587321B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
587321 五、發明說明(1) 【發明所屬之技術領域】 本發明係有關於一種半導體積體電路(semiconductor integrated circuits ; ICs)之構造,且特別是有關於一 種能夠防止接合塾(bonding pad)剝離(peeling)之接合塾 區構造。 【先前技術】587321 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a structure of semiconductor integrated circuits (ICs), and in particular, to a structure capable of preventing peeling of a bonding pad. (Peeling) junction ridge structure. [Prior art]
當積體電路製造完成之後,形成於表面之頂部金屬層 係經界定成複數接合墊(bonding pad),而分別與形成於 底層金屬塾(metal pad)成電性連接後,經打線機 (bonder)以金屬線連接於接合墊與導架相對應之導腳間。 換言之,接合墊係作為内部電路與外接信號導腳間之介 面,而外接信號不外乎就是電源信號、接地信號、或輸入 /輸出信號等等。 以下配合第1及2圖說明習知之金屬墊構造。首先,請 參照第1圖,其繪示出習知金屬墊構造之剖面圖。其中, 標號108為一半導體基底,其上形成有若干半導體元件, 此處為簡化圖式,僅繪示出一平整基底。一第一圖案介電 層202形成於此基底1〇8上以作為金屬間介電声 (inter_metal dielectric ; IMD),例如是低介電材料After the fabrication of the integrated circuit is completed, the top metal layer formed on the surface is defined as a plurality of bonding pads, and is electrically connected to the metal pad formed on the bottom layer, respectively, and then passed through a bonder. ) Connected between the guide pad corresponding to the bonding pad and the guide frame by a metal wire. In other words, the bonding pad serves as an interface between the internal circuit and the external signal guide pins, and the external signal is nothing more than a power signal, a ground signal, or an input / output signal, and so on. The conventional metal pad structure is described below with reference to FIGS. 1 and 2. First, please refer to FIG. 1, which is a cross-sectional view showing a conventional metal pad structure. Wherein, reference numeral 108 is a semiconductor substrate on which a plurality of semiconductor elements are formed. Here, in order to simplify the diagram, only a flat substrate is illustrated. A first patterned dielectric layer 202 is formed on the substrate 108 as an inter-metal dielectric (IMD), such as a low dielectric material.
層’且-第-金屬塾單元201,外型為正方形或矩形,形 成於上述金屬間介電層2 02内,以作為連接半導體元件内 連線與外部導線之電性連接結構。之後,纟第一圖案介電 層202及第一金屬塾單元201上形成有一第二圖案介電層The layer 'and-th-metal rhenium unit 201 has a square or rectangular shape and is formed in the intermetallic dielectric layer 202 as an electrical connection structure for connecting the internal wiring of the semiconductor element and the external wire. After that, a second patterned dielectric layer is formed on the first patterned dielectric layer 202 and the first metal framed unit 201.
587321 發明說明(2) 204,而位於第一金屬墊單元201上方之介電層2〇4形成有 介層洞(via hole)2 04a,介層洞2〇4a内有銅金屬插塞 (plug) 2 04b,用以電性連接第一金屬墊單元2〇1。接"'著, 第二圖案介電層204上形成有一第三圖案介電層2〇6及第二 金屬堅單元2 05。此金屬墊單元205外型同樣為方形或矩 形,係用以透過插塞204b及第一金屬墊單元2〇1而與基底 108上的半導體元件作電性連接並作為連接外部電路之接 合墊(bonding pad)。最後,在第二金屬墊單元2〇5周邊上 方,形成有一鈍態(passivation)保護層208,以保護接墊 205在後續封裝(package)製程中不受到損害。上述保護層 208具有一開口 208a而露出上述金屬層2〇5表面以作為後^ 打線機之金屬線接合之部分。 然而’請參照第2圖,其繪示出根據第1圖之第一圖案 介電層202及第一金屬墊單元2 〇1之上視圖。如上所述,由 於第一圖案介電層202機械強度弱並且附著性 (bondability)不佳,因此在化學機械研磨(chemical mechanical polishing ;CMP)應力的作用下,容易在第一 金屬墊單元2 01的角落發生應力集中而介電層2〇2產生龜 裂’嚴重影響元件的電特性及產品之品質。再者,經過打 線機施加的機械應力及超音波振盪之雙重作用之後,第一 "電層202會發生龜裂及剝離的現象,如第2圖所示。更嚴 重者,整個頂部金屬層2 0 5及金屬層201會被打線機之金^ 線掀起而脫離(pee ling)介電層(未繪示)而形成陷坑 (crater),造成半導體裝置失效。587321 Description of the invention (2) 204, a via hole 2 04a is formed in the dielectric layer 204 located above the first metal pad unit 201, and a copper metal plug is provided in the via hole 204a 2 04b, for electrically connecting the first metal pad unit 201. As a result, a third patterned dielectric layer 206 and a second metal rigid cell 205 are formed on the second patterned dielectric layer 204. The shape of the metal pad unit 205 is also square or rectangular, and is used to electrically connect with the semiconductor element on the substrate 108 through the plug 204b and the first metal pad unit 201 and as a bonding pad for connecting external circuits ( bonding pad). Finally, a passivation protection layer 208 is formed above the periphery of the second metal pad unit 205 to protect the pad 205 from being damaged in the subsequent package process. The protective layer 208 has an opening 208a, and the surface of the metal layer 205 is exposed to serve as a part of the metal wire bonding of the post-wire machine. However, please refer to FIG. 2, which shows a top view of the first patterned dielectric layer 202 and the first metal pad unit 2 01 according to FIG. 1. As described above, since the first patterned dielectric layer 202 has weak mechanical strength and poor bondability, it is easy to apply the chemical mechanical polishing (CMP) stress on the first metal pad unit 2 01 Stress concentration occurs in the corners and cracks occur in the dielectric layer 202, which seriously affects the electrical characteristics of the device and the quality of the product. In addition, after the dual effects of mechanical stress and ultrasonic oscillation applied by the wire bonder, the first " electrical layer 202 may crack and peel, as shown in Fig. 2. More seriously, the entire top metal layer 205 and the metal layer 201 will be lifted up by the wire of the wire bonder and peel away from the dielectric layer (not shown) to form a crater, causing the semiconductor device to fail.
0503-8562TW(Nl) ; TSMC200M3i6 ; Pel icia.ptd % ' ---- 587321 五、發明說明(3) 之美國專利第 1月6日公告之美國專利第 一種可防止接合墊區剝落 整與周圍的接面積以增加 集度的增加且半導體元件 的結構在尺寸縮小的製作 題,本發明主要目的在於 可增加外部應力的釋放, 達到防止接合墊的剝離、 於西元2 00 1年1〇月23日公告 6,306,749B1號以及西元2〇〇1年1 6,313,541B1號中Lin等人皆揭露 的結構,主要皆係利用增加接合 其附著力,然而,隨著半導體積 隨之縮小的趨勢之下,這些複雜 上面臨極大的困難。 有鑑於此,為了解決上述問 提供一種接合墊區之結構,不僅 也可以確保接合塾區之黏著性, 陷坑之目的。 【發明内容】 本發明之目的在於提供一 合墊的剝離、陷坑。 本發明之特徵主要係利用 (s 1 〇 t),開口由上視圖觀之, 通’也可以整個開口包含於頂 態之開口皆同時存在,該開口 開口内部充滿介電層,可以增 黏著力’並加強整個接合塾區 (interlock capability)。 為獲致上述之目的,本發 構’主要包括·形成於上述半 種接合墊區之結構,防止接 在頂部金屬層中增設開口 可以與頂部金屬層外部相連 4金屬層内部,或是兩者型 係用以釋放外部應力,並且 加接合墊區與介電層之間的 對介電層的聯鎖能为 明提出一種接合塾區之会士 導體基底表面之一圖案化介 麵晒 0503-8562TWF(Nl) ; TSMC200M316 ; Felicia.ptd 第 五、發明說明(4) U電部金屬層以及設置於上述圖案 項邱令厲® 一述頂σ卩金屬層重疊之一接合墊。其中, ◎ρ金屬層設置於上述圖案化介電層内,使上述 7兩上述圖幸仆介鬥充 案化介電Γ二 接合塾之表面露出於上述圖 却Α ί據本發明,上述開口由上視圖觀之,可以與上述TS ^屬層外部相連通,也可以整個開口包含於上述頂部 形= 3 ’或是兩者型態之開口皆同時存在。上述開口的 匕括:矩形、三角形、不規則形狀、任意圖案或任奄 又予。士述開口大鱧設置於上述頂部金屬層之四個角落' 層,ί =述’本發明之接合塾區之結構更包括:一保護 ^^ 述接合墊之周圍上方之圖案化介電層表面, J t述金屬墊表面,以做為接合的部分;以及複數金 :層二:別設置於上述圖案化介電層内之頂部金屬層下 方,其中各金屬層之間以複數金屬插塞相連。 述,上述圖案介電層可由低介電材料構成。另 2二A金屬層之材質可包括銅(Cu)、鋁(A1)或銅鋁 d)alloy)。至於,上述接合墊之材質可包括鋁 述,上述頂部金屬層與上述接合塾可呈矩形。 下文上述目的、特徵和優點能更明顯易懂, :文特舉-較佳貫施例’並配合所附圖式,作詳細說明如 Γ · 瞧 第7頁0503-8562TW (Nl); TSMC200M3i6; Pel icia.ptd% '---- 587321 V. Description of the invention (3) The first U.S. patent issued on January 6th to prevent peeling and bonding of the bonding pad area The production area of the surrounding junction area is increased to increase the density and the structure of the semiconductor device is reduced in size. The main purpose of the present invention is to increase the release of external stress and prevent the peeling of the bonding pad. The structures disclosed by Lin et al. In No. 6,306,749B1 and No. 16,313,541B1 of 2001, announced on the 23rd, are mainly used to increase the adhesion of the joint. However, as the semiconductor volume shrinks, Under the trend, these complexities are facing great difficulties. In view of this, in order to solve the above problem, a structure of a bonding pad area is provided, which can not only ensure the adhesion of the bonding pad area, but also the purpose of pitting. SUMMARY OF THE INVENTION The object of the present invention is to provide a peeling and sinking of a pad. The feature of the present invention is mainly the use of (s 1 0t). The opening is viewed from the top view, and the opening can also be included in the top state. The opening is filled with a dielectric layer inside, which can increase the adhesion. 'And strengthen the entire interlock capability. In order to achieve the above purpose, the present structure 'mainly includes a structure formed in the above-mentioned half of the bonding pad area, preventing an additional opening in the top metal layer, which can be connected to the outside of the top metal layer, inside the metal layer, or both It is used to release the external stress, and the interlocking of the dielectric layer between the bonding pad area and the dielectric layer can provide a patterned interface for the surface of a non-conductor conductor that joins the ridge area. 0503-8562TWF (Nl); TSMC200M316; Felicia.ptd Fifth, description of the invention (4) A metal layer of the U electrical part and a bonding pad provided on the above pattern item Qiu Lingli® where the top σ 卩 metal layer overlaps. Among them, the ◎ ρ metal layer is disposed in the patterned dielectric layer, so that the surfaces of the above-mentioned two and the above-mentioned graphs are filled with the dielectric Γ two-junction 塾 exposed in the above-mentioned figure A. According to the present invention, the opening Viewed from the top view, it can communicate with the outside of the TS layer, or the entire opening can be included in the top shape = 3 'or both types of openings can exist at the same time. The daggers of the above openings: rectangular, triangular, irregular shapes, arbitrary patterns, or any other. Said openings are arranged at the four corners of the top metal layer, and the structure of the bonding region of the present invention further includes: a protection surface of the patterned dielectric layer above the bonding pad. J t describes the surface of the metal pad as the bonding part; and multiple gold: layer two: do not set under the top metal layer in the patterned dielectric layer above, where each metal layer is connected by a plurality of metal plugs . It is stated that the patterned dielectric layer may be made of a low dielectric material. The material of the two A metal layers may include copper (Cu), aluminum (A1), or copper and aluminum (d) alloy). In addition, the material of the bonding pad may include aluminum, and the top metal layer and the bonding pad may be rectangular. The above-mentioned purposes, features, and advantages can be more clearly understood below: Wen Teju-the preferred embodiment ’and the accompanying drawings, for a detailed description such as Γ · See page 7
587321587321
【實施方式】 以下利用第3圖 银口墊區之結>r再別w圓以及第4 第5圖與第6圖之頂部金屬層之上視圖,說;之 一較佳實施例。 个\明之 f先,請先參照第3圖,說明本發明之接合墊 構。該結構主要包括:形成於半導體基底1〇〇表面之一圖》 化介電層115、具有複數開口之一頂部金屬層140以及:: 於圖案化介電層115内且與頂部金屬層14〇重 一 1 150 。 设口! 圖中顯示一半導體基底100,半導體基底100表面可能 具有任何所需之半導體元件,例如:電晶體、二極體以及 任何習知之半導體元件,此處為求簡化圖示起見, 未繪示。 並且,複數圖案化介電層,例如:一第一圖案化介電 層111、一第二圖案化介電層112、一第三圖案化介電層 113、一第四圖案化介電層114與一第五圖案化介電層 115 ’依序堆疊於半導體基底1〇〇上。各圖案化介電層 111〜11 5的材質例如為氧化矽(s i 〇2 )、構矽玻璃(pSG )、硼 礎石夕玻璃(BPSG)或是其他低介電常數材料,如氟矽玻璃 (FSG)。 另外,複數金屬層,例如:第一金屬層丨3!、第二金屬 層132、第二金屬層133與第四金屬層134,分別設置於第 一至第四圖案化介電層13卜134内部。圖中繪示四層金屬 層1 3 1〜1 3 4 ’然而實際上金屬層的層數可配合電路設計而[Embodiment] The top view of the top metal layer of Fig. 3 and Fig. 4 and Fig. 6 is described below using a knot of the silver mouth pad region in Fig. 3, and a preferred embodiment. First, please refer to FIG. 3 to explain the bonding pad structure of the present invention. The structure mainly includes: a pattern formed on the surface of the semiconductor substrate 100; a dielectric layer 115; a top metal layer 140 having a plurality of openings; and: within the patterned dielectric layer 115 and the top metal layer 14. Weighing 1 150. Establish a mouth! The figure shows a semiconductor substrate 100. The surface of the semiconductor substrate 100 may have any desired semiconductor components, such as transistors, diodes, and any conventional semiconductor components. For simplicity, it is not shown here. In addition, the plurality of patterned dielectric layers are, for example, a first patterned dielectric layer 111, a second patterned dielectric layer 112, a third patterned dielectric layer 113, and a fourth patterned dielectric layer 114. A fifth patterned dielectric layer 115 ′ is sequentially stacked on the semiconductor substrate 100. The material of each of the patterned dielectric layers 111 to 115 is, for example, silicon oxide (SiO 2), silicate glass (pSG), borosilicate glass (BPSG), or other low dielectric constant materials, such as fluorosilicon glass ( FSG). In addition, a plurality of metal layers, for example, the first metal layer 3, the second metal layer 132, the second metal layer 133, and the fourth metal layer 134 are disposed on the first to fourth patterned dielectric layers 134 and 134, respectively. internal. The figure shows four metal layers 1 3 1 ~ 1 3 4 ’However, the number of metal layers can actually be matched with the circuit design.
0503-8562TW(Nl) : TSMC2001-1316 ; Felicia.ptd 第8頁 587321 五、發明說明(6) 調整,可依需求而定,並不在此加以設限。至於圖案化介 電層之層數則必須配合金屬層的數目,使每一金屬層接設 置於每一圖案化介電層内部。 另外,頂部金屬層1 4〇係指最頂層之金屬層,設置於 最頂層(第五)圖案化介電層丨丨5内部。本發明之特徵係頂 部金屬層1 40具有複數開口,並且開口内部必需充滿圖案 化介電層115。由於外部應力容易集中於角落,所以該些 開口大體設置於頂部金屬層1 4 〇的四個角落,可以有效消 除且釋放外部應力,而且開口内部充滿圖案化介電層 115,可使得整個接合墊區對圖案化介電層的附著力增 加,如此一來,便可有效防止接合墊區因受到打線接合引 發應力而導致剝落。由剖面圖中並無法觀察到頂部金屬層 1 40内部之開口,後續文中將以上視圖詳細說明頂部金屬 層1 4 0内部之開口。 各層金屬層13卜134與頂部金屬層14〇之材質可包括銅 (Cu)、紹(A1)或銅紹合金(Cu/A1 alloy)。並且,各金屬 層1 3卜134與頂部金屬層14〇之間皆設置複數金屬插塞丨〇, 以做為電性連接。金屬插塞1〇之材質例如為金屬鎢(w)。 另外’接合墊(bonding pad)15〇重疊於頂部金屬層之 表面,同樣設置於圖案化介電層115内部,並且其表面露 出至外部,用以後續藉由打線製作接腳,用以血外部電性 連接。接合塾150的材質例如為金屬鋁(A1)。、 最後,一保護層120,設置於接合墊15〇之周圍上方之 圖案化介電層115表面。並且,保護層12〇具有一接合開口0503-8562TW (Nl): TSMC2001-1316; Felicia.ptd Page 8 587321 V. Description of the invention (6) Adjustments can be made according to requirements, and no restrictions are set here. As for the number of the patterned dielectric layers, it is necessary to match the number of metal layers so that each metal layer is disposed inside each patterned dielectric layer. In addition, the top metal layer 140 refers to the topmost metal layer, which is disposed inside the topmost (fifth) patterned dielectric layer 5. The feature of the present invention is that the top metal layer 140 has a plurality of openings, and the inside of the openings must be filled with the patterned dielectric layer 115. Since external stresses are easily concentrated in the corners, the openings are generally disposed at the four corners of the top metal layer 14 0, which can effectively eliminate and release external stresses, and the openings are filled with a patterned dielectric layer 115, which can make the entire bonding pad The adhesion of the region to the patterned dielectric layer is increased. In this way, the bonding pad region can be effectively prevented from being peeled off due to the stress caused by wire bonding. The openings inside the top metal layer 1 40 cannot be observed from the cross-sectional view. The following views will explain the openings inside the top metal layer 1 40 in detail in the following text. The material of each of the metal layers 13 and 134 and the top metal layer 14 may include copper (Cu), Shao (A1), or Cu / A1 alloy. In addition, a plurality of metal plugs are provided between each of the metal layers 134 and 134 and the top metal layer 14o as an electrical connection. The material of the metal plug 10 is, for example, metal tungsten (w). In addition, a 'bonding pad' (15) overlaps the surface of the top metal layer, and is also provided inside the patterned dielectric layer 115, and its surface is exposed to the outside for the subsequent production of pins by wire bonding and the use of blood. Electrical connection. The material of the bonding pad 150 is, for example, metal aluminum (A1). Finally, a protective layer 120 is disposed on the surface of the patterned dielectric layer 115 above the periphery of the bonding pad 150. In addition, the protective layer 12 has a joint opening.
587321 五、發明說明(7) 區I,用以露出接合墊1 5 0表面,以方便接合墊1 5 0進行打 線。 各層金屬層131〜134、頂部金屬層140與接合墊15〇之 形狀通常為矩形,也可以依照需求製作成其他形狀,在此 並不加以設限。 本發明之特徵在於頂部金屬層1 50之開口2〇〇,請參見 第4A圖至第4F圖,開口200a可以整個包含於頂部金屬層 150内部,另外,請參見第5A圖至第5E圖,開口 20Ob也可 以與頂部金屬層1 5 0外部相連通,或是兩者型態之開口 200a、200b皆同時存在(如第6A圖至第6C圖所示)。開口 20 0a、200b的形狀可包括:弧形、直線、帶狀、鑛尺形、 鑽石形、長方形、多邊形(可由三邊至八邊,或甚至更多 邊,例如:矩形、三角形、五角形、六角形、八角形… 等)、不規則形狀、任意圖案或任意文字(例如:C、e、Η、 I、J、Κ、L、Μ、Ν、0、U、V、W、X…等),在此並不加以 設限,且大體設置於頂部金屬層丨50之四個角落。· 發明功效 根據本發明’利用在頂部金屬層中設計開口,用以釋 放外部應力,而且開口内部充滿圖案化介電層,可使得整 個接合墊區對圖案化介電層的附著力性(adhesi〇n)增加, 加強整個接合塾區結構之聯鎖能力(interl〇ck capabi 1 1 ty),避免在進行打線接合時,打線機施加的機 械應力及超音波振盪而造成金屬墊剝離、陷坑的問題發587321 V. Description of the invention (7) Zone I is used to expose the surface of the bonding pad 150 to facilitate the bonding of the bonding pad 150. The shapes of each of the metal layers 131 to 134, the top metal layer 140, and the bonding pad 150 are generally rectangular, and other shapes can be made according to requirements, which are not limited here. The present invention is characterized in that the opening 200 of the top metal layer 150 is shown in FIGS. 4A to 4F. The opening 200a may be entirely contained inside the top metal layer 150. In addition, please refer to FIGS. 5A to 5E. The opening 20Ob can also communicate with the top metal layer 150 externally, or both types of openings 200a, 200b exist at the same time (as shown in FIGS. 6A to 6C). The shapes of the openings 20 0a, 200b may include: arc, straight, band-shaped, ruler-shaped, diamond-shaped, rectangular, polygonal (from three sides to eight sides, or even more sides, for example: rectangle, triangle, pentagon, Hexagon, octagon, etc.), irregular shapes, arbitrary patterns or arbitrary text (for example: C, e, Η, I, J, KK, L, M, N, 0, U, V, W, X, etc. ), Which is not limited here, and is generally arranged at the four corners of the top metal layer 50. Effect of the invention According to the present invention, 'the opening is designed in the top metal layer to release external stress, and the opening is filled with a patterned dielectric layer, which can make the entire bonding pad area adhere to the patterned dielectric layer (adhesi 〇n) increase, strengthen the interlocking ability of the entire joint ridge structure (interlocck capabi 1 1 ty), to avoid the mechanical stress and ultrasonic vibration applied by the wire bonding machine during wire bonding, which will cause the metal pad to peel and pit. Issue
0503-8562TWF(Nl) : TSMC2001-1316 ; Felicia.ptd 第 1〇 頁 587321 五、發明說明(8) 生。 本發明雖以較佳實施例揭露如上,然其並非用以限定 本發明的範圍,任何熟習此項技藝者,在不脫離本發明之 精神和範圍内,當可做些許的更動與潤飾,因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。0503-8562TWF (Nl): TSMC2001-1316; Felicia.ptd Page 10 587321 V. Description of the invention (8). Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the scope of the present invention. Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.
0503-8562TWF(Nl) ; TSMC200M316 ; Felicia.ptd 第11頁0503-8562TWF (Nl); TSMC200M316; Felicia.ptd page 11
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