TW586207B - Flip-chip die - Google Patents
Flip-chip die Download PDFInfo
- Publication number
- TW586207B TW586207B TW091101433A TW91101433A TW586207B TW 586207 B TW586207 B TW 586207B TW 091101433 A TW091101433 A TW 091101433A TW 91101433 A TW91101433 A TW 91101433A TW 586207 B TW586207 B TW 586207B
- Authority
- TW
- Taiwan
- Prior art keywords
- signal
- pad
- flip
- metal layer
- ball
- Prior art date
Links
- 239000010410 layer Substances 0.000 claims description 57
- 239000002184 metal Substances 0.000 claims description 52
- 239000011241 protective layer Substances 0.000 claims description 13
- 238000005272 metallurgy Methods 0.000 abstract description 7
- 238000002161 passivation Methods 0.000 abstract 3
- 235000012431 wafers Nutrition 0.000 description 36
- 229910000679 solder Inorganic materials 0.000 description 12
- 238000012536 packaging technology Methods 0.000 description 6
- 230000003068 static effect Effects 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 235000013305 food Nutrition 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Description
08670twf2.doc/006 第91101433號說明書修正本
修正日期92.12.18 (發明說明應敘明:發明所屬之技術領域、先前技術、內容、實 施方式及圖式簡單說明) 【發明所屬之技術領域】 本發明是有關於一種覆晶晶片,且特別是有關於一種 具有不同尺寸的銲墊及球底金屬層之接觸面積的覆晶晶 片。 【先前技術】 在現今資訊爆炸的社會,電子產品遍佈於日常生活 中,無論在食衣住行育樂各方面,均會應用到積體電路元 件所組成的產品,且伴隨著電子科技不斷地演進,功能性 更複雜、更人性化的產品不斷推陳出新,就電子產品外觀 而言,也朝向輕、薄、短、小的趨勢設計,因此,在半導 體封裝(Package)的領域亦對應開發出許多高密度半導 體封裝的技術,例如覆晶封裝(Flip Chip,F/C)及球格 陣列封裝(Ball Grid Array,BGA)等等。 覆晶封裝技術主要是在晶片(Die)的銲墊(Pad)上 形成凸塊(Bump)之後,再將翻面後之晶片經由凸塊而 直接連接至基板(Substrate)或印刷電路板(Printed Circuit Board,PCB)上,與打線(Wire Bonding)及軟片自動貼 合(Tape Automatic Bonding,TAB )的封裝技術相較之下, 覆晶封裝技術將可提供較短的訊號傳導路徑,故具有較佳 的電氣特性。此外,覆晶封裝技術亦可設計將晶背裸露在 外’用以提筒晶片於運作時的散熱效率。基於上述原因’ 修正日期92.12.18 08670twf2.doc/006 第91101433號說明書修正本 覆晶封裝技術係普遍地運用在半導體封裝產業上。 請參考第1圖,其爲習知之一種覆晶晶片(Flip Chip Die)的剖面示意圖。覆晶晶片100主要係組成自晶片102 及多個凸塊114 (僅繪示其中之二),其中晶片1〇2之主 動表面(Active Surface ) 104 上配置有一保護層(Passivation Layer ) 106及多個銲墊110 (同樣僅繪τκ其中之二),而 保護層106之開口 108係暴露出銲墊11〇。此外’爲了增 加凸塊114與銲墊110之間的接合性,通常是配置球底金 屬層(Under Ball Metallurgy,UBM ) 112 於靜墊 110 上’ 用以作爲凸塊114與銲墊110之間的接合媒介’最後使得 覆晶晶片100可經由凸塊Π4而連接至外界之基板或印刷 電路板上。 請同樣參考第1圖,依照功能上的不同,銲墊110可 區分爲訊號銲墊(signal Pad )及電源/接地銲墊 (Power/Ground Pad),而凸塊114亦可對應區分爲訊號 凸塊(Signal Bump)及電源/接地凸塊(power/Ground Bump)。値得注意的是,由於習知設計之銲墊110與球 底金屬層112之間的接觸面積均相同,使得電流經由靜墊 110流至球底金屬層112的電流流量相同。爲了達到晶片 102之全部電源/接地所需之電流流量,習知係藉由增加靜 墊110的數量,特別是增加電源/接地銲墊的數目,來達 成上述之目的。 【發明內容】 本發明之目的在於提供一種覆晶晶片’可允許較大的 修正日期92.12.18 08670twf2.doc/006 第91101433號說明書修正本 電流從銲墊通過球底金屬層,而降低晶片之電源/接地銲 墊的數目,並提供晶片更佳的電氣性能。 基於本發明之上述目的,本發明提出一種覆晶晶片, 此覆晶晶片具有一晶片,其具有一主動表面、一保護層、 至少一訊號銲墊及至少〜非訊號銲墊,其中保護層、訊號 銲墊及非訊號銲墊均配置於晶片之主動表面,且保護層係 暴露出訊號銲墊及非訊號銲墊。此外,此覆晶晶片更具有 至少一訊號球底金屬層,其配置於訊號銲墊上,以及至少 一非訊號球底金屬層,其配置於非訊號銲墊上,其中非訊 號球底金屬層與非訊號銲墊之間的接觸面積係至少大於訊 號球底金屬層與訊號銲墊之間的接觸面積之1〇 %。另外, 此覆晶晶片具有包括至少〜訊號凸塊,其配置於訊號球底 金屬層上,以及至少一非訊號凸塊,其配置於非訊號球底 金屬層上。 爲讓本發明之上述目的、特徵和優點能明顯易懂,下 文特舉一較佳實施例,並配合所附圖示,作詳細說明如下: 【圖式簡單說明】 第1圖爲習知之一種覆晶晶片的剖面示意圖; 第2圖爲本發明之較佳實施例之一種覆晶晶片的剖面 示意圖;以及 第3圖爲本發明之較佳實施例之另一種覆晶晶片的剖 面7K意圖。 【圖式標示說明】 100 :覆晶晶片 102 :晶片 08670twf2.doc/006 修正日期 92.12.18 第91101433號說明書修正本 104 :主動表面 106 :保護層 108 :開口 110 :銲墊 112 :球底金屬層 114 :凸塊 200、300 :覆晶晶片 202、302 :晶片 2〇4、304 :主動表面 206、306 :保護層 208a、308a :第一開口 208b、308b ··第二開口 210a、310a :第一銲墊 210b、310b :第二銲墊 212a、312a :第一球底金屬層 212b、312b :第二球底金屬層 214a、314a ··第一凸塊 214b、314b :第二凸塊 586207 【實施方式】 較佳實施例 請參考第2圖,其爲本發明之較佳實施例之一種覆晶 晶片的剖面示意圖。覆晶晶片200主要包括晶片202、多 個第一凸塊214a (僅繪示其中之一)及多個第二凸塊214b (僅繪示其中之一)。晶片202具有一主動表面204、一 保護層206、多個第一銲墊210a (僅繪示其中之一)及多 個第二銲墊210b (僅繪示其中之一),其中主動表面2〇4 係泛指晶片202之具有主動元件(Active Device)的一面。 此外,保護層206、第一銲墊210a及第二銲墊210b則配 置於該晶片202之該主動表面204,其中第一銲墊210a及 7 修正日期92.12.18 08670twi2.doc/006 第91101433號說明書修正本 第二銲墊210b係可爲晶片202之原有銲墊,亦或是晶片202 之重配置線路層(Redistribution Layer)(未繪不)所構 成的銲墊。 請同樣參考第2圖,保護層206係具有至少一第一開 口 208a及至少一第二開口 208b,其分別對應暴露出第一 銲墊210a及第二銲墊210b,値得注意的是,第二開口 208b 之孔徑約略大於該第一開口 208a之孔徑,如此將使得第 二銲墊210b所暴露出之面積大於第一銲墊210a所暴露出 之面積。 請同樣參考第2圖,爲了增加第一凸塊214a與第一 銲墊210a之間的接合性,以及增加第二凸塊214b與第二 銲墊210b之間的接合性,覆晶晶片200更具有至少一第 一球底金屬層212a及至少一第二球底金屬層212b,其中 第一球底金屬層212a係配置於第一銲墊210a上,而第二 球底金屬層212a則配置於第二銲墊210a上。値得注意的 是,第一球底金屬層212a必須完全涵蓋第一銲墊210a所 暴露出來的表面,爲了避免受到對位誤差的影響,第一球 底金屬層212a (第二球底金屬層212b)之分佈面積通常 設計大於第一銲墊210a (第二銲墊210b)所暴露出來的 面積,此外,於凸塊製程時,可藉由控制第一球底金屬層 212a (第二球底金屬層212b)之面積,對應控制第一凸塊 214a (第二凸塊214b)之高度。另外,由於第二銲墊210b 所暴露出之面積係至少大於第一銲墊210a所暴露出之面 積之10 %,使得第二球底金屬層212b與第二銲墊210b之 修正日期92.12.18 08670twf2.doc/006 第91101433號說明書修正本 間的接觸面積將至少大於第一球底金屬層212a與第一銲 墊210a之間的接觸面積之10 %。 請同樣參考第2圖,當設計以第一銲墊210a作爲訊 號銲墊,並以第二銲墊210b作爲電源/接地銲墊(即非訊 號銲墊)時,由於第二球底金屬層212b與第二銲墊210b 之間的接觸面積係至少大於第一球底金屬層212a與第一 銲墊210a之間的接觸面積之10 %,故可允許較大的電流 從第二銲墊210b通過第二球底金屬層212b。此外,當第 二球底金屬層212b之尺寸增加時,第二凸塊214b之體積 亦將對應增加,同時在第一凸塊214a與第二凸塊214b之 高度相同的情況下’將可增加電流通過的截面積’因而降 低第二凸塊214b之電性阻抗値,進而提高晶片202之電 氣效能。 承上所述,由於第二銲墊210b與第二球底金屬層212b 之間的接觸面積較大’故可允許較大的電流從第二靜墊 210b流經第二球底金屬層212b,與習知第1圖之覆晶晶 片100相較之下,爲了達到晶片202之全部電源/接地所 需要之電流流量’可應用本發明之覆晶晶片200的設計’ 對應增加電源/接地銲墊(即非訊號銲墊)與其球底金屬 層之間的接觸面積’而無須額外設計增加銲墊之數目’或 者僅設計增加相當少之銲墊數目來達到上述目的° 此外,爲了更增加第2圖之第二球底金屬層212b與 第二銲墊210b之間的接觸面積’請參考第3圖’其爲本 發明之較隹實施例之另一種覆晶晶片的剖面示意圖。第3 586207 08670twf2.doc/006 修正日期 92.12.18 第91101433號說明書修正本 圖與第2圖的不同處在於覆晶晶片300之第二銲墊310b 的面積係大於覆晶晶片200之第二銲墊210b的面積。如 第3圖之覆晶晶片300所示,可設計增加第二銲墊310b 之面積,並對應增加第二開口 308b之孔徑,進而增加第 二銲墊310b所暴露出之面積,再配置上更大面積的第二 球底金屬層310b,使得第二球底金屬層312b與第二銲墊 31〇b之間的接觸面積更大。 綜上所述,本發明之覆晶晶片具有銲墊與球底金屬層 之接觸面積大小不同的設計,主要是藉由增大保護層之開 口的孔徑,而增加銲墊所暴露出之面積,並同時增加球底 金屬層之分佈面積,進而增加銲墊與球底金屬層之間的接 觸面積,故可允許較大的電流從銲墊通過球底金屬層。此 外,本發明更可藉由設計增加銲墊之面積,並對應增加開 口之孔徑,同時增加球底金屬層之分佈面積,亦將增加銲 墊與球底金屬層之間的接觸面積。 由於本發明之覆晶晶片係具有銲墊與球底金屬層之接 觸面積不同大小的設計,故可允許較大範圍的電流從銲墊 通過球底金屬層,因而降低電流從銲墊通過球底金屬層之 電性阻抗,進而提升晶片之整體的運作效能。此外,在球 底金屬層之分佈面積亦同時增加的情況下,將對應增加凸 塊之體積,故可增加電流通過的截面積,進而提高晶片之 電氣效能。另外,爲了達到晶片之電源/接地原先設計所 需要的電流流量,本發明係對應增加電源/接地銲墊(即 非訊號銲墊)與其球底金屬層之間的接觸面積,因此無須 10 586207 08670twf2.doc/006 修正日期 92.12.18 第91101433號說明書修正本 大幅增加電源/接地銲墊(即非訊號銲墊)之數目來達到 上述目的。 雖然本發明已以一較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 神和範圍內,當可作些許之更動與潤飾,因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 11
Claims (1)
- 586207 08670twf3.doc/006 拾、申請專利範圍 1. 一種覆晶晶片,至少包括: 一晶片,具有一主動表面、一保護層、至少一訊號銲 墊及至少一非訊號銲墊,其中該保護層、該訊號銲墊及該 非訊號銲墊均配置於該晶片之該主動表面,且該保護層係 暴露出該訊號銲墊及該非訊號銲墊; 至少一訊號球底金屬層,配置於該訊號銲墊上; 至少一非訊號球底金屬層,配置於該非訊號銲墊上, 其中該非訊號球底金屬層與該非訊號銲墊之間的接觸面積 係至少大於該訊號球底金屬層與該訊號銲墊之間的接觸面 積之10 % ; 至少一訊號凸塊,配置於該訊號球底金屬層上;以及 至少一非訊號凸塊,配置於該非訊號球底金屬層上。 2·如申請專利範圍第1項所述之覆晶晶片,其中該 非訊號銲墊係爲電源銲墊及接地銲墊其中之一。 3·如申請專利範圍第1項所述之覆晶晶片,其中該 非訊號凸塊之高度係相當於該訊號凸塊之高度。 4·如申請專利範圍第1項所述之覆晶晶片,其中該 非訊號銲墊所暴露出之面積係大於該訊號銲墊所暴露出之 面積。 5·如申請專利範圍第1項所述之覆晶晶片,其中該 非訊號球底金屬層之分佈面積係大於該訊號球底金屬層之 分佈面積。 6.如申請專利範圍第1項所述之覆晶晶片,其中該 12 586207 08670twf3 .doc/006 修正日期93.2.16 非訊號銲墊之面積係大於該訊號銲墊之面積。 7.如申請專利範圍第1項所述之覆晶晶片,其中該 晶片更具有一重配置線路層,其配置於該晶片之該主動表 面,而該訊號銲墊及該非訊號銲墊係由該重配置線路層所 構成。13
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TW091101433A TW586207B (en) | 2002-01-29 | 2002-01-29 | Flip-chip die |
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US7576436B2 (en) * | 2002-12-13 | 2009-08-18 | Advanced Semiconductor Engineering, Inc. | Structure of wafer level package with area bump |
TW586199B (en) * | 2002-12-30 | 2004-05-01 | Advanced Semiconductor Eng | Flip-chip package |
DE10352349B4 (de) * | 2003-11-06 | 2006-11-16 | Infineon Technologies Ag | Halbleiterchip mit Flip-Chip-Kontakten und Verfahren zur Herstellung desselben |
JP4758678B2 (ja) * | 2005-05-17 | 2011-08-31 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20070045845A1 (en) * | 2005-08-31 | 2007-03-01 | Anand Lal | Ball grid array interface structure and method |
US7485563B2 (en) * | 2006-06-29 | 2009-02-03 | Intel Corporation | Method of providing solder bumps of mixed sizes on a substrate using a sorting mask and bumped substrate formed according to the method |
US9000876B2 (en) | 2012-03-13 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Inductor for post passivation interconnect |
TWI435350B (zh) * | 2012-06-05 | 2014-04-21 | Delta Electronics Inc | 變壓器 |
US8969191B2 (en) * | 2013-07-16 | 2015-03-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Mechanisms for forming package structure |
US10559547B2 (en) * | 2017-06-28 | 2020-02-11 | Murata Manufacturing Co., Ltd. | Semiconductor chip |
JP2019009409A (ja) * | 2017-06-28 | 2019-01-17 | 株式会社村田製作所 | 半導体チップ |
US11855017B2 (en) * | 2021-01-14 | 2023-12-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method |
US20230068329A1 (en) * | 2021-08-30 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device |
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US5851911A (en) * | 1996-03-07 | 1998-12-22 | Micron Technology, Inc. | Mask repattern process |
US6118180A (en) * | 1997-11-03 | 2000-09-12 | Lsi Logic Corporation | Semiconductor die metal layout for flip chip packaging |
US5977632A (en) * | 1998-02-02 | 1999-11-02 | Motorola, Inc. | Flip chip bump structure and method of making |
JP2000100814A (ja) * | 1998-09-18 | 2000-04-07 | Hitachi Ltd | 半導体装置 |
TW459362B (en) * | 2000-08-01 | 2001-10-11 | Siliconware Precision Industries Co Ltd | Bump structure to improve the smoothness |
US6348401B1 (en) * | 2000-11-10 | 2002-02-19 | Siliconware Precision Industries Co., Ltd. | Method of fabricating solder bumps with high coplanarity for flip-chip application |
US6433427B1 (en) * | 2001-01-16 | 2002-08-13 | Industrial Technology Research Institute | Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication |
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