586140 (1) 玖、發明說明 【發明所屬之技術領域】 本發明係相關於一種以鋁金屬作爲導電材質所製之電 容器以及電感器之積體製程方法，特別是，相關於一種鋁 金屬堆疊式金屬電容器以及鋁材質堆疊式電感器之積體製 程方法。 【先前技術】 習知之鋁金屬電容器以及電感器之構成圖係如圖1所 示0 習知以鋁金屬爲混合信號或高頻信號之導線體之製程 技術，由於鋁金屬本身之電阻高，所產生之效果皆不盡理 想。 以電感器而言，需要維持一高Q値。所謂該Q値， 係指施加一頻率（f)下，等效電感値與角頻率（6；=2;rf )之乘積再除以等效電阻値之値。在習知鋁金屬電容器中 ，卻由於所生電阻値偏高，因此，所產生之Q値皆不盡理 想。例如，對於習知具有2微米厚度鋁金屬2nH之電感値 之電感器，其Q値只有約爲9。 以習知電容器而言，其功效尙顯不足，其不足之處包 括：單位面積之電容量仍待提昇，在此同時，電壓値與所 產生電容値之間’需保持爲線性，以及需要提昇電容器之 崩潰電壓，以因應當代較爲頻繁使用之高施加電壓値。 (2) (2)586140 【發明內容】 本發明在提中一種鋁金屬電容器以及電感器之積體製 程，而提高鋁金屬電感器之Q値，以及提高鋁金屬爲材質 之金屬-絕緣-金屬（Metal-Insulator-Metal ) ，MIM電容器 之單位面積電容値，並且保持施加電壓値與所生電容値之 線性關係以及提高電容器之崩潰電壓。本發明鋁金屬之電 感器Q値，相對於銅金屬電感器Q値，係更爲提昇，且 電容器之效能亦大大提昇。 【實施方式】 如圖1所示，係習知電容器以及電感器之構成圖。該 圖中之電容極板延伸體（1 )、電容極板延伸體（2 )以及 電感器主體（5)之高度爲2微米。 圖2至圖4所示者，係爲本發明堆疊式電容器以及電 感器所實施之步驟圖。本發明之鋁材質堆疊式金屬電容器 以及鋁材質堆疊式電感器之積體製程方法中，該堆疊式金 屬電容器包含電容極板延伸體（1 )、電容極板延伸體（2 )、電容極板（3)以及電容極板（4)，該堆疊式電感器 包含一電感器主體（5)以及電感器延伸體（6)，該電容 極板延伸體（1 )、電容極板延伸體（2 )以及電感器主體 (5 )係設置於介電層（7 )之上，而電容極板（3 )、電 容極板（4 )以及電感器延伸體（6 )係設置於該介電層 (7)之中，該電容極板（3)、電容極板（4)對向設置， 該介電層（7 )中之其餘部位爲氧化物（8 )所注滿，該方 (3) (3)586140 法包含以下步驟： &〜半導體基底（11)之上，形成積體電路所需之半 導體元:件，再於其上形成介電層（12)，其中包含後端工 藝（Backend)金屬互連線（Interconnect); 在介電層（12)之上，依次沉積金屬層，電容器介電 質’金屬層。經由兩次曝光，鈾刻，第一次界定電容極板 (3)和電容器介電質（9)，第二次界定電容極板（4) 和電感器延伸體（6 )。 其後沉積氧化物，經化學機械拋光法形成介電層（7 )°再經曝光，蝕刻，金屬塡充，化學機械拋光法形成金 屬層間電連接線（i 〇 )。 第一疊層島形體形成步驟，係在該介電層（7)之上 ，經由金屬沉積，曝光，蝕刻步驟，以鋁金屬而形成三個 島形體，分別爲該電容極板延伸體（1 )、該電容極板延 伸體（2)以及該電感器主體（5)，且該三個島形體在介 電層（7)之上表面，分別通過金屬層間電連接線（10 )與 該電容極板（3)、該電容極板（4)以及該電感器延伸體 (6 )形成電接觸； 第一疊層形成步驟，係以沈積方式塡滿氧化物（1 3 ) 於該電容極板延伸體（1 )、該電容極板延伸體（2 )以及 該電感器主體（5 )之四周，並使該氧化物（1 3 )之上表 面以化學機械拋光法（CMP )，或是與氧化物濕蝕刻法混 合使用而處理表面，而形成第一疊層（1 4 )。如混合使用 時，該化學機械拋光法在該電容極板延伸體（1 )、該電 -8- (4)586140 容極板延伸體（2 )以及該電感器主體（5 )之上剩餘 物厚度爲20…200A ; 第二疊層形成步驟（參考圖2)，係於該第一疊 14)之上，沈積一電容介電層，而成爲一第二疊層電 介電質（15); 第二疊層電容介電層處理步驟（參考圖3)，係 光與蝕刻方法，完全移除位於該電容極板延伸體（： 及該電感器主體（5)之上之電容介電層，而分別作 容極板延伸體接觸部（1 6 )以及電感器接觸部（1 8 ) 僅部份移除該電容極板延伸體（1 )之上的電容介電 該部份移除表面積係與電容極板延伸體（2 )之表面 近作爲電容極板延伸體接觸部（1 7 ); 第三疊層島形體形成步驟（參考圖4)，係在電 板延伸體C接觸部（1 7 )、電容極板延伸體接觸部（ 以及電感器接觸部（1 8 )之上，以沈積，曝光與蝕刻 上厚層之鋁物質，該電容極板延伸體接觸部（1 6 )之 厚層鋁物質向電容極板延伸體接觸部（17 )方向延伸 形成與電容極板延伸體（1)相近之尺寸； 位於該電容極板延伸體接觸部（17)、該電容極 伸體接觸部（1 6 )以及電感器接觸部（1 8 )之上之厚 物質係分別作爲電容極板延伸體（20 )、電容極板延 (21 )以及第三疊層電感器主體（22 )。其中電容極 伸體（2 1 )與電容極板延伸體（1)以其間的第二疊層 器介電質（1 5 )形成電容，加之電容極板（3 )、電 氧化 層（ 容器 以曝 :)以 爲電 ，但 層， 積相 容極 16) 而佈 上之 ，並 板延 層鋁 伸體 板延 電容 容極 -9 - (5) (5)586140 板（4 )之間電容，使單位面積之電容量較之傳統制程爲 高。 其中，可重複上述第一疊層形成步驟，第二疊層電容 介電層處理步驟、第三疊層島形體形成步驟，而形成更多 層的鋁材質堆疊式金屬電容器以及鋁材質堆疊式電感器。 本發明之另一特徵在於，緊接鋁金屬之後的氧化物與 電容介電層之設置，係先沈積該氧化物，之後經由化學機 械拋光法，或與氧化物濕蝕刻法混合使用而與該些島狀物 之上的氧化物平面化，之後再沈積該電容介電層。 本發明之另一特徵在於該第三疊層之鋁物質係在沈積 之第一時間而與第一疊層之鋁材質接觸部相接觸以形成接 點。 本發明之另一特徵在於該第三疊層經疊置之後，電感 器主體之總厚度（第一疊層加第三疊層）係超過3微米。 雖然本發明係以實施例以而說明，對於熟知此技藝者 可在不離開本發明之基本觀念以及範圍下而有許多之修改 【圖式簡單說明】 圖1係展示習知電容器以及電感器之構成圖； 圖2係展示本發明以沈積氧化物，再化學機械拋光法 或與氧化物濕蝕刻法混合使用，且之後沈積介電層之構成 圖； 圖3係展不本發明在圖2之介電層之上，以曝光以及 -10· (6) (6)586140 蝕刻而處理之構成圖；以及 圖4係展示本發明在圖3之上，形成金屬、氧化物以 及介電層，以構成堆疊式電容器以及電感器之構成圖。 主要元件對照表 1:電容極板延伸體 2 :電容極板延伸體 3:電容極板 φ 4 :電容極板 5 :電感器主體 6:電感器延伸體 7:介電層 8:氧化物 9:電容器電介質 10:金屬層間電連接線 1 1:半導體基底 _ 12:介電層 1 3 :氧化物 14:第一疊層 15:第二疊層電容器介電質 1 6 :電容極板延伸體接觸部 1 7 :電容極板延伸體接觸部 1 8 :電感主體接觸部 1 9 :第三疊層島形體 -11 - (7) (7)586140 20:電容極板延伸體 21:電容極板延伸體 22:第三疊層電感器主體 -12-586140 (1) Description of the invention [Technical field to which the invention belongs] The present invention relates to a method for integrating capacitors and inductors made of aluminum metal as a conductive material, and in particular, to an aluminum metal stack type Integrated method of metal capacitors and aluminum stacked inductors. [Previous technology] The structure diagram of conventional aluminum metal capacitors and inductors is shown in Figure 1. 0 The manufacturing process technology of aluminum conductors with mixed signals or high-frequency signals is known. Due to the high resistance of aluminum metals, The results are not ideal. In terms of inductors, a high Q 値 needs to be maintained. The so-called Q 値 refers to the product of the equivalent inductance 値 and the angular frequency (6; = 2; rf) divided by the equivalent resistance 下 at a frequency (f). In the conventional aluminum metal capacitors, due to the high resistance 値 generated, the resulting Q 生 is not ideal. For example, for conventional inductors having an inductance 値 of aluminum metal 2nH with a thickness of 2 micrometers, the Q 値 is only about 9. As far as conventional capacitors are concerned, their efficacy is not sufficient. The disadvantages include: the capacitance per unit area still needs to be improved. At the same time, the voltage between the voltage 値 and the capacitance 値 needs to be kept linear, and it needs to be improved The breakdown voltage of the capacitor should be applied to a high applied voltage, which is more frequently used. (2) (2) 586140 [Summary of the invention] The present invention is to improve the integration process of an aluminum metal capacitor and an inductor, to improve the Q 値 of the aluminum metal inductor, and to improve the metal-insulation-metal of aluminum metal. (Metal-Insulator-Metal), the capacitance per unit area of the MIM capacitor 値, and maintain a linear relationship between the applied voltage 値 and the generated capacitance 以及 and increase the breakdown voltage of the capacitor. Compared with the copper metal inductor Q 値, the aluminum metal inductor Q 値 of the present invention is more improved, and the performance of the capacitor is also greatly improved. [Embodiment] As shown in FIG. 1, it is a configuration diagram of a conventional capacitor and an inductor. The height of the capacitor plate extension (1), the capacitor plate extension (2), and the inductor body (5) in the figure is 2 micrometers. The steps shown in Figs. 2 to 4 are step diagrams implemented by the stacked capacitors and inductors of the present invention. In the integrated method of the aluminum material stacked metal capacitor and the aluminum material stacked inductor of the present invention, the stacked metal capacitor includes a capacitor plate extension (1), a capacitor plate extension (2), and a capacitor plate (3) and a capacitor plate (4), the stacked inductor includes an inductor body (5) and an inductor extension body (6), the capacitor plate extension body (1), and the capacitor plate extension body (2) ) And the inductor body (5) are disposed on the dielectric layer (7), and the capacitor plate (3), the capacitor plate (4), and the inductor extension (6) are provided on the dielectric layer ( 7), the capacitor plate (3) and the capacitor plate (4) are oppositely arranged, and the rest of the dielectric layer (7) is filled with the oxide (8), and the side (3) ( 3) The 586140 method includes the following steps: & ~ On the semiconductor substrate (11), the semiconductor elements required to form the integrated circuit are formed, and then a dielectric layer (12) is formed thereon, which includes the back-end process (Backend ) Metal interconnect (Interconnect); on top of the dielectric layer (12), a metal layer is deposited in sequence, the capacitor dielectric 'metal layerAfter two exposures, uranium engraving, the capacitor plate (3) and the capacitor dielectric (9) were defined for the first time, and the capacitor plate (4) and the inductor extension (6) were defined for the second time. Thereafter, an oxide is deposited, and a dielectric layer (7) is formed by a chemical mechanical polishing method, and then exposed, etched, metal charged, and a chemical mechanical polishing method is used to form a metal interlayer electrical connection line (io). The first laminated island-shaped body forming step is based on the dielectric layer (7), and three metal island-shaped bodies are formed from aluminum metal through metal deposition, exposure, and etching steps, which are the capacitor plate extensions (1 ), The capacitor plate extension (2) and the inductor body (5), and the three island-shaped bodies are on the surface of the dielectric layer (7), and are connected to the capacitor through a metal interlayer electrical connection line (10), respectively. The electrode plate (3), the capacitor plate (4), and the inductor extension (6) form electrical contact; the first stack forming step is to fill the capacitor plate with an oxide (1 3) in a deposition manner. The extension body (1), the capacitor plate extension body (2) and the inductor body (5), and the upper surface of the oxide (1 3) is subjected to chemical mechanical polishing (CMP), or The oxide wet etching method is used in combination to process the surface to form a first stack (1 4). If used in combination, the chemical mechanical polishing method leaves residues on the capacitor plate extension (1), the electric-8- (4) 586140 capacitor plate extension (2), and the inductor body (5). The thickness is 20 ... 200A; the second stack forming step (refer to FIG. 2) is deposited on the first stack 14), and a capacitor dielectric layer is deposited to become a second stack dielectric (15) The second laminated capacitor dielectric layer processing step (refer to FIG. 3), which is a method of light and etching, completely removes the capacitor dielectric layer located on the capacitor plate extension (: and the inductor body (5)); The capacitor dielectric extension part (1 6) and the inductor contact part (1 8) respectively only partially remove the capacitor dielectric on the capacitor plate extension (1), and the part removes the surface area. It is close to the surface of the capacitor plate extension (2) as the capacitor plate extension contact (17); the third laminated island-shaped body forming step (refer to FIG. 4) is at the contact portion of the electric plate extension C ( 17) on the contact part of the extension of the capacitor plate (and the contact part of the inductor (18)) to deposit, expose and etch a thick layer of aluminum The thick layer of aluminum material of the contact portion (16) of the capacitor plate extension body extends toward the contact portion (17) of the capacitor plate extension body to form a size similar to that of the capacitor plate extension body (1); located on the capacitor plate The thick material on the extension body contact portion (17), the capacitor pole extension portion (1 6) and the inductor contact portion (1 8) serves as the capacitor plate extension (20) and the capacitor plate extension ( 21) and a third laminated inductor body (22), wherein the capacitor pole extension (2 1) and the capacitor plate extension (1) form a capacitor with a second laminate dielectric (1 5) in between, In addition, the capacitor electrode plate (3), the electrical oxidation layer (the container is exposed :) are considered as electricity, but the layer, the product compatible electrode 16) are laid on the board, and the aluminum extended body and the plate extended the capacitor capacity -9-( 5) (5) 586140 The capacitance between the plates (4) makes the capacitance per unit area higher than that of the traditional process. Among them, the above-mentioned first laminated formation step, the second laminated capacitor dielectric layer processing step, The third laminated island-shaped body forming step, so as to form more layers of aluminum stacked metal capacitors and aluminum materials Stacked inductor. Another feature of the present invention is that the oxide and the capacitor dielectric layer immediately after the aluminum metal are deposited first, and then subjected to a chemical mechanical polishing method or an oxide wet etching method. It is mixed and used to planarize the oxides on the islands, and then deposit the capacitor dielectric layer. Another feature of the present invention is that the aluminum material of the third stack is deposited with the first time of deposition. The aluminum contacts of the first stack are in contact to form a contact. Another feature of the present invention is that after the third stack is stacked, the total thickness of the inductor body (the first stack plus the third stack) Department of more than 3 microns. Although the present invention is described by way of examples, those skilled in the art can make many modifications without departing from the basic concept and scope of the present invention. [Schematic description] Figure 1 shows the conventional capacitors and inductors. Composition diagram; FIG. 2 shows the composition diagram of the present invention by depositing an oxide, then chemical mechanical polishing method or mixed with oxide wet etching method, and then depositing a dielectric layer; FIG. 3 shows the invention in FIG. 2 The structure diagram of the dielectric layer processed by exposure and -10 · (6) (6) 586140 etching; and FIG. 4 shows the present invention on FIG. 3 to form a metal, oxide, and dielectric layer to Structure diagram of stacked capacitors and inductors. Comparison table of main components 1: capacitor plate extension 2: capacitor plate extension 3: capacitor plate φ 4: capacitor plate 5: inductor body 6: inductor extension body 7: dielectric layer 8: oxide 9 : Capacitor dielectric 10: Metal interlayer electrical connection line 1 1: Semiconductor substrate_ 12: Dielectric layer 1 3: Oxide 14: First stack 15: Second stack capacitor dielectric 16: Capacitor plate extension Contact part 17: Capacitor plate extension body Contact part 18: Inductor body contact part 19: Third laminated island body -11-(7) (7) 586140 20: Capacitor plate extension 21: Capacitor plate Extension body 22: third laminated inductor body-12-