玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、內容、實 施方式及圖式簡單說明） 發明所屬技術之盤 本發明是有關於頻率調變類比積體電路解調器，且特 別是有關於一種利用能量密度不同來解調調變訊號的解調 器。 先前技術 以下說明習知的頻率調變類比解調技術’特別注意的 是習知技術不使用積體電路的方式實現頻率調變類比解調 技術。首先，若一'個頻率調變訊號使用數位的方式解調’ 則其訊號在時域(time domain)的情形爲： 桌（1)式 冲)=4 C0S(2v/c，+ 2;^ £ m⑺汾） 一般的做法是將此方程式經過一個延遲’經過一段時 間的延遲後，可以表示爲： 弟（2)式 邓 + r) = 4 cos(2;r/c(/ + r) + 2；^· f 之後，（1)乘（2)，再經過濾波’將局項項濾掉’即可 解出 第(3)式 τη{ί) = γ{[πι{ί)άί) 由第（3)式得知，運算後的結果爲m(t)。因此’此過程 爲一個微分器，此時與m⑴的資料速率有關。若資料速率 愈高，耗電流愈大。 10338twf.doc/008 4 584989 現今常用的類比解調方式使用一個外接式分離器與一 組外接式的RC電路，結合成一個高品質因數的RLC：共振 器，其中心頻率爲fc。再者，一個調變訊號可視爲一個資 料調變成一個載子（carrier，中心頻率爲fc)。右經過分離 器後，會產生某種程度的遲延，則此中心頻率產生的相位 變化爲九十度。相同的，若將此變化後的訊號與原來的調 變訊號做相乘運算，再濾去高頻項，則所得的資料即爲解 調訊號。 再者，由於習知的頻率調變（frequency modulation)類 比解調技術使用外部元件組合而成(如：LC tank)，所以此 方式的缺點是資料速率（data rate)有頻寬的限制。再者， 若利用數位電路實現頻率調變解調技術，則需一個過度取 樣（oversampk)的時脈訊號，且同樣的資料速率與時脈訊 號需有相對的關係，因此，增加許多使用上的困難。除此 之外，利用數位電路實現頻率調變解調技術更有耗電較大 的缺點，且須配合類比電路。 發明內容 有鑒於此，本發明的目的就是在提供一種頻率調變類 比積體電路解調器。此解調器利用積體電路的方式製作， 增加利用上的便利性。再者，利用訊號能量密度的特性進 行解調變，可以降低功率損耗且降低頻寬的限制。 爲達成上述及其他目的，本發明提出一種頻率調變類比積體 電路解調器，其組成包括由零點檢知器輸入一個原始調變 訊號，並根據一個基礎電壓準位輸出一個第一解調訊號； 第一充放電路耦接於該零點檢知器，輸入該第一解調訊號 10338twf.doc/008 5 584989 且輸出一第二解調訊號；峰値檢知器耦接於第一充放電 路，輸入該第二解調訊號且輸出一完成解調訊號。再者’ 亦可不使用峰値檢知器，而使用一個乘法器。乘法器耦接 於第一充放電路，當輸入第二解調訊號與原始調變訊號 後，輸出一完成解調訊號。 依照本發明的較佳實施例所述，上述之零點檢知器包 含一個正向訊號與負向訊號，利用這二個訊號控制第一充 放電路。 依照本發明的較佳實施例所述，上述之原始調變訊號 * 若大於基礎電壓準位時，第一充放電路執行一充電操作。 依照本發明的較佳實施例所述，上述之原始調變訊號 若小於基礎電壓準位時，第一充放電路執行一放電操作。 依照本發明的較佳實施例所述，上述之第一解調訊號 爲頻率不相等之一方波，當輸入第一充放電路後，第一充 放電路輸出之第二解調訊號爲振幅不相等之正弦波。 綜合上述，本發明提出一種頻率調變類比積體電路解調 器。此解調器以積體電路的方式實現，增加利用上的便利 鲁 性。再者，由於利用訊號能量密度的特性進行解調變，所 以可以降低功率損耗且降低頻寬的限制。再者，由於不同 於習知的設計方法，所以本發明不需一個過度取樣的時脈 訊號，且同樣的資料速率與時脈訊號亦不需有相對的關 係，因此，大幅降低使用上的困難，有效提昇使用效率。 由於縮短各項相關應用的設計時程，所以可有效促進產業 發展。 實施方式 10338twf.doc/008 6 584989 請參照第1圖，其繪示依照本發明一較佳實施例的電 路方塊圖。第1圖揭示的頻率調變類比解調器包括能量檢 知器108與峰値檢知器106。其中’能量檢知益1〇8包括 零點檢知器102與第一充放電路104。其中’零點檢知器 102耦接於第一充放電路104，第一充放電路1〇4耦接於 峰値檢知器106。 當零點檢知器輸入一個原始調變訊號時，零屬^檢知器 將根據一個基礎電壓準位輸出一個第一解調訊號。其中， 原始調變訊號波形如第3圖所示，第一解調訊號訊號波形 如第4圖所示，而基礎電壓準位可設爲1伏時。之後，當 第一充放電路輸入第一解調訊號後，第一充放電路會輸出 一第二解調訊號。其中，第一解調訊號訊號波形如第5圖 所示。之後，當峰値檢知器106輸入第二解調訊號後，峰 値檢知器106輸出一完成解調訊號，完成訊號解變的動作。 其中，完成解調訊號波形如第5圖所示。 請參照第2圖，其繪示依照本發明一較佳實施例的電 路方塊圖。第2圖揭示的是如第1圖之能量檢知器108的 電路方塊圖。零點檢知器108以正向訊號204與負向訊號 206耦接於第一充放電路。 觀察第1圖之原始調變訊號，可以發現其訊號的表現 方式爲疏密不一的形式，疏密程度即爲所包含的資料，亦 即，疏密程度即爲時間軸上的能量密度。換句話說，若能 將訊號的能量分出，則可解調出資料。當原始調變訊號輸 入零點檢知器時，由於基礎電壓準位設爲1伏特，所以原 始調變訊號中大於1伏特的波形會產生一段高電壓準位的 10338twf.doc/008 7 584989 方波。相反的，原始調變訊號中小於1伏特的波形會產生 一段低電壓準位的方波。由以上的敘述可知，零點檢知器 108輸出的第一調變訊號是頻率不相等之方波。 接著，第一調變訊號中高電壓準位的方波轉換爲正向 訊號，低電壓準位的方波轉換爲負向訊號。其中，正向訊 號控制切換開關208且使電容212充電。類似的，負向訊 號控制切換開關210且使電容212放電。之後，當第一充 放電路執行一連串的充電操作與放電操作後，則輸出如第 5圖所示的第二解調訊號，其爲振幅不相等之正弦波。 再者，由第二解調訊號的波形可知，由於能量密度較 高的原始調變訊號充放電的時間較短，所以第二解調訊號 產生的對應振幅較低。類似的，由於能量密度較低的原始 調變訊號充放電的時間較長，所以第二解調訊號產生的對 應振幅較高。因此，利用振幅的變化即可解調資料。基於 上述原因，由於爲了分辨出振幅的變化，所以把第二解調 訊號輸入峰値檢知器106。之後，峰値檢知器106即輸出 如第6圖所示之完成解調訊號。 必須要注意的是，上述能量檢知器的內部電路僅爲舉 例之用，然熟習此技藝者當知此並非爲本發明的必要限制 條件而可依環境所需自行調整電路設計方式。 請參照第7圖，其繪示依照本發明一較佳實施例的電 路方塊圖。第7圖揭示的頻率調變類比解調器包括能量檢 知器708與乘法器706。本實施例之元件功能及運作方法 與第1圖實施例近似，不同的是第一充放電路把第二解調 訊號輸入乘法器706。由於第二解調訊號爲振幅（能量）不 10338twf.doc/008 8 584989 相等之正弦波，所以與原始調變訊號一同輸入乘法器706 後，即可解調訊號。 綜合上述，本發明提出一種頻率調變類比積體電路解調 器。由於利用訊號能量密度的特性進行解調變，所以可以 降低功率損耗與頻寬的限制。再者，由於不同於習知的設 計方法，所以本發明不需一個過度取樣的時脈訊號，且同 樣的資料速率與時脈訊號亦不需有相對的關係，因此’大 幅降低使用上的困難，有效提昇使用效率。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 圖式簡單說明 第1圖繪示的是本發明之一最佳實施例之電路方塊 圖， 第2圖繪示的是本發明另一最佳實施例之電路方塊圖 圖； 第3圖繪示的是本發明又一最佳實施例之訊號波形 圖， 第4圖繪示的是本發明其他最佳實施例之訊號波形 圖； 第5圖繪示的是本發明其他最佳實施例之訊號波形 圖； 第6圖繪示的是本發明其他最佳實施例之訊號波形 圖；以及 10338twf.doc/008 9 584989 第7圖繪示的是本發明之一最佳實施例之電路方塊 圖。 圖式標記說明= 102，702 :零點檢知器 1〇4，704 :第一充放電路 106 :峰値檢知器 108，708 :能量檢知器 204 :正向訊號 206 :負向訊號 208 :切換開關 210 :切換開關 212 :電容 706 :乘法器 10 10338twf.doc/008发明 Description of the invention (the description of the invention should state: the technical field, prior art, content, embodiments, and drawings of the invention are briefly explained) The technology of the invention The invention relates to a frequency modulation analog integrated circuit demodulator In particular, it relates to a demodulator that uses different energy densities to demodulate modulation signals. Prior art The conventional frequency modulation analog demodulation technique will be described below. It is to be noted that the conventional technology implements the frequency modulation analog demodulation technique without using an integrated circuit. First, if a frequency modulation signal is demodulated digitally, the signal in the time domain is: Table (1) type punching = 4 C0S (2v / c, + 2; ^ £ m⑺fen) The general approach is to delay this equation after a delay 'after a period of delay, it can be expressed as: Brother (2) Deng + r) = 4 cos (2; r / c (/ + r) + After 2; ^ · f, (1) multiply (2), and then filter 'filter the local term' to solve the formula (3) Equation τη {ί) = γ {[πι {ί) άί) by Equation (3) shows that the result after the operation is m (t). Therefore, this process is a differentiator, which is related to the data rate of m⑴. The higher the data rate, the greater the current consumption. 10338twf.doc / 008 4 584989 The commonly used analog demodulation method today uses an external splitter and a set of external RC circuits to form a high-quality RLC: resonator with a center frequency of fc. Furthermore, a modulation signal can be regarded as a data modulation into a carrier (center frequency is fc). After passing the separator to the right, there will be a certain degree of delay, so the phase change caused by this center frequency is ninety degrees. Similarly, if this changed signal is multiplied with the original modulated signal and the high-frequency terms are filtered out, the obtained data is the demodulated signal. Furthermore, since the conventional frequency modulation analog demodulation technology is composed of external components (such as an LC tank), the disadvantage of this method is that the data rate has a bandwidth limitation. Furthermore, if digital modulation is used to implement the frequency modulation and demodulation technology, an oversampk clock signal is required, and the same data rate and clock signal need to be related. Therefore, a lot of difficult. In addition, the use of digital circuits to implement frequency modulation and demodulation technology has the disadvantage of greater power consumption, and must be matched with analog circuits. SUMMARY OF THE INVENTION In view of this, an object of the present invention is to provide a frequency modulation analog integrated circuit demodulator. This demodulator is made by integrated circuit, which increases the convenience in use. Furthermore, demodulation using the characteristics of the signal energy density can reduce power loss and bandwidth limitations. In order to achieve the above and other objectives, the present invention proposes a frequency modulation analog integrated circuit demodulator. The composition includes a zero point detector inputting an original modulation signal and outputting a first demodulation according to a basic voltage level. Signal; the first charging and discharging circuit is coupled to the zero detector, the first demodulation signal is input 10338twf.doc / 008 5 584989 and a second demodulation signal is output; the peak-to-peak detector is coupled to the first charger The amplifier circuit inputs the second demodulated signal and outputs a completed demodulated signal. Furthermore, it is also possible to use a multiplier instead of the peak detector. The multiplier is coupled to the first charging and discharging circuit. When the second demodulation signal and the original modulation signal are input, the multiplier outputs a completed demodulation signal. According to a preferred embodiment of the present invention, the above-mentioned zero-point detector includes a positive signal and a negative signal, and uses these two signals to control the first charging and discharging circuit. According to a preferred embodiment of the present invention, if the above-mentioned original modulation signal * is greater than the basic voltage level, the first charging and discharging circuit performs a charging operation. According to a preferred embodiment of the present invention, if the above-mentioned original modulation signal is smaller than a basic voltage level, the first charging and discharging circuit performs a discharging operation. According to a preferred embodiment of the present invention, the above-mentioned first demodulation signal is a square wave with an unequal frequency. When the first charge-discharge circuit is input, the second demodulation signal output by the first charge-discharge circuit is an amplitude variable. Equal sine wave. In summary, the present invention provides a frequency modulation analog integrated circuit demodulator. This demodulator is implemented as an integrated circuit, which increases the convenience and convenience in use. In addition, since the demodulation is performed using the characteristics of the signal energy density, the power loss can be reduced and the bandwidth limitation can be reduced. Furthermore, because it is different from the conventional design method, the present invention does not need an over-sampled clock signal, and the same data rate does not need to have a relative relationship with the clock signal. Therefore, the difficulty in use is greatly reduced. , Effectively improve the use efficiency. Since the design time of various related applications is shortened, it can effectively promote industrial development. Embodiment Mode 10338twf.doc / 008 6 584989 Please refer to FIG. 1, which illustrates a block diagram of a circuit according to a preferred embodiment of the present invention. The frequency modulation analog demodulator disclosed in FIG. 1 includes an energy detector 108 and a peak-to-peak detector 106. The 'energy detection benefit 108' includes a zero point detector 102 and a first charge / discharge circuit 104. The 'zero point detector 102' is coupled to the first charge / discharge circuit 104, and the first charge / discharge circuit 104 is coupled to the peak-to-peak detector 106. When the zero point detector inputs an original modulation signal, the zero detector ^ will output a first demodulated signal according to a basic voltage level. Among them, the original modulation signal waveform is shown in Fig. 3, the first demodulation signal waveform is shown in Fig. 4, and the basic voltage level can be set to 1 volt. After that, when the first demodulation signal is input by the first charging and discharging circuit, the first demodulation signal is output by the first charging and discharging circuit. The waveform of the first demodulation signal is shown in Figure 5. After that, when the second demodulation signal is input from the peak-to-peak detector 106, the peak-to-peak detector 106 outputs a completed demodulation signal to complete the signal de-mutation operation. The waveform of the demodulated signal is shown in Figure 5. Please refer to FIG. 2, which illustrates a block diagram of a circuit according to a preferred embodiment of the present invention. Fig. 2 shows a block circuit diagram of the energy detector 108 as shown in Fig. 1. The zero detector 108 is coupled to the first charging and discharging circuit with a positive signal 204 and a negative signal 206. Observing the original modulation signal in Figure 1, we can see that the signal's performance is in the form of different density. The degree of density is the included data, that is, the degree of density is the energy density on the time axis. In other words, if the energy of the signal can be divided, the data can be demodulated. When the original modulation signal is input to the zero point detector, since the basic voltage level is set to 1 volt, the waveform greater than 1 volt in the original modulation signal will produce a high voltage level. 10338twf.doc / 008 7 584989 square wave . In contrast, the waveform of less than 1 volt in the original modulation signal will generate a square wave with a low voltage level. It can be known from the above description that the first modulation signal output by the zero-point detector 108 is a square wave with a different frequency. Then, the square wave of the high voltage level in the first modulation signal is converted into a positive signal, and the square wave of the low voltage level is converted into a negative signal. Among them, the forward signal controls the switch 208 and charges the capacitor 212. Similarly, the negative signal controls the switch 210 and discharges the capacitor 212. After that, when the first charging and discharging circuit performs a series of charging and discharging operations, it outputs a second demodulated signal as shown in FIG. 5, which is a sine wave with unequal amplitude. Furthermore, it can be known from the waveform of the second demodulated signal that the original modulated signal with a higher energy density has a shorter charging and discharging time, so the corresponding amplitude generated by the second demodulated signal is lower. Similarly, because the original modulation signal with a lower energy density takes longer to charge and discharge, the corresponding amplitude generated by the second demodulated signal is higher. Therefore, it is possible to demodulate data by using the change in amplitude. For the above reasons, the second demodulated signal is input to the peak detector 106 in order to discriminate the change in amplitude. After that, the peak-to-peak detector 106 outputs a completed demodulation signal as shown in FIG. It must be noted that the internal circuit of the energy detector is for example only. However, those skilled in the art know that this is not a necessary limitation of the present invention and can adjust the circuit design method according to the needs of the environment. Please refer to FIG. 7, which shows a block diagram of a circuit according to a preferred embodiment of the present invention. The frequency modulation analog demodulator disclosed in FIG. 7 includes an energy detector 708 and a multiplier 706. The functions and operating methods of the components in this embodiment are similar to those in the embodiment of FIG. 1 except that the first charging and discharging circuit inputs the second demodulated signal to the multiplier 706. Since the second demodulated signal is a sine wave with an amplitude (energy) that is not equal to 10338twf.doc / 008 8 584989, the signal can be demodulated after being input to the multiplier 706 together with the original modulation signal. In summary, the present invention provides a frequency modulation analog integrated circuit demodulator. Because demodulation is performed using the characteristics of signal energy density, power loss and bandwidth limitations can be reduced. Furthermore, because it is different from the conventional design method, the present invention does not need an over-sampled clock signal, and the same data rate does not need to have a relative relationship with the clock signal, so 'the use difficulty is greatly reduced. , Effectively improve the use efficiency. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. Brief Description of the Drawings Figure 1 shows a circuit block diagram of a preferred embodiment of the present invention, and Figure 2 shows a circuit block diagram of another preferred embodiment of the present invention; Figure 3 shows FIG. 4 is a signal waveform diagram of another preferred embodiment of the present invention. FIG. 4 is a signal waveform diagram of other preferred embodiments of the present invention. FIG. 5 is a signal waveform diagram of other preferred embodiments of the present invention. Waveform diagram; FIG. 6 shows a signal waveform diagram of another preferred embodiment of the present invention; and 10338twf.doc / 008 9 584989 FIG. 7 shows a circuit block diagram of a preferred embodiment of the present invention. Description of graphical symbols = 102, 702: zero point detector 104, 704: first charge / discharge circuit 106: peak detector 108, 708: energy detector 204: positive signal 206: negative signal 208 : Changeover switch 210: changeover switch 212: capacitor 706: multiplier 10 10338twf.doc / 008