TW584976B - Magnetic memory device - Google Patents

Abstract

A magnetic memory device has two TMR elements 4a and 4b, a memory cell 52 consisting of two NMOS transistors 5a and 5b, a word line connected to the gates of NMOS transistors 5a and 5b, a bit line connected to the TMR element 4a through the NMOS transistor 5a, and a sensor amplifier 53 connected to the bit line and an inverted bit line. Signals are inputted to the selected word line when the data is read out, and the sensor amplifier 53 is used to read the voltage difference between the bit line and the inverted bit line according to the signals inputted in the word line.

Description

584976 A7 B7 V. Description of the invention (i) [Technical field to which the invention belongs] The present invention relates to a magnetic memory device, especially a magnetic memory device containing a memory element representing a strong magnetic tunnel effect. [Known Technology] MRAM (Magnetic Random Access Memory) which is a non-volatile memory that uses magnetic recording data is known. For MRAM, for example, NIKKEI ELECTRONICS 1999, 11, 15 (ηο · 757) ρρ · 49 to 56 are disclosed in detail. 18 and 19 are schematic diagrams showing the structure of the MRAM memory element disclosed in the above-mentioned document. As shown in FIG. 18, the conventional MRAM memory element 110 includes a non-magnetic layer 102 provided between a ferromagnetic layer 101, a ferromagnetic layer 103, and a ferromagnetic layer 101 and 103. The ferromagnetic layer 101 is less likely to be inverted than the ferromagnetic layer 103. Here, ferromagnetism refers to the magnetism in which a magnetic atom or a free atom of a metal aligns magnetic moments in parallel due to positive exchange interactions to form a state of spontaneous magnetization, and a substance having the ferromagnetism is called ferromagnetism body. The ferromagnetic layers 101 and 103 are formed of the ferromagnetic body. It is also known that the non-magnetic layer 102 is a GMR (Giant Magneto resistance) film using metal. In recent years, TMR (Tunneling Magneto Resistance) film with useful insulators has been developed. TMR film has the advantage of greater resistance than GMR film. Specifically, the MR ratio (resistance change rate) of the GMR film is 10% degree, and the MR ratio (resistance change rate) of the TMR film is 20% or more. Hereinafter, the memory element 11o formed of a TMR film is referred to as a TMR element 11o. Next, refer to Figures 18 and 19 to illustrate the conventional use of TMR elements. 11 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297). 313122 (Please read the precautions on the back before filling this page) Economy Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperative

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V. Description of the invention (2 (please read the notes on the back before filling this page) the memory principle of MRAM. As shown in Figure 18, set the magnetization of two strong magnetic layers ι〇1 and 103 in the same direction (parallel) The state at that time corresponds to the data "0". As shown in Fig. 19, the state where the magnetizations of the two magnetic layers ιοί and 103 are in opposite directions (anti-parallel) corresponds to the data "". Here is the TMR element 110 has the property that the resistance (rg) is small when the magnetization directions are parallel, and the resistance (Ri) is large when it is anti-parallel. The use of the above-mentioned magnetization direction is parallel or anti-parallel makes the resistance of the TMR element 11 0 different to distinguish The data is OR "1". Fig. 20 is a block diagram showing the overall structure of MRAM when a memory cell is formed with a conventional TMR element and a transistor. The structure of the conventional MRAM 150 is described below with reference to Fig. 20. Memory Unit 151 is composed of a plurality of memory cells 120 arranged in a matrix form (only four memory cells 120 are shown in the simplified diagram in FIG. 20). One memory cell 120 is composed of one TMR element 11 and one The NMOS transistor 111 is formed. The gates of the NMOS transistors 111 of the memory cells 120 arranged in the row direction of the printed consumer's cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs are connected to the common word lines RWLi to RWLn for reading. One of the TMR elements 110 of each of the memory cells 120 arranged in the direction is provided with word lines WWLi to WWLn for rewriting. One of the TMR elements 110 of each of the memory cells 120 arranged in a column direction The ferromagnetic layer is connected to the common bit lines BL: to BLn. The read word lines RWL i to RWLn are connected to the column decoder 152, and each bit line is connected to the row decoder 153. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 2 313122 584976 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7_ V. Description of the invention (3) Externally designated column address and row position The address is input at the address pin 154. The column address and row address are transferred from the address terminal 154 to the address latch 155. The bit latched by the address latch 155 The address-to-bit ratio is via the address buffer 15 6 is transferred to the column decoder 152, and the row address is transferred to the row decoder 153 via the address buffer 156. The column decoder 152 selects the corresponding address latch 155 of each of the read word lines RWM to RWLn. The word line RWL for reading out the latched column address, and the word line WWL! To WWLn corresponding to the word line corresponding to the column address latched by the address latch 155 are selected. Meta Wire WWL. The column decoder 152 controls the potentials of the read word lines RWL to RWLn and the rewrite word lines wWh to WWLn in accordance with the signals from the voltage control circuit 157. The row decoder 153 selects the bit line corresponding to the row address latched by the address flash 155 in each bit line, and controls the potential of each bit line 81 ^ to BLn according to the signal of the voltage control circuit 158. The externally designated data is the input data terminal 59. This data is transferred from the data terminal 159 to the line decoder 53 via the input buffer 160. The row decoder 153 controls the potentials of the bit lines BLi to BLn corresponding to the data. The data read from any memory cell 120 is transferred from each element line BL1 to the sense decoder 153 to the sense amplifier group 161. The sense amplifier group 161 is formed by a current sense amplifier. The data judged by the sense amplifier group 16 are output to the outside by the output buffer 162 through the data terminal 159. This paper rule fiii ^ 7_CNS) A4 size ⑵〇χ 297 public love) --- 3 313122 ----------- 01-(Please read the precautions on the back before filling this page) I tt — lllllt — — — — — — — — — — — — — — — — — — — 584976 A7

___ B7 V. Description of the invention (4) The operations of the above circuits (152 to 162) are controlled by the main control circuit 163. f Jing first read the precautions on the back and then fill out this page.) The following describes the writing (rewriting) and reading operations of the conventional MR AM 150 with the above structure. (Write operation) When the write operation is performed, an orthogonal current flows to the selected word line WWL and bit line BL for replacement. In this way, it is possible to perform the rewrite only on the TMR element 11 located at the intersection of the bit line bl and the rewrite word line WWL. Specifically, a sum (combined magnetic field) of two magnetic fields generated by the respective currents flowing through the word line WWL and bit line BL generates a magnetic field (combined magnetic field) and acts on the TMR element 11. This combined magnetic field reverses the magnetization direction of the TMR element 110, for example, changes from "1" to ", 0,". As for the TMR element 110 outside the intersection, there is no current flowing at all, and only current flows in one direction. The TMR element 1 i 〇 without a current flowing through it does not generate a magnetic field, and its magnetization direction does not change. The TMR element 110 having a current flowing only in one direction is not sufficient to change its magnetization direction because the magnetic field generated is not large enough. As described above, the clothing printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is based on the bit line BL and the character line WWL corresponding to the current flowing at the selected address. The magnetization direction of the TMR element 110 at the intersection of the writing word line WWL is converted into the direction shown in FIG. 18 or FIG. 19. This allows data to be written, 〇 ,, or "1," (reading action) When you want to read out the data written as described above, the voltage applied to the reading script paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) 4 313122 584976 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (5) The RWL wire makes the NMOS transistor 丨 丨 丨 conductive. In the above state, it is determined by The current of the bit line BL is larger or smaller than the current value of the reference to determine whether the data is "1" or. At this time, as shown in the data in Fig. 丨 8, when "0", the resistance value (RG )small. That is, the current value flowing through the bit line Bl is larger than the reference current value. When the data is "1" as shown in Fig. 19, the resistance value (Ri) is larger than the state shown in Fig. 18 because the magnetization direction is anti-parallel. As a result, the current value of the bit line BL is smaller than the reference current value. [Problems to be Solved by the Invention] When the conventional MRAM 150 is used to read data, it is necessary to make the bit line a slight potential (0 · 4ν or less) to detect a current value. The reason for this is that the TMR element 110 has a characteristic that the change in resistance cannot be confirmed if the potential difference applied to both ends is not so small. Therefore, it is necessary to apply a small potential difference (less than 4V) to both ends of the TMR element 11 〇, and as a result, the current value flowing is also small. The structure of a conventional sense amplifier (amplifier) for detecting the above-mentioned minute current value is complicated and inconvenient. In order to read a small current value, the reading speed becomes slower. The present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a magnetic memory device in which the structure of a sense amplifier (amplifier) is not complicated. Another object of the present invention is to provide a magnetic memory device capable of improving the reading speed by detecting the state of the data by detecting a minute current value. Yet another object of the present invention is to make the above magnetic memory device easy to replace from a DRAM. [Means for solving the problem] This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 5 313122 (Please read the precautions on the back before filling this page) ♦ • 0 丨 order · ---- ---- Line 584976 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy — ___ _________ B7 _V. Description of the Invention (6) The magnetic memory device in the first item of the scope of patent application has: 1 memory element and second memory element, and memory cells formed by first and second transistors each connected to the first and second memory elements; word lines connected to control terminals of the first and second transistors; A bit line connected to the first memory element via the first transistor; an inverted bit line connected to the bit line of the second memory element and the bit line via the second transistor; and connected to the bit line and An amplifier that inverts the bit line, and inputs a signal to the selected word line during data reading, and uses an amplifier for the potential difference between the bit line and the inverted bit line generated by the input signal on the word line. read out. · As mentioned above, the invention according to item 1 of the scope of patent application, because two first and second memory elements and two first and second transistors with a strong magnetic tunnel effect are used to form a memory unit, and Since the potential difference between the bit lines and the inverted bit lines of the two first and second memory elements is detected by an amplifier, data can be easily read. Therefore, it is not necessary to detect the state of the minute current flowing through the bit line by the state of the memory cell and a transistor constituting the memory cell as a conventional one having a strong magnetic tunnel effect. As a result, the architecture of the amplifier is not complicated. In addition, because the potential difference between the bit line and the inverted bit line is read by an amplifier for the input signal of the word line, it is different from the state of the tiny current value flowing through the conventional read bit line, even if the memory element has high resistance. The value can also be easily read. According to the invention according to the first item of the patent application, as described above, the amplifier reads out the potential difference between the bit line and the inverted bit line as an amplifier. Therefore, the same amplifier as the conventional DRAM (sense amplifier) can be used. Simple This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 6 313122 — — — J — — — — — — — II (Please read the precautions on the back before filling this page): Order · -line I, --------------------. '584976 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 7 A7 B7___ V. Description of Invention (7) The amplifier reads the data stored in the magnetic memory device. Since it is not necessary to use a complex sense amplifier for a memory cell composed of a memory element and a transistor with a strong magnetic tunnel effect as is conventionally known, high-speed reading can be achieved. The structure and operation method of the sense amplifier and circuit are similar to those of the conventional DRAM, so the DRAM technology can be applied as it is. As a result, it is easy to replace it from the DRAM. For the magnetic memory device of the second patent application scope, for the structure of the first patent application scope, the first memory element and the second memory element each include a first magnetic layer and an insulating barrier layer and a first magnetic layer. The second magnetic layer, which is more difficult to reverse than the first magnetic layer, and further includes a second magnetic layer connected to the first memory element and a second magnetic layer connected to the second memory element, and should be applied to the character. The timing of the rising of the signal of the line pulls down the potential of the second magnetic layer of the first memory element and the second magnetic layer of the second memory element to the auxiliary word line for ground potential. According to the invention in the second item of the scope of the patent application, the auxiliary word line can be used to easily pull down the potential of the second magnetic layer of the first memory element and the second magnetic layer of the second memory element in the direction of the ground potential by setting the auxiliary word line. As a result, when the potential of the second magnetic layer of the first memory element and the second magnetic layer of the second memory element is pulled down to the ground potential, the resistance value of the first memory element and the second memory element can be reduced. The difference causes a potential difference between the bit line and the inverted bit line. Then, the potential difference can be easily detected with an amplifier. The magnetic memory device in the scope of the patent application No. 3 is the structure of the scope of the patent application in the first or the second scope, in order to reduce the signal of the character line I paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 (Public Love) '---- 313122 (Please read the precautions on the back before filling this page) ί Order i ------- Line 1 ·-Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 8 584976

5. Description of the Invention (8) The timing is performed before the potential of the second magnetic layer of the first memory element and the second magnetic layer of the second memory element reaches the ground potential. The structure according to item 3 of the scope of patent application can prevent the potential difference between the bit line and the inverted bit line from disappearing. Since the potential difference between the bit line and the inverted bit line occurs only in the transition state, if the potential of the second magnetic layer of the first and second memory elements reaches the ground potential, the bit line and the counter of the first magnetic layer are connected The index line also becomes ground potential. As a result, the potential difference between the bit line and the inverted bit line disappears. The structure of the third item of the patent application is because the signal applied to the word line is reduced before the potential of the second magnetic and magnetic layers of the first and second memory elements reaches the ground potential. Before the potential difference between the bit lines disappears, the potential difference is detected by the amplifier. The magnetic memory device in the scope of patent application No. 4 has a structure in any of the scope of patent applications in Nos. 1 to 3, and further has a timing for falling of the signal applied to the word line, and the amplifier and the bit line are reversed. Separating transistor for bit line separation. The fourth item in the scope of the patent application is due to the above-mentioned structure. When the potential of the second magnetic layer of the first and second memory elements reaches the ground potential, the amplifier is separated from the bit line and the bit line is inverted with a transistor. Because of the separation, the potential difference between the bit line and the inverted bit line can be read by the amplifier. The magnetic shame device in the scope of patent application No. 5 has a configuration in which any of the scope of patent application scopes Nos. 1 to 3 makes the first memory element and the second memory element memorize mutually opposite data. According to the fifth aspect of the patent application, the above-mentioned structure enables data to be easily read out using the resistance difference between the first memory element and the second memory element. This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 issued) 313122 J ----- ΚΙΙΦ ------- • --Order --------- line (please first (Read the notes on the back and fill out this page) 584976 A7

V. Description of the invention (9) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 9 The magnetic memory device of the 6th scope of the patent application is more equipped with the first transistor connection for the composition of the first or second scope of the patent application. A dummy bit line on the first memory element, and a detection circuit for detecting a falling timing of the dummy bit line. Due to the above structure, the virtual bit line and the detection circuit can be used to detect the falling timing of the bit line due to the above-mentioned constitution. By using the obtained timing, the amplifier can easily read the stored data by measuring the potential difference between the bit line and the inverted bit line. The magnetic memory device with the scope of patent application No. 7 is based on the structure of No. 6 of the scope of the applied specialty, and further has a timing for the virtual bit line falling obtained by the detection circuit to separate the amplifier from the bit line and the inverted bit line. The transistor for separation is activated by the falling timing of the virtual bit line obtained by the detection circuit. Due to the above-mentioned configuration, the potential difference between the bit line and the inverted bit line is easily read by the amplifier due to the above-mentioned configuration. The magnetic memory device of claim 8 of the patent scope has a constitution of the patent application scope of 6 or 7, and the detection circuit includes an input voltage as the first transistor applied to the gate and a reference voltage as the gate applied. The second transistor ′ of the electrode makes the current flowing through the first transistor larger than the current flowing through the second transistor and outputs an L (low) potential when the input voltage is equal to the reference voltage. Because of the above structure, the scope of patent application No. 8 can effectively prevent the output from becoming unstable when the input voltage is the same as the reference voltage. The magnetic memory device in the ninth scope of the patent application includes a second magnetic layer including a first magnetic layer and a first insulating barrier layer interposed on the surface of the first magnetic layer, and one surface of the first magnetic layer facing the first magnetic layer, and 2 The other paper size of the magnetic layer is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 313122 __________0i_____ 丨 Order; _______ Line > (Please read the precautions on the back before filling this page) 584976 A7

V. Description of the invention (10) A memory element with a strong magnetic tunneling effect on a third magnetic layer (opposite to the back of the page before reading this page) with a second insulating barrier layer facing one side, and Each of the memory cells formed by the first magnetic layer and the third magnetic layer of the memory element and the second transistor and the second transistor are connected to the word lines of the control terminals of the first and second transistors; via The first transistor is connected to the bit line of the first magnetic layer; the inverted bit line that is connected to the bit line by the third transistor and the bit line through the second transistor; and connected to the bit line And inverting bit line amplifiers. When data is read, a signal is input to the selected word line, and the potential difference between the bit line and the inverted bit line is read out using an amplifier according to the signal of the input word line. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs according to item 9 of the scope of the patent application, as described above, the memory element and the j-th and The crystal constitutes a memory unit, and an amplifier detects the potential difference between the bit line and the inverted bit line connected to the first and third magnetic layers using an amplifier, so that data can be easily read. Therefore, it is not necessary to detect the minute current value flowing through the bit line by using a state in which a memory element and a transistor having a strong magnetic tracking effect form a memory cell. As a result, the configuration of the amplifier is not complicated. In addition, the potential difference between the bit line and the inverted bit line caused by the input signal on the word line is read by an amplifier, which is different from the conventional state of reading the small current value flowing through the bit line. It is also easy to detect the state where the memory element has a high resistance. The invention of the 9th aspect of the patent application also uses a memory element containing one of the ferromagnetic tunneling effects of the first, second, and third magnetic layers and two first and second transistors to form a memory unit. The paper size of the two memory elements is applicable to the Chinese National Standard (CNS) A4 specification (21〇X 297 mm) 313122 10 584976 A7 _______ B7 _____ V. Description of the invention (11) and the state performance of the two transistors forming the memory cell Reduce the area of the memory unit. (Please read the precautions on the back before filling this page.) According to item 9 of the scope of patent application, the structure of detecting the potential difference between the bit line and the inverted bit line by the amplifier is described above, so it can be used in conventional DRAM. The amplifier used reads the data stored in the magnetic memory device. Therefore, it is not necessary to use a memory element having a strong magnetic tunnel effect and a transistor to form a memory cell as is conventionally required, and a complicatedly constructed sensing amplifier 'can be used to achieve a high-speed reading operation. Because the structure, circuit structure and operation method of the sense amplifier are similar to the conventional DRAM, the DRAM technology can be used as it is. As a result, the self-DRAM can be easily replaced. The magnetic memory device with the scope of patent application No. 10 is composed of the scope of the patent application scope with No. 7, and the magnetic layer includes a sidewall formed on one side of one of the second magnetic layers through the first insulating barrier layer ( A first magnetic layer having a side wall shape, and the third magnetic layer includes a third magnetic layer having a side wall shape formed on the other side of the second magnetic layer via a second insulating barrier layer. Due to the above-mentioned structure of the scope of patent application, it is easy to form a memory device composed of the first magnetic layer, the second magnetic layer, and the third magnetic layer. . The magnetic memory device with the scope of patent application No. 11 is composed of the scope of the patent application scope with No. 10, and the side wall-shaped magnetic layer and the third magnetic layer are covered with the insulating barrier material layer to cover the second magnetic layer. After the magnetic material layer is formed, it is subjected to square etching to form a magnetic material layer. The 11th item in the scope of the patent application is easy to form the i-th magnetic layer because of the above-mentioned structure, which can be formed using the same process as the conventional side wall forming process. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Love) 11 313122 584976 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs --------- -B7 ______ V. Description of the Invention (12) A memory element composed of the second magnetic layer and the third magnetic layer. The magnetic memory device with the scope of patent application No. 12 has a structure of any one of the patent application scopes Nos. 9 to π, and the second magnetic layer of the memory element is formed more easily than the first magnetic layer and the third magnetic layer. And a supplementary word line that pulls down the potential of the second magnetic layer of the memory element to the ground potential at the rising timing of the signal to be applied to the word line. Item 12 of the scope of the patent application has the configuration described above, and the potential of the second magnetic layer of the memory element can be easily pulled down to the ground potential by providing an auxiliary word line. When the potential of the second magnetic layer of the memory element is pulled down to the ground potential, a potential difference occurs between the bit line and the inverted bit line due to the difference in the resistance value of the memory element. The amplifier detects the potential difference to easily detect the stored data. The magnetic memory device in the thirteenth aspect of the patent application has a structure in which any one of the nineth to thirteenth aspects of the patent application is enclosed, and the potential of the second magnetic layer of the memory element is set with the falling timing of the signal to the word line. Before reaching ground potential. The above configuration according to item 13 of the scope of patent application can prevent the potential difference between the bit line and the inverted bit line from disappearing. The potential difference between the bit line and the inverted bit line occurs only in the transition state. Therefore, if the potential of the second magnetic layer of the memory element becomes the ground potential, the bit line connected to the first magnetic layer and the third magnetic layer and The inverted bit line also becomes a ground potential. As a result, the potential difference between the bit line and the inverted bit line disappears. In the structure of the patent application No. 13, since the signal to the word line is lowered before the potential of the second magnetic layer of the memory element reaches the ground potential, it is possible to reduce the potential difference between the bit line and the inverted bit line before the potential difference disappears. The amplifier detects it.

12 313122 (Please read the precautions on the back before filling out this page) 0 I 丨 Order: -I line < 584976 A7 V. Description of the invention (13 The magnetic memory device of item 14 of the patent application park is based on the scope of patent application The structure of any one of items 9 to 13 is further provided with a separation transistor that separates the amplifier from the bit line and the inverted bit line according to the falling timing of the signal applied to the word line. The scope of application for patent No. 14 With the configuration described above, before the potential of the second magnetic layer of the memory element reaches the ground potential, the amplifier is separated from the bit line and the inverted bit line by the separation transistor, so that the bit line and the bit line can be read by the amplifier. The potential difference between the bit lines is reversed. The magnetic memory device in the scope of patent application No. 15 is composed of any of the patent application scopes in Nos. 9 to 14, and the first magnetic layer and the third magnetic layer are stored in the magnetic memory device. The 16th item in the scope of the patent application is composed as described above, and the difference in resistance between the resistances of the first magnetic layer and the second magnetic layer and the resistance of the third magnetic layer and the second magnetic layer can be easily used to read out the data. Memory data. Patent application The magnetic memory device of item 17 includes a second magnetic layer including a first magnetic layer and a first insulating barrier layer interposed on the surface of the first magnetic layer. A memory element having a strong magnetic tunnel effect of the third magnetic layer disposed opposite to the other surface with a second insulating barrier layer interposed therebetween; and the first magnetic layer and the first and third magnetic layers each connected to the memory element A memory cell formed by a second transistor. Item 17 of the scope of the patent application consists of one memory element with a strong magnetic tunneling effect including the first, second, and third magnetic layers as described above, and two first and second memory cells. The second transistor constitutes a memory unit. Comparing two memory elements and two transistors to form a memory unit, the area of the memory unit can be reduced. This paper size applies to the Chinese National Standard (CNS) A4 (210 X 297) (Mm) 313122! .---------_ ί (Please read the notes on the back before filling out this page) J Order · ί · Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 13 584976 A7 B7 5 Description of the invention (14) [Embodiments of the invention] The following describes the embodiment of the present invention with reference to the drawings. (Please read the precautions on the back before filling out this page.) First Embodiment The first diagram is a block diagram showing the overall structure of the MRAM according to the first embodiment of the present invention. Fig. 2 shows a circuit diagram of a memory cell unit and a sense amplifier unit of the MRAM of the first embodiment shown in Fig. 1. Fig. 3 is an operation waveform diagram illustrating the read operation of the MRAM shown in Figs. 1 and 2. First, the overall configuration of the MRAM of the first embodiment will be described with reference to FIGS. 1 and 2. The MRAM of the first embodiment has the same structure as a conventional ORAM except for a memory cell array. The MRAM of the first embodiment is structured around a matrix-shaped memory cell array 51. The memory unit descending 51 is composed of a memory unit (52) arranged in a row direction and a column direction. The memory unit 52 stores one-bit data in the smallest unit of memory. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. A memory unit 52 in the MRAM of the first embodiment is composed of two TMR elements 4a and 4b, and two NMOS transistors 5a and 5b. As shown in Fig. 2, the TMR element 4a includes a ferromagnetic layer 3a, an insulating barrier layer 2a, and a ferromagnetic layer 1a which is harder to reverse than the ferromagnetic layer 3a. The TMR element 4b includes a ferromagnetic layer 3b, an insulating barrier layer 2b, and a ferromagnetic layer 1b that is less likely to be reversed than the ferromagnetic layer 3b. The gates of the two NMOS transistors 5a and 5b are connected to the word line WL. The TMR element 4a represents an example of the "first memory element having a strong magnetic tunneling effect" of the present invention, and the TMR element 4b represents an example of the "second memory element having a strong magnetic tracking effect" of the present invention. Strong magnetic layer 3a, 3b This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 14 313122

Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 15 584976 5. The invention description (l5) indicates an example of the" first magnetic layer "of the present invention, and the ferromagnetic layers Ia and lb represent the" second magnetic layer "of the present invention An example. In addition, the NMOS transistor 5a and 5b each represent the rth of the present invention! "Transistor" and "second transistor". And two NMOS transistors 5 & and 讣 's gates are examples of the "control terminal" of the present invention. In the memory cell array 51, the memory cells 52 arranged in the column direction (the vertical direction in the figure!) Are connected to the character line WL and the auxiliary character line SWL. The memory cells 52 arranged in the row direction (the horizontal direction in the figure!) Are connected to the bit line bL and the inverted bit line / BL. The inverted bit line / BL and the corresponding bit line BL constitute a set of bit line pairs. Each element line pair BL, / BL is connected to each sense amplifier (SA) 53 in the form of a cross couple latch. The signal potentials of each bit line pair BL, the bit line BL of / BL and the inverted bit line / BL are complementary changes. NMOS transistors 8a and 8b are provided between each element line pair BL, / BL and each sense amplifier (sa) 53 to separate each element line pair BL, / BL and each sense amplifier (SA) 53. . The gates of the NMOS transistors 8a and 8b are connected to the signal line 03. The NMOS transistors 8a and 8b show an example of the "separation transistor" in the present invention. The sense amplifier 53 is an example of the "amplifier" of the present invention. Each word line WL is connected to the column decoder 54. When the column address RA is input from the outside, the column address ra is supplied to the column decoder 54 via the column address buffer 55. The column decoder 54 selects the word line WL corresponding to the column address ra accordingly. Each word line WL is composed of NMOS transistor 6 and PMOS transistor. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 313122 • m 0 1 ---.------ -. Awi ----- j t_i ------- (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 16 584976 A7 B7 V. Description of the invention ( 16) The inverter circuit of the body 7 is connected to one of the terminals of the auxiliary word line SWL ·. The other terminal of the auxiliary word line SWL is connected to Vcc via a PMOS transistor 9. The gate of the PMOS transistor 9 is connected to the signal line 4 4. The word line WL is connected to one of the input terminals of the AND circuit 11 and is connected to the output terminal of the AND circuit 11. The other input terminal of the AND circuit 11 is connected to a signal line 0 which is always 0 (L potential) when writing. NMOS transistors 10a and 10b are connected to the bit line BL and the inverted bit line / BL, respectively. The gates of the NMOS transistors 10a and 10b are connected to the signal line 05. The terminals of one of the NMOS transistors 10a and 10b are connected to each other. The NMOS transistors 10a and 10b connected to each other are connected to precharge the circuit 67. Each sense amplifier 53 is connected to an input / output line I / O and an inverted input / output line / 1/0 via respective transfer gates 56. Input and output I / O and inversion Input and output / 1/0 constitute the input and output pair I / O and / 1/0. The input / output pair I / O and / 1/0 are connected to a read amplifier 57. The sense amplifier 57 is connected to a data output circuit 58 via a data bus DB and an inverted data bus / DB. The data bus DB and the inverted data bus / DB constitute the data bus to DB, / DB. The input / output pair I / O and / 1/0 are connected to the precharge circuit 59. In addition, the potentials of the input / output I / O and the reverse input / output / 1/0 are complementary changes. The potentials of the data bus DB and the inverted data bus / DB are also complementary changes. The output circuit 58 outputs the data to the outside. Each pass gate 56 is connected to a column decoder via a column selection line CSL. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 313122 --------------- ------ " " 7 Order -------- M — ^ wi < Please read the notes on the back before filling in this page) 584976 Α7 ---------- B7 V. Description of Invention (17) (Please read the notes on the back before filling this page) 60. Each transfer gate 56 is composed of a pair of NMOS transistors connected between the input / output pair 1/0, / 1/0, and the sense amplifier 53. The gates of the pair of NMOS transistors are connected to the row decoder 60 via a column selection line CSL. Therefore, when the row selection line CSL becomes η (high) potential, a pair of NMOS transistors are turned on, and the transfer gate 56 is turned on. When the row address CA is input from the outside, the column address CA is supplied by the row address buffer 61 to the row decoder 60 and an address transition detection circuit (ATD: Address Transition Detector) 62. The ATD62 detects the column address CA. The change of the line is detected by the external input of the row address CA, and a pulse signal ATD1 of 1 pulse is generated. That is, the pulse signal ATD1 is generated every time the row address CA changes. This pulse signal ATD1 is output to the line decoder control circuit 63, the precharge control circuit 64, and the sense amplifier control circuit 65. _ Line · The precharge control circuit 64 generates a precharge circuit activation signal PC that becomes one of the high voltages at a preset time according to the pulse signal ATD1 falling from the Η potential to the L potential. The activation signal PC is output to a precharge circuit 59. The pre-charge circuit 59 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs will make the input / output pair I / O, / 1/0 the same potential, and pre-charge to a predetermined potential (for example, 1 / 2Vcc ·· Vcc is the driving voltage of MRAM). The precharge circuit 59 becomes inactive (activated standby state) when the activation signal PC becomes L potential, and stops precharging the input / output pair I / O, / 1/0. The line decoder control circuit 63 generates a pulse with a predetermined time to become one of the pseudo-potentials according to the pulse signal ATD1 falling from the pseudo-potential to the L-potential. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 17 313122 584976 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. The row decoder activation signal YS of the invention description (18). The activation signal YS is output to the line decoder 60. The row decoder 60 becomes activated when the activation signal Y S is input, and selects a row (a pair of bit line pairs BL, / BL) of the memory array 51 corresponding to the row address CA input from the outside. That is, the row decoder 60 becomes activated when the activation signal YS is input. When the row decoder 60 is activated, the row selection line CSL corresponding to the row address CA input from the outside is selected, and the row selection line CSL is set to a pseudo potential. As a result, the transfer gate 56 connected to the row selection line CSL is turned on. Then, through the sense amplifier 53 corresponding to the transfer gate 56, a column of the memory cell array 51 corresponding to the row address CA input from the outside is selected. The sense amplifier control circuit 65 generates a sense amplifier activation signal READ that is one pulse delayed from the pulse signal ATD1 by a predetermined time based on the pulse signal ATD1 falling from the Η potential to the L potential. The timing and pulse width of the activation signal READ are preset. The activation signal read is output to the read amplifier 57. The delay time of the activation signal READ is a time for the potential difference between the input / output pair I / O and / 1/0 to become a sufficient potential difference for data reading. That is, according to the data setting read by the memory unit 52, the state that the sense amplifier 57 does not misread is changed from the input / output pair 1/0, / 1/0 from the precharged potential standby to a change to a sufficient potential difference. time. That is, each of the control circuits 63 to 65 is provided with a delay circuit that receives the pulse signal ATD1 from the η potential to the L potential to generate an activation signal YS, PC, and READ at an appropriate timing and pulse amplitude, and a pulse-generating electronic paper. The standard has been used in China's National Standard (CNS) A4 specification 〇〇297 297 public love) 18 313122 (Please read the precautions on the back before filling out this page) # -I 定 · ί-Line · Intellectual Property Bureau of the Ministry of Economic Affairs employee consumption Printed by the cooperative 19 584976 Α7 _ B7 V. Description of the invention (19) Road 0 is also provided with a readout detection circuit 66 for detecting the potential difference between the data bus line pair DB and / DB and generating a readout detection signal READ according to the detection result. Therefore, when the potential of the data bus line pair DB, / DB reaches a predetermined potential difference or more, the data read by the memory unit 52 is determined and output to the outside. Therefore, the detection data output (readout operation) can be performed from the potential difference between the detection data bus line pair DB and / DB. Then, the readout detection circuit 66 detects the readout operation based on the potential difference between DB and / DB of the data bus line, and generates a readout detection signal READ of the pseudo-potential based on the detection result. This detection signal READ is output to the line decoder control circuit 63, the precharge control circuit 64, and the sense amplifier 65. Fig. 4 is a partial cross-sectional structure diagram of the memory unit of the first embodiment shown in Figs. The cross-sectional structure of the memory unit 52 according to the i-th embodiment will be described below with reference to FIG. 4. A predetermined area on the surface of the substrate 71 of the memory unit 52 of the first embodiment forms a separation area 72. The element formation area surrounded by the separation area 72 forms an n-type source / drain area 73 at predetermined intervals. Gates constituting the word lines WL1 and WL2 are formed in a channel area between the adjacent N-type source / drain areas 73. This gate and a pair of N-type source / drain regions constitute an NMQS transistor 5a. The N-type source / drain region 73 located at both ends is connected to the ferromagnetic layer 3a of the TMR 70 component 4a via the conductive layers 74 and 75. The ferromagnetic layer is easily reversed, and as shown in Fig. 4, the direction of the data changes. On the other side of the ferromagnetic layer 3a is ^ formed by the insulating barrier layer 2a than the ferromagnetic layer 3a. This paper has been oversized using the Chinese National Standard 297. 313122 (Please read the precautions on the back before filling this page) Order 1.1 i. 584976 Α7 ——B7 V. Description of the invention (20) The ferromagnetic layer la which is not easily reversed. The ferromagnetic layer 1a should not be fixed in one direction when the data is inverted. The ferromagnetic layer 1a is connected to the auxiliary word lines SWL1 and SWL2 via a conductive layer 77. The central N-type source / drain region 73 is connected to the bit line BL via a conductive layer 76. An interlayer insulating film 78 is formed between the bit line BL and the substrate 71. The memory unit 52 of the MRAM according to the first embodiment of the circuit configuration shown in Figs. 1 and 2 can be easily realized by using the memory unit having the above-mentioned cross-sectional structure. Next, the writing and reading operations of the MRAM structured as described above will be described. (Write operation) The following describes the write operation for the state where the memory cell 52 connected to the word line WL1 is being written. When data is written in the MRAM according to the first embodiment, the signal line 06 is first set to the L potential. As a result, an L potential is input to the other terminal of the AND circuit 11. At this time, the character line WL1 of one of the input terminals of the input AND circuit 11 is at a pseudo potential due to the character line selected by the series decoder 54. Therefore, a portion of the output of the AND circuit 11 of the selected word line WL1 is L potential. As described above, since the signal line 06 is at the L potential, the word line WL1 connected to the output of the AND circuit 11 is forced to the L potential. As a result, the NMOS transistors 5a and 5b connected to the word line WL1 connected to the output terminal of the AND circuit 11 are turned off. Next, the signal line 04 is lowered to the L potential and the PMOS transistor 9 is turned on. At this time, the word line WL1 connected to the SWL1 via the inverter is at a pseudo potential, so the NMOS transistor 6 constituting the inverter is in an on state. Therefore, the paper size of SWL1 is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 313122 (Please read the precautions on the back before filling this page) Φ '---------- --Line Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 20 584976 A7 " " " " " " ------- 2Z --------------- ------ V. Description of the invention (21) The lower part is the ground potential. Since the upper part of SWL1 is lowered, the PMOS transistor 9 is turned on to Vcc potential, and SWL1 flows current from top to bottom. Next, use the input and output line pairs I / O, /; [/ 〇 to make the selected bit bit line Bl and the inverted bit το line / BL each be a Η potential and an L potential. In addition, the signal line 0 5 is raised to a Η potential, and the NMOS transistor i0a and 10b are turned on. As a result, the bit line BL is short-circuited with the corresponding inverted bit line / BL, and a current flows from the bit line BL in the η potential state to the inverted bit line / B1 in the L potential state. That is, a current in the left direction flows through the bit line BL and a current in the right direction flows through the inverted bit line / BL. When the bit line BL and the inverted bit line / BL want to flow a current in a direction opposite to the above, a signal of an L potential is applied to the bit line BL and a signal of a pseudo potential is applied to the inverted bit line / BL. As described above, the auxiliary word line Swl1 of the selected memory cell flows a current from top to bottom, and the bit line pair BL, / BL passes opposite currents to the selected memory cell TMR element. The ferromagnetic layer 3a of 4a and the ferromagnetic layer 3b of the TMR element 4b easily write the opposite data (for example, "1" and, 0 ,,). Another example is to write the opposite data to the ferromagnetic layer 3a of the TMR element 4a and the ferromagnetic layer 3b of the TMR element 4b (for example, 0, and "factory"), and then circulate BL and / BL. The direction of the current can be reversed. For unselected memory cells, data is not rewritten because the auxiliary word line SWL has no current flow. (Reading action) This paper size applies the Chinese National Standard (CNS) A4 specification. (210 X 297 Public Love) 313122 (Please read the notes on the back before filling out this page) -1 --- I— Order -------- • Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 21 584976 A7 B7 __ V. Description of the invention (22) As mentioned above, when the data is written, the ferromagnetic layer 3a connected to the bit line TMR element 4a and the TMR element connected to the inverted bit line / bl The ferromagnetic layer of 4b complements the data written in the opposite magnetic field. The read operation when the memory cell 52 connected to the word line wu is selected is described below with reference to FIG. 2. First, before the word το line WL1 rises, the word The element line WL1 is in the state of the B potential. At this time, since the word line WL1 is connected to the opposite side The transistor PMOS transistor 7 is on, so the auxiliary word line swu is at the Vcc potential. As a result, the potential of the node a is also Vcc. Since the TMR elements 4a and 4b are conductors, the TMr element 4a and the flutter potential It also becomes Vcc. In this state, 05 is raised to a pseudo potential, and the bit line BL and the inverted bit line / BL are precharged to Vcc by the precharge circuit 67. When the word line WL1 rises, the word line WL1 is set to the Η potential by the row decoder 54, so the NMOS transistors 5a and 5b connected to the word line WL1 are turned on. As a result, the bit line BL and the inverted bit line / BL, and the tMr elements 4a and 4b In this state, the potential of the bit line bl, the inverted bit line / BL, and the node a is vcc. When the word line WL1 rises to a Η potential, 05 becomes the L potential, and the precharge circuit is cut off. 67, and the NMOS transistor 6 connected to the inverter circuit of the word line WL1 is turned on, so the potential of the auxiliary word line SWL1 is slowly pulled down to the GND potential, and the potential of the node a is also slowly pulled Down to GND potential. The potentials of bit line BL and inverted bit line / BL are also slowly pulled down to GND potential The TMR element 4a connected to the bit line BL side here is the ferromagnetic layer 3a and la on the upper and lower layers due to the direction of the magnetic field. This paper size applies the Chinese National Standard (CNS) A4 specification (21〇 × 297 mm) 313122 C Please read the notes on the back before filling in this page.) 订 ί ί · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 22 584976 A7 -------- Β7__ V. Description of Invention (23) Mutual On the contrary, therefore, the resistance of the TMR element 4b connected to the inverted bit line / BL is higher. (Please read the precautions on the back before filling in this page.) At the timing when the potentials of bit line BL and inverted bit line / BL start to pull to GND, due to bit line BL and inverted bit line, and Since the node a has only a small potential difference, its MR ratio (resistance change rate) is at its maximum. As the potential of the node a decreases, the potentials of the bit line BL and the inverted bit line / BL also decrease. At this time, since the resistance of the tmr element on the bit line BL side is slightly higher, the potential drop is slower than that of the inverted bit line / BL. As a result, a potential difference is generated between the bit line BL and the inverted bit line / BL. As shown in Fig. 3, at the timing when the potential difference occurs, the word line is lowered from the η potential to the L potential. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The above-mentioned timing of falling of the character line WL1 is implemented before the potential of the node & reaches the GND potential. The reason is as follows. Since the potential difference between the bit line bl and the inverted bit line / BL occurs only in the transition state, if the potentials of the ferromagnetic layers la and lb (potential of node a) of the tmr elements 4a and 4b become the GND potential, then each connection The bit lines and inverted bit lines / BL on the ferromagnetic layers 3a and 3b also become the GND potential. In this way, the potential difference between the bit line BL and the inverted bit line / BL disappears and cannot be detected. In the transition timing, although a potential difference occurs between the bit line BL and the inverted bit line / BL, since the TMR elements 4a and 4b are conductors, the bit line BL and the inverted bit line / BL finally become the same Potential. This causes the signal line 0 3 to fall in response to the falling timing of the word line WL1. As a result, the NMOs transistor (separation transistor) 83 and 8b are turned off, so that the paper size of bit line I applies the Chinese National Standard (CNS) A4 specification (210 X 297). ---- 23 313122 584976 A7 __ B7 V. Description of the invention (24) BL and the inverted bit line / BL are separated from the sense amplifier 53. Thereafter, the sense amplifier 53 is activated by the rises of 0 1 and 0 2. The potential difference between the bit line BL on the sense amplifier 53 side and the inverted bit line / BL on the sense amplifier 53 side is amplified and divided into Vcc and GND. The data reading operation is completed as described above. At the falling timing of the signal line 03, 05 is increased, and the precharge circuit 67 is turned on to precharge the bit line BL and the inverted bit line / BL to Vcc. In the first embodiment, as described above, the two TMR elements 4a and 4b and the two NMOS transistors 5a and 5b constitute a memory cell 52, and the bit line BL and the inverted bit connecting the two TMR elements 4a and 4b are connected. The potential difference between the element line / BL is detected by the sense amplifier 53, so that data can be easily read. Since the potential difference is detected according to the method described above, it is not necessary to detect the value of the microcurrent flowing through the bit line in a state where a memory cell is composed of a TMR element and an NMOS transistor. As a result, it is possible to avoid the trouble of having a complicated sense amplifier for detecting a small current value. According to the first embodiment, since the potential difference between the bit line BL and the inverted bit line / BL is detected by the sense amplifier 53 as described above, a simple sense amplifier 53 similar to that of a conventional DRAM can be used. To read the data stored in MRAM. As described above, since a simple sense amplifier 53 can be used to read data, a high-speed reading operation can be performed by using a relatively complicated sense amplifier.

According to the MRAM of the first embodiment, the configuration of the sense amplifier 53 and the overall circuit configuration and operation method are similar to those of the conventional DRAM. Therefore, the DRAM technology can be used as it is. As a result, it is easy to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) from the DRAM paper size. 313122 (Please read the precautions on the back before filling this page) ------- " T- ------ Line-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 24 584976 A7 B7 V. Description of Invention (25) Replacement. 12th Embodiment Fig. 5 is a block diagram showing the structure of a full skeleton of an MRAM according to a second embodiment of the present invention. Fig. 6 shows a circuit diagram of the MRAM memory cell unit and the sense amplifier unit of the second embodiment of Fig. 5. Fig. 7 is a circuit diagram showing the internal configuration of a comparer section of the MRAM of the second embodiment of Figs. 5 and 6. Referring to Figs. 5 and 6, the MRAM of the second embodiment differs from the MRAM of the first embodiment shown in Figs. 1 and 2 in that a dummy bit line (virtual BL) is provided, and a detection is provided. Comparator 201 for the potential of the virtual bit line. The comparator 201 shows an example of the "detection circuit" of the present invention. This is explained in detail below. As shown in FIGS. 5 and 6, in the second embodiment, a dummy bit line (virtual BL) having the same configuration as the bit line BL is provided. That is, the dummy bit line is connected to the TMR element 4a via the electric crystal 5a. All the TMR elements 4a connected to the virtual bit line are set so that the magnetization directions of the ferromagnetic layers 1a and 3a are the same (parallel). Then, the virtual bit line is connected to one input terminal of the comparator 201. The other input terminal of the comparator 201 is connected to Vcc (reference voltage). The output of the comparator 201 is connected to the inverter 202, and the output of the inverter 202 is connected to the inverter 203. The output of the inverter 202 is used as the signal 0 1, and the output of the inverter 203 is used as the signal 02. The signals 01 and 02 are used as activation signals of the sense amplifier 53. As shown in Fig. 7, the comparator 201 contains a pair of pMOS transistors 213 and 214, and the input voltage (the voltage of the virtual bit line) vin is applied to its gate. The paper size is applicable to the Chinese National Standard (CNS) A4. Specifications (210 X 297 mm) 313122 (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs * Order 0.0.I -------- line-- ---------------------- 25 584976 A7 B7 V. Description of the invention (26) NMOS transistor 211, Vcc is applied to its gate NMOS transistor 212. The NMOS transistor 211 shows an example of the "i-th transistor" of the present invention, and the NMOS transistor 212 shows an example of the "second transistor" of the present invention. One terminal of the NMOS transistor 211 and 212 is connected to the constant current source 215, and one terminal of the PMOS transistor 213 and 214 is connected to vcc. An output voltage Vout is output from a connection point between the other terminal of the PMOS transistor 213 and the other terminal of the NMOS transistor 211. The comparator 201 according to the second embodiment shown in Fig. 7 is configured so that the amount of current flowing through the NMOS transistor 211 to which Vin is applied is larger than the amount of current flowing through the NMOS transistor 212 to which Vcc is applied. Specifically, the gate width of the NMOS transistor 211 is made larger than that of the NMOS transistor 212, so that the amount of current flowing through the NMOS transistor 211 is larger than the amount of current flowing through the NMOS transistor 212. Without changing the gate width, forming the gate length of the NMOS transistor 211 to be longer and longer than the gate of the NMOS transistor 212 can also make the amount of current flowing in the NMOS transistor 211 more than the current flowing in the NMOS transistor 212 The amount is large. As described above, the current amount of the NMOS transistor 21 applied with Vin is larger than the current amount of the NMOS transistor 212 applied with Vcc. Therefore, even when Vin is Vcc equal to the reference voltage Vcc, an L potential signal can be output. Output voltage Vout. Because of this, when the input voltage Vin of the comparator 201 is Vcc, the instability of the comparator 201 can also be prevented. That is, the comparator 201 of the second embodiment outputs a signal of the L potential when Vin is the same as the reference voltage Vcc, and outputs a signal of the pseudo potential when Vin is lower than the reference voltage. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 313122 (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

; 0 ------- Jtri -------, ♦ -------------------- II 26 584976 A7 V. Description of the invention (27) In the second embodiment, as shown in FIGS. 5 and 6, the signal 07 and the output of the column decoder output 60 are input to the AND circuit 205. The output of the AND circuit 205 is connected to the gate of the transistor 204 which connects the bit line BL and the inverted bit line / BL. Due to the above configuration, it is easy to short only the selected bit line BL and the corresponding inverted bit line / BL. Next, the read and write operations of the MRAM according to the second embodiment configured as described above will be described. (Read operation) Fig. 8 is a conceptual diagram showing an operation waveform of a read operation of the MRAM according to the second embodiment of the present invention. Figures 9 and 10 show the operation waveform simulation diagrams of the MRAM read operation in the second embodiment. In the second embodiment, a read operation is described in which the resistance of the TMR element 4a connected to the bit line BL is lower than the resistance of the TMR element 4b connected to the inverted bit line / BL. That is, as in the memory cell 52 connected to the word line WL2 shown in FIG. 6, the magnetization direction of the TMR element 4a is the same (parallel), and the magnetization direction of the TMR element 4b is the opposite (anti-parallel) read operation. . The read operation will be described below with the state of the selected word line WL2 selected. Referring to FIG. 6 ', the initial state before the word line WL2 rises is that the word line WL2 is in the L potential state. At this time, the PMOS transistor 7 of the inverter circuit connected to the word line WL2 is turned on, so the potential of the auxiliary word line sWL2 becomes Vcc. As a result, the potential of the node a also becomes Vcc. Since the TMR elements 4a and 4b are conductors, the potentials of the TMR elements 4a and 4b also become Vcc. In this state, 05 is raised to a Η potential, and the bit line BL, the inverted bit line / BL, and the dummy bit line are precharged by the precharge circuit 67. The paper size applies the Chinese National Standard (CNS) A4 specification ⑵G X (297 Gongchu) ------- '" 27 313122 (Please read the precautions on the back before filling this page)

• -ί Order -------- line -m Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 584976 A7 _______ B7 V. Description of the invention (28) becomes Vcc 〇 It rises to η potential on the character line WL2 At this time, the NMOS transistors 5a and 5b connected to the word line WL2 are turned on. As a result, the bit lines bl and the inverted bit lines / BL, the TMR elements 4a and 4b are turned on. In this state, the potentials of bit line BL, inverted bit line / bl, virtual bit line (virtual BL), point a, node b, and node c become Vcc. Before the word line WL2 rises to the Η potential, 05 becomes the L potential. The precharge circuit 67 is turned off and the NMOS transistor 6 connected to the inverter circuit of the word line WL2 is turned on. Therefore, the word line s is assisted. The potential of WL2 gradually decreases toward the GND potential. Due to this, the potential of the node a is also slowly pulled down to the GND potential. Accordingly, the potentials of the bit line bl and the inverted bit line / BL are gradually pulled down to the GND potential. Fig. 8 shows a waveform in a state where the character line WL is raised and the auxiliary character line SWL is gradually lowered. As shown in Fig. 8, the word line WL is raised and the auxiliary word line SWL is gradually lowered, and the nodes b and c (see Fig. 6) are lowered. At this time, since the resistance values of the TMR element 4a having the same magnetization direction (parallel) and the TMR element 4b having the opposite magnetization direction (anti-parallel) are different, a potential difference is generated between the node b and the node c. The bit line BL and the inverted bit line / BL on the cell side (memory / cell 52 side) begin to decrease at the potentials of the node and the node c below Vcc-Vt (threshold voltage). At this time, the potential drop of the TMR element 4a whose parallel magnetization direction is low and whose resistance is low is earlier than that of the TMR element 4b whose magnetization direction is antiparallel and whose resistance is high. At this time, the on-resistance of the transistor 5a and 5b connected to the bit line BL and the inverted bit line / BL on the cell side is dependent on the gates of the transistors 5a and 5b. The paper size applies the Chinese National Standard (CNS) A4 specification. (210 X 297 male t) 313122 (Please read the notes on the back before filling out this page) fi line 丨 Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 28 584976 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 29 A7 V. Description of the invention (29) The potential differences VgsB and VgsC of the source of the electrode (see FIG. 6). In the above state, since the potentials of the node b and the node C are different, VgsB of the transistor & is different from VgsC of the transistor 5b. As a result, the transistor 5a connected to the TMR element 4a having a lower resistance (parallel) has a large Vgs and a low resistance. Therefore, the potential difference between the bit line BL on the cell side and the inverted bit line / BL is larger than the potential difference between the node b and the node 0. Similarly, the potential difference (Vsig) between the bit line bl on the sense amplifier side and the inverted bit line / BL will be larger because of the Vgs of the 1 ^] ^ 8 transistors 8a and 8b used for separation. However, since the bit line BL and the inverted bit line / BL wiring capacity on the sense amplifier side are smaller than the bit line BL and the inverted bit line / BL on the cell side, the wiring capacity is smaller. The bit line Bl and the inverted bit line / BL on the amplifier side will be at the same potential as the bit line BL and the inverted bit line / BL on the cell side. Because of this, the timing at which the bit line and the inverted bit line on the sense amplifier side starts to drop from Vcc to the timing at which the bit line and the inverted bit line on the cell side become the same potential can obtain input to the sense amplifier 53 The time when the potential difference between both ends is large. In the first embodiment described above, the sense amplifier 53 starts detection at any timing when the bit line BL and the inverted bit line / BL on the cell side become 0V. In this way, the timing with better detection efficiency may be lost. However, according to the second embodiment, the timing of the falling of the bit line BL on the sense amplifier side is detected because a comparator 201 for detecting the virtual bit line (virtual BL) and the potential of the virtual bit line is provided. Then, the bit line and the inverted bit line on the cell side are separated from the bit line and the inverted bit line on the sense amplifier side according to the timing, and the sense amplifier 53 is operated. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 313122 (Please read the precautions on the back before filling this page)

584976 A7

V. Description of the Invention (30) Specifically, as described above, the potential levels of the bit line BL and the inverted bit line / BL, the virtual bit line (virtual bl), and the auxiliary word line sWL2 in the initial state are Vcc. After that, the character line WL2 rises, and the auxiliary character line SWL starts to gradually decrease. This causes a potential difference between the bit line BL on the cell side and the inverted bit line / BL. When the potentials of the bit line BL and the inverted bit line / BL on the cell side reach below Vcc-Vt, as shown in FIG. 8, the bit line BL and the inverted bit line / The potential of BL starts to drop from Vcc. The potential of the virtual bit line (comparator side) also starts to decrease at this timing. At this time, the TMR element 4a connected to the virtual bit line is set to a low-resistance state in which the magnetization direction is parallel, so the virtual bit line is the one with a lower resistance than the bit line BL and the inverted bit line / BL. (Bit line BL in the second embodiment) The fall of the potential is started at the same timing. In the initial state, the input Vin of the comparator 201 connected to the dummy bit line is Vcc, which is the same as the reference voltage Vcc. According to the second embodiment, as described above, when the input Vin of the comparator 201 is at the same Vcc as the reference voltage Vcc, the signal that the output Vout is at the L potential is output. Then, when the potential of the virtual bit line (comparator side) starts to decrease from Vcc and the voltage of the virtual bit line (comparator side) is lower than Vcc, the reference voltage of comparator 201 is Vcc, so comparator 201 outputs Η Potential. By this signal, the signal 02 becomes a pseudo potential, and the signal 0 1 becomes an L potential. Thereby, the sense amplifier 53 is activated. At this timing, the signal 03 decreases. This causes the separation NMOS transistors 8a and 8b to be turned off, thereby separating the bit line and the inverted bit line on the cell side from the bit line and the inverted bit line on the sense amplifier side. Then the potentials of the bit lines and inverted bit lines on the side of the sense amplifier and this paper size apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 313122 (Please read the precautions on the back before filling in this Page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs * 榉 碧 ϋ ϋ ϋ n ϋ »^ — ^ 0, · * 1 n · ϋ« ϋ · 1 »II ϋ · .1 n — ϋ · ϋ H« I ϋ II ϋ II n ϋ an II ϋ I _ 30 584976 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

5. Description of the invention (M) The sensing of the DR AM is also amplified and read out. As for the bit line BL and the inverted bit line / BL on the cell side, they rise to the Η potential at the signal 0 5 and return to the initial state. Figures 9 and 10 show actual simulated waveforms. Fig. 9 shows the waveform of the observed bit line BL when the sense amplifier 53 has not started sensing. Fig. 10 shows waveforms when the comparator 201 is operated and the sense amplifier 53 is operated. (Write operation) The write operation of the second embodiment is basically the same as the write operation of the first embodiment described above, and a detailed description thereof is omitted here. However, according to the second embodiment, as described above, the signal 07 and the column decoder are inputted to the AND circuit 205, and the output of the AND circuit 205 is connected to the electrical circuit for connecting the bit line Bl and the inverted bit line / BL. Gate of crystal 204. Therefore, during the writing operation, it is easy to short only the selected bit line BL and its corresponding inverted bit line / BL. As described above, according to the second embodiment, the dummy bit line and the comparator 201 can be used to detect the falling timing of the bit line BL on the sense amplifier side. Then, the falling timing of the virtual bit line detected by the comparator 201 turns off the NMs transistors 8a and 8b for separation, and activates the sense amplifier 53 so that the sense amplifier 53 can easily detect the sense. The potential difference (Vsig) between the bit line on the amplifier side and the inverted bit line. (Third Embodiment) Fig. 11 is a block diagram showing the overall structure of an MRAM according to a third embodiment of the present invention. Fig. 12 shows the MRAM of the third embodiment of Fig. 11. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 31 313122 (Please read the precautions on the back before filling this page) φ! : ί. Line 丨 584976 A7 ________ B7 V. Circuit diagram of memory unit section and sense amplifier section of invention description (32). Referring to Figs. 1 and 12, the third embodiment differs from the first embodiment shown in Figs. 1 and 2 only in the memory cell portion. That is, a memory cell 82 of the MRAM of the third embodiment is composed of a double-junction TMR element 24 and two NMOS transistors 5a and 5b. The circuit configuration other than the memory cell portion of the third embodiment is the same as that of the first embodiment. As shown in FIG. 12, the double-junction TMR element 24 of the third embodiment includes a ferromagnetic layer 23a, an insulating barrier layer 22a, a ferromagnetic layer 23b, an insulating barrier layer 22b, and a specific ferromagnetic layer 23a and a ferromagnetic layer 23b. The ferromagnetic layer 21 which is harder to reverse. That is, the two surfaces of the ferromagnetic layer 21 that is not easily reversed at the center are formed with ferromagnetic layers 23a and 23b respectively through insulating barrier layers 22a and 22b. The TMR element 24 is double-bonded according to the third embodiment. The ferromagnetic layer 1a of the TMR element 4a of the first embodiment and the ferromagnetic layer 1b of the TMR element 4b are shared by a ferromagnetic layer 21 shown in FIG. Therefore, according to the third embodiment, one TMR element 24 double-bonded can have the same function as the two TMR elements 4a and 4b of the first embodiment. The above-mentioned double-junction TMR element 24 represents an example of the "memory element having a strong magnetic tunnel effect" of the present invention. The ferromagnetic layer 23a is an example of the "first magnetic layer" of the present invention, the ferromagnetic layer 21 is an example of the "second magnetic layer" of the present invention, and the ferromagnetic layer 23b is an example of the "third magnetic layer" of the present invention. An example. The insulating barrier layer 22a indicates an example of the "first insulating barrier layer" of the present invention, and the insulating barrier layer 22b indicates that the "first paper size of the present invention applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 313122" (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. I · _ ίντ ------- 线 1 # ------------ -------- 丨! 32 584976 A7 B7 V. Description of the invention (33) 2 Insulation barrier layer ". C Please read the precautions on the back before filling this page) As described above, according to the third embodiment, only the two TMR elements 4a and 4b of the first embodiment are replaced by a double-junction TMR element 24, and other circuit configurations This is the same as the first embodiment. Therefore, the write and read operations of the MRAM of the third embodiment are also the same as those of the first embodiment, and detailed descriptions thereof are omitted. As described above, according to the third embodiment, a memory cell is composed of a ferromagnetic layer 21, 23a, and 23b, a double-junction TMR element 24 including insulating barrier layers 22a, and 22b, and two NMOS transistors 5a and 5b. 82. Therefore, comparing the first embodiment in which one memory cell 52 is formed by using two TMR elements 4a and 4b and two NMOS transistors 5a and 5b, the area of the memory cell unit can be reduced. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs According to the third embodiment, the reading operation is the same as that of the first embodiment, and the same effect as that of the first embodiment can be obtained. That is, the sense amplifier 53 (see FIG. 12) detects the potential difference between the bit line BL and the inverted bit line / BL connected to a double-junction TMR element 24, and data can be easily read. Therefore, it is not necessary to detect a minute current value flowing through a bit line as in the conventional configuration of forming a memory cell with a TMR element and an NMOS transistor. As a result, it is possible to avoid a complicatedly constituted sense amplifier for detecting a minute current value. According to the third embodiment, as in the first embodiment, a configuration in which the potential difference between the bit line BL and the inverted bit line / BL is detected by the sense amplifier 53 (see FIG. 12) is used. The sense amplifier 53 used by dram reads out data using a simple sense amplifier 53. Therefore, it is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) than this paper size. 33 313122 584976 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 34 A7 B7 V. Description of the invention (34) The structure is more complicated than the conventional one When using a sense amplifier, it can be used for high-speed motion. The MRAM of the third embodiment is the same as the first embodiment. The configuration of the sense amplifier 53, the overall circuit configuration, and the operation method are similar to those of the conventional ORAM. Therefore, DRAM technology can be used as it is. As a result, replacement from DRAM is easy. Since a pulsed signal is input to the selected word line, the potential difference between the bit line and the inverted bit line is read by the sense amplifier 53 (refer to FIG. 12), and a small current is read as is conventionally known. Since the values are different, data can be easily detected even in a state where the resistance of the double-junction TMR element 24 is high. Fig. 13 is a plan layout diagram of the circuit configuration for realizing the MR AM of the third embodiment of Figs. Π and 12, and Fig. 14 shows a cross-sectional view taken along line 100-100 of Fig. 13. The structure of the memory cell 82 of the MRAM according to the third embodiment will be described below with reference to Figs. 13 and 14. The plan layout of FIG. 13 is a simplified diagram showing only the bit line bl and the inverted bit line / BL, forming the ferromagnetic layers 21, 23a, and 23b of the double junction TMR element 24, and the bit line contact portion. 94. As shown in Fig. 14, the cross section of the memory cell 82 of the MRam of the third embodiment is formed in a predetermined area on the surface of the substrate 91, and a separation area 92 is formed. The separated element formation region 92 forms an N-type source / drain region 93 at a predetermined interval from the surrounding element formation region. Gates constituting the word lines WL1 and WL2 are formed on the channel region between the adjacent N-type source / drain regions 93. _For the N-type source / drain region 93 on both ends, the paper size is via the conductive layer._ Grid 〇〇 × 297 公 爱) ~ --- 313122 (Please read the precautions on the back before filling in this page)

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 35 584976 A7 ___ B7 V. Description of the invention (35) 96 Connect the double-junction TMR element 24 with the easily reversed side wall-shaped ferromagnetic layer 23a. The conductive layer 96 and the ferromagnetic layer 23 a are connected via a contact hole 99. In order to prevent the conductive layer 96 from reacting with the ferromagnetic layer 23a, a barrier layer (not shown) may be formed between the conductive layer 96 and the ferromagnetic layer 23a. A ferromagnetic layer 21 is formed on the side surface of the ferromagnetic layer 23a via an insulating barrier layer 22a. On the other side of the ferromagnetic layer 21, a ferromagnetic layer 23b that is easily reversed in the shape of a side wall is formed via an insulating barrier layer 22b. Here, the ferromagnetic layers 23a and 23b of the double-junction TMR element 24 are as described above. The center ferromagnetic layer 21 shown in FIG. 13 is formed into a zigzag shape. The bit line contact portion 94 located on the surface of the central N-type source / drain region 93 is connected to the bit line BL via a conductive layer 98. Then, the interlayer insulating films 95 and 97 are formed in a completely covered state. 15 to 17 are cross-sectional views and perspective views showing the manufacturing process of the double-junction TMr element portion shown in Figs. 13 and 14. The manufacturing process of the double-junction TMR element 24 will be described below with reference to FIGS. 15 to 17. First, as shown in Fig. 15, a ferromagnetic layer 21 having a pattern having a predetermined shape formed on the interlayer insulating film 95 is formed. Then, alumina 22 serving as an insulating barrier material is formed in a state of covering the magnetic layer 21 and the interlayer insulating film 95, and then a contact hole 99 is formed in the area where the alumina 22 is positioned on the conductive layer 96. Next, the ferromagnetic material layer 23 is formed over the entire surface. Then, anisotropic etching is performed on the entire surface to form ferromagnetic layers 23a and 23b having a sidewall shape as shown in FIG. Here, the ferromagnetic layer 23a is also formed in the contact hole 99, so the ferromagnetic layer 23a and the conductive layer 96 are in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 313122 (Please read the back Note this page, please fill in this page) # • t -------- line 1 · 584976 A7 I. J37 V. Description of the invention (36) It is in electrical connection state. As described above, the third embodiment can easily form the double-junction TMR element 24 composed of the ferromagnetic layers 21, 23a, and 23b by applying the same procedure as the conventional sidewall formation procedure. The materials of the ferromagnetic bodies 21, 23a, and 23b of the third embodiment are, for example, a multi-layer film formed of a ferromagnetic body 23a and 23b that is easy to reverse [... a core layer, a Py layer, and a Ta layer. In turn, the ferromagnetic layer 21 uses a multi-layered gadolinium formed of a co75-Fe25 layer, an Ir-Mn layer, a Py layer, a Cu layer, a py layer, and a Ta layer. The materials for the above ferromagnetic layer are described on page 5 of the 116th Annual Meeting of the Applied Magnetic Society of Japan, "Current Status and Future Prospects of mrAm and Competitive Technologies" (U.U. 17, 2000). Thereafter, as shown in Fig. 17, the ferromagnetic layers 23a and 23b are formed into a zigzag pattern. Thereby, a double-junction TMR element 24 as shown in Figs. 13 and 14 can be easily formed. The points of the above-mentioned embodiments are merely examples and the present invention is not limited thereto. The scope of the present invention is shown in the scope of the patent application of the present invention, and includes all changes within the meaning and scope equivalent to the scope of the patent application. For example, in the above embodiment, the memory element constituting the memory element is a TMR element, but the present invention is not limited to this. As long as it is a memory element having a strong magnetic tracking effect, a memory element other than the TMR element may be used. Further, a memory element having a magnetoresistance effect other than a memory element having a strong magnetic tunnel effect can be used to obtain the same effect as that of the above embodiment. In the second embodiment described above, the paper contains the contents of the first embodiment. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love). 313122 (锖 Please read the precautions on the back before filling this page)

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

* · I · # 1 · 1 ϋ ϋ ϋ ϋ ϋ II ϋ I ϋ ϋ ϋ n ϋ 1 · I ϋ H 1 ^ 1 ϋ ϋ .1 IH ϋ 1 I 36 584976 A7 B7 V. Description of the invention (37) Memory The configuration of the unit 52 is exemplified by the addition of a dummy bit line (virtual bl) and the comparator 201. However, the present invention is not limited to this, and a dummy bit line is added to the configuration of the third embodiment including the memory unit 82. (Virtual bl) and the comparator 201 can also achieve the same effect. [Effects of the Invention] As described above, according to the present invention, the memory unit is composed of two first and second memory elements and two first and second transistors having a strong magnetic tunnel effect, and an amplifier is used. Detects the potential difference between the bit line and the inverted bit line connected to the two first and second memory elements, so it is not necessary to have a memory element and a memory element and a transistor with a strong magnetic tracking effect as is conventional The state of the memory cell needs a sense amplifier of a complicated structure, so high-speed reading can be performed. In addition, since the configuration and circuit configuration of the sense amplifier and its operation method are similar to those of the conventional DRAM, the DRAM technology can be used as it is. As a result, the replacement of the DRAM is easy. In addition, since a memory element having a strong magnetic tracking effect including the first, second, and third magnetic layers, and two first and second transistors are used to constitute a memory cell, in addition to the above effects, comparison The state in which the memory unit is composed of two memory elements and two transistors has the effect of reducing the area of the memory unit. [Brief description of the drawings] Fig. 1 is a block diagram showing the overall configuration of the MRAM according to the first embodiment of the present invention. Figure 2 shows the MRAM memory cell unit and the paper size of the first embodiment. The paper used the Chinese National Standard (CNS) A4 specification ⑽χ 挪 公 爱) 313122 (Please read the note on the back? Matters before filling out this page)- Φ.-· .I Order -------- Printed by the Ministry of Economics, Wisdom and Property Bureau, Consumer Cooperatives, 37 584976 V. Description of Invention (38) Circuit diagram of the structure of the amplifier section. (Please read the precautions on the back before filling out this page.) Figure 3K 7K Waveform diagram of the read operation of the MRAM in the first embodiment shown in Figure 1 and Figure 2. Fig. 4 shows the cross-sectional structure of the MRAM memory cell unit of the first embodiment shown in Figs. 1 and 2. Fig. 5 is a block diagram showing the overall configuration of an MRAM according to a second embodiment of the present invention. Fig. 6 shows a circuit diagram of the "RAM memory cell unit and the sense amplifier unit" of the second embodiment shown in Fig. 5. Fig. 7 shows the internal configuration circuit diagram of the comparator shown in Figs. 5 and 6. Fig. 8 Fig. 9 shows the operation waveform concept of the read operation of the second embodiment. Fig. 9 shows the operation waveform simulation diagram of the read operation of the MrAM of the second embodiment. Fig. 10 shows the operation of the read operation of the MRAM of the second embodiment. Waveform simulation diagram. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. Figure 11 is a block diagram showing the overall structure of the MRAM according to the third embodiment of the present invention. Figure 12 shows the MRAM memory cell unit of the third embodiment of Figure 11. And the circuit diagram of the sense amplifier unit. Fig. 13 shows the plan layout of the MRAM memory cell unit in the third embodiment shown in Figs. 11 and 12. Fig. 14 shows the MR AM edge of the third embodiment shown in Fig. 13. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 38 313122 584976 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (39) Section 100-100 line section & Figure 15 Fig. 14 is a cross-sectional view for explaining the manufacturing process of the double-junction TMR element of the memory unit part. Fig. 16 is a cross-sectional view for explaining the manufacturing process of the double-junction tmr element of the memory unit part of Fig. 14. Fig. 17 The figure shows a perspective view for explaining the manufacturing process of the double-junction TMr element in the third embodiment of Fig. 14. Fig. 18 shows a schematic diagram of the structure of a conventional MRAM memory element. Fig. 19 shows the structure of a conventional MRAM memory element. Schematic diagram. Fig. 20 shows a block diagram of the entire structure of a conventional MRAM Q [Description of element symbols] la, lb, 21 ferromagnetic layer (second magnetic layer) 2b insulating barrier layer 3b, 23a ferromagnetic layer (first magnetic layer) TMR element (first memory element) DMR element (second memory element) 211 NMOS transistor (first transistor) 212 NMOS transistor (second transistor) 6 > 10a > 10b NMOS transistor 7 '9 PMOS transistor 8a, 8b NMOS transistor (separation transistor) 22a Insulation barrier layer (first insulation barrier layer) 22b Insulation barrier layer (second insulation barrier layer) 23b Ferromagnetic layer (third magnetic layer) 'This paper Standards apply to Chinese national standards (CNS) A4 specification (210 X 297 mm) '' ---- 39 313122 2a 3a 4a 4b 5a 5b (Please read the precautions on the back before filling this page). I order ·-line. 584976 V. Description of the Invention (4〇) Printed by A7 _B7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 24 Dual-junction TMR element (memory element) 51 Memory array 52 ~ 82 Memory unit 53 Sense amplifier (amplifier) 54 Column decoder 60 Line decoder 201 pre-charging circuit (Please read the precautions on the back before filling this page)

This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 40 313122

Claims (1)

584976 ___ ^ Printed by the Staff Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs 槪 No. 90126458 Patent Application Amendment to the Patent Scope (August 5, 1992) | 1 · A magnetic memory device having: The first memory element and the second memory element, and a memory unit composed of the first and second transistors each connected to the aforementioned second and second memory elements; the control terminals connected to the aforementioned first and second transistors Word line; connected to the first memory element winter bit line via the first transistor; connected to the second memory element through the second transistor just described to form a bit line pair with the bit line An inverted bit line; and an amplifier connected to the preceding bit line and the inverted bit line, so that when data is read, a signal is input to the selected word line and read by the amplifier The input signal is generated on the word line and a potential difference is generated between the bit line and the inverted bit line. 2. For example, the magnetic memory device of the patent application, wherein the front ^ th memory element and the front 22 memory element each include a magnetic layer and an insulation barrier layer facing the first magnetic layer. A second magnetic layer that is less easily reversed than the second magnetic layer; and further includes: a second magnetic layer connected to the first magnetic memory element and the second magnetic layer of the second memory element; When the signal line of the aforementioned character line rises, the second magnetic layer of the first memory element and the aforementioned paper size will apply the Zhongguan Standard (CNS) A4 specification (21G X297 public love) 1 (revised version) 313122 584976 No. The auxiliary word line for the potential of the second magnetic layer of the 2 memory element is pulled down to the ground potential. 3. The magnetic memory device according to item 1 of the scope of patent application, wherein the falling timing of the signal of the word line is that the potential of the second magnetic layer of the first memory element and the second magnetic layer of the second memory element reaches Perform before ground potential. 4. The magnetic memory device according to item 1 of the patent application scope, which further includes a separation transistor that separates the amplifier from the bit line and the inverted bit line according to the falling timing of the signal applied to the word line. . 5. The magnetic memory device according to item 1 of the scope of the patent application, wherein the aforementioned first §memory element and the aforementioned second memory element are used to memorize mutually opposite data. 6. The magnetic memory device according to item 1 or 2 of the patent application park, further comprising: a virtual bit line connected to the second memory element via the first transistor; and detecting the virtual bit line Falling timing detection circuit. Printed by the Staff Welfare Committee of the Central Bureau of Standards of the Ministry of Economic Affairs 7. If the magnetic memory device of the 6th scope of the patent application is applied, it further has the falling timing of the aforementioned virtual bit line that should be detected by another detection circuit so that the aforementioned amplifier and the aforementioned bit The transistor for separation in which the element line and the inverted bit line are separated, and the aforementioned amplifier is used to activate the falling timing of the virtual bit line obtained by the aforementioned detection circuit. 8. If the magnetic memory device according to item 6 of the patent application scope, wherein the aforementioned detection circuit includes an input voltage applied to the gate electrode and reference to this paper ^ National Standard (CNS) A4 specification (210 X 297 mm) -------- 2 (Revised version) 313122 9. The voltage is the second transistor applied to the gate, so that the current flowing through the third transistor is larger than the current flowing through the second transistor. When the input voltage is equal to the reference voltage, the L potential is turned on. A magnetic memory device comprising: a second magnetic layer having a first magnetic layer and a first insulating barrier layer interposed on a surface of the first magnetic layer, and one surface of which is opposed to each other; and a second magnetic layer on the second magnetic layer. A hidden element having a strong magnetic tunneling effect on the other surface of the third magnetic layer disposed opposite to the second insulating wall layer, and the first magnetic layer and the first magnetic layer of the third magnetic layer connected to the memory element A memory cell formed by a second transistor and a second transistor; a word line connected to the control terminal of the first and second transistors; a bit line connected to the first magnetic layer via the first transistor; An inverted bit line connected by the aforementioned second transistor to the aforementioned third magnetic layer and forming a bit line pair with the aforementioned bit line; and printed by the Staff Welfare Committee of the Central Standards Bureau of the Ministry of Economy and connected to the aforementioned bit line and the An amplifier of the transposed bit line, so that when reading data, input a signal to the selected word line, and use the amplifier to read out the bit line and the inverted bit line according to the signal input to the word line. Between The potential difference. 10. The magnetic memory device according to item 9 of the scope of the patent application, wherein the first magnetic layer includes a first magnetic layer having a sidewall shape formed on a side surface of one of the second magnetic layers via the first insulating barrier layer. Paper size applies Chinese National Standard (CNS) A4 specification (21 × 297 mm) 3 (Revised version) 3B122 584976 H3 The third magnetic layer contains another layer formed on the second magnetic layer through the second insulating barrier layer. The third magnetic layer in the shape of a side wall on one side. 11 · The magnetic memory device according to item 10 of the patent application scope, wherein the first magnetic layer and the third magnetic layer in the shape of the side wall are covered with an insulating barrier material layer. After the magnetic material layer is formed in the state of the second magnetic layer, anisotropic etching is performed on the magnetic material layer. 12. The magnetic memory device according to item 9 of the patent application park, wherein the second magnetic layer of the memory element has a formation ratio. The first magnetic layer and the third magnetic layer are not easy to be reversed, and are provided with a signal rising timing of the signal line applied to the word line to pull the potential of the second magnetic layer of the memory element. The auxiliary word line to the ground potential. 13. The magnetic memory device according to item 9 of the scope of patent application, wherein the timing of the signal applied to the word line is that the potential of the second magnetic layer provided on the memory element reaches the ground. Before the potential. Printed by the Staff Welfare Committee of the Central Bureau of Standards of the Ministry of Economic Affairs. For example, the magnetic memory device of item 9 of the patent application park, which has the timing of the signal applied to the word line. A transistor for separation in which the element line and the aforementioned inverted bit line are separated. 15. The magnetic memory device according to any one of the items 9 to 14 of the patent application, which includes the first magnetic layer and the third magnetic property. Layers of memory are opposite to each other. 16 · —A magnetic memory device with: 4 (Revised) 313122 584976 Printed by the Staff Welfare Committee of the Central Bureau of Standards, Ministry of Economic Affairs H3 Contains the first magnetic layer and the first magnetic barrier layer is interposed on the surface of the first magnetic layer, and one of the two surfaces is oppositely arranged. A magnetic layer and a memory element having a strong magnetic tunneling effect on the other surface of the second magnetic layer on the other side via a second insulating wall layer and having a strong magnetic tunnel effect; and A memory unit composed of the first and second transistors of the first magnetic layer and the third magnetic layer. 5 (Revised) 313122 This paper size applies to China National Standard (CNS) A4 (210 x 297 mm)