584937 五、發明說明（1) [發明所屬之技術領域] 本發明是有關於一種半導體元件之佈局結構，且特別 是有關於一種應用於記憶體元件之字元線交接點佈局結構 (Word Line Strap Layout Structure) o [先前技術] 在一個高儲存容量的的記憶體元件中，其記憶體陣列 (memory array)通常藉由場氧化層（field oxide， FOX)劃 分成數個記憶體區域（m e m o r y a r e a )，其中每一個記憶體 區域的資料容量例如是8百萬位元（M b i t s )、3 2百萬位元、 或是6 4百萬位元。記憶體陣列中的多晶石夕（p 〇 1 y s i 1 i c ο η ) 或多晶石夕化金屬（polysilicon silicide， polycide)字元 線（word 1 ine)係橫跨過數個不同的記憶體區域與其間之 場氧化層。為了降低字元線的阻值，可以藉由接觸窗將位 於記憶體區域之間（即位於場氧化層上）的字元線電性連接 至上層金屬線，以形成字元線交接點佈局結構。由於金屬 材料的阻值遠低於多晶矽（或多晶矽化金屬）的阻值，因 此，該佈局方式可以大幅減少記憶體元件之電阻電容遲滯 效應（RC delay)。 第1 A圖為習知字元線交接點佈局結構的上視圖，且第 1 B圖為該結構之I - Γ剖面圖。另外，第2圖繪示在記憶體 元件中，採用習知字元線交接點佈局結構時所產生的缺 點。 請同時參照第1 A圖以及第1 B圖，多晶矽字元線1 0 4橫 跨過位於基底1 0 0上之場氧化層1 0 2，其係位於二個記憶體584937 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a layout structure of a semiconductor device, and more particularly, to a layout structure of word line intersections applied to a memory device (Word Line Strap). Layout Structure) o [Prior art] In a high-capacity memory element, its memory array is usually divided into several memory areas by field oxide (FOX). The data capacity of each memory area is, for example, 8 million bits (M bits), 32 million bits, or 64 million bits. The polycrystalline stone (p 〇1 ysi 1 ic ο η) or polysilicon silicide (polycide) word line (word 1 ine) in the memory array spans several different memory regions. And the field oxide layer in between. In order to reduce the resistance value of the word line, the word line located between the memory regions (that is, on the field oxide layer) can be electrically connected to the upper metal line through the contact window to form a word line junction layout structure. . Since the resistance value of the metal material is much lower than that of polycrystalline silicon (or polycrystalline silicon silicide), this layout method can greatly reduce the RC delay of the memory element. Fig. 1A is a top view of a layout structure of a conventional word line junction, and Fig. 1B is an I-Γ cross-sectional view of the structure. In addition, Fig. 2 shows the defects generated when the conventional word line junction layout structure is adopted in the memory device. Please refer to FIG. 1A and FIG. 1B at the same time. The polycrystalline silicon character line 1 0 4 crosses the field oxide layer 1 2 on the substrate 100, which is located in two memories.
10881twf.ptd 第5頁 584937 五、發明說明（2) 區域1 0之間，另外，字元線1 0 2藉由接觸窗1 0 6與金屬線 1 0 8電性連接，以形成一個字元線交接點佈局結構，其中 接觸窗1 0 6係位於場氧化層1 0 2上。在高操作電壓的使用考 量下，場氧化層102的厚度通常高達5000〜6000埃，所以場 氧化層1 0 2與相鄰的記憶體區域1 0之間會有一個很大的階 梯高度（step height)。 請參照第2圖，由於場氧化層1 0 2的高度及寬度都相當 大，所以在靠近記憶體區域1 0邊緣的地方，用來定義位元 線（未繪示）之光阻圖案1 1 0的關鍵尺寸（c r i t i c a 1 d i m e n s i ο n )會受到場氧化層1 0 2的影響，使得位於記憶體 區域1 0邊緣之位元線的關鍵尺寸不在可接受的範圍内，另 外，由於這些位元線的電性與其他位元線不同，所以只能 作為假位元線（d u m m y b i t 1 i n e s )，如此將使記憶體陣列 的積集度（integration)下降。 [發明内容] 有鑑於此，本發明的目的就是在提供一種字元線交接 點佈局結構，這種佈局方式使得鄰近場氧化層之位元線其 關鍵尺寸不再受到場氧化層的影響，以解決習知技術所存 在的問題。 本發明的再一目的是提供一種字元線交接點佈局結 構，此佈局方式可以省去假位元線，而得以增加記憶體陣 列的積集度。 本發明提出的字元線交接點佈局結構係包括一隔離島 (isolation post)，一字元線，一接觸窗以及一金屬線。10881twf.ptd Page 5 584937 V. Description of the invention (2) Between the area 10, in addition, the word line 1 0 2 is electrically connected to the metal line 1 0 8 through the contact window 10 to form a character The line junction layout structure, wherein the contact window 106 is located on the field oxide layer 102. Considering the use of high operating voltage, the thickness of the field oxide layer 102 is usually as high as 5000 to 6000 Angstroms, so there is a large step height between the field oxide layer 102 and the adjacent memory region 10 (step height). Please refer to FIG. 2. Since the height and width of the field oxide layer 102 are quite large, a photoresist pattern 1 1 for defining bit lines (not shown) near the edge of the memory area 10 is used. The critical size of 0 (critica 1 dimensi ο n) will be affected by the field oxide layer 1 2, so that the critical size of the bit line located at the edge of the memory area 10 is outside the acceptable range. In addition, because these bits The electrical property of the line is different from other bit lines, so it can only be used as a dummy bit line (dummybit 1 ines). This will reduce the integration of the memory array. [Summary of the Invention] In view of this, the object of the present invention is to provide a layout structure of word line junctions. This layout method makes the key dimensions of bit lines adjacent to the field oxide layer no longer affected by the field oxide layer. Solve problems with conventional technologies. Another object of the present invention is to provide a layout structure of word line intersections. This layout method can eliminate dummy bit lines and increase the accumulation degree of the memory array. The layout structure of the intersection of word lines proposed by the present invention includes an isolation post, a word line, a contact window, and a metal line.
10881twf.ptd 第6頁 584937 五、發明說明（3) 其中，隔離島位於二個記憶體區域間的基底上，且此隔離 島可為藉由區域氧化法（local oxidation， LOCOS)所形成 的場氧化層。另外，字元線橫跨過基底與隔離島，且接觸 窗位於隔離島上方之字元線上，其中此隔離島與接觸窗的 尺寸相近。另外，金屬線位於基底上，且藉由接觸窗與字 元線電性連接。 在本發明之字元線交接點佈局結構中，由於隔離島和 接觸窗一樣小，因此，在定義位元線之光阻圖案時，靠近 記憶體區域邊緣的關鍵尺寸將不會受到隔離島的影響。也 就是說，位於記憶區邊緣的位元線可作為具有功用的位元 線，而不再是假位元線，且記憶體陣列的積集度亦可因此 提升。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： [實施方式] 第3圖至第5圖，其繪示依照本發明一較佳實施例的一 種字元線交接點佈局結構。其中，第3圖為字元線交接點 佈局結構的上視簡圖，第4圖為第3圖之字元線交接點佈局 結構的局部區域3 1 0的放大圖，且第5圖為第4圖所示之局 部結構的I V - I V ’剖面圖。 請同時參照第3圖、第4圖以及第5圖，字元線交接點 佈局結構係配置於二個記憶體區域3 0間之基底3 0 0上。此 佈局結構包括數個隔離島3 0 2、數條字元線3 0 4、數個接觸10881twf.ptd Page 6 584937 V. Description of the invention (3) The isolated island is located on the base between two memory regions, and the isolated island can be a field formed by local oxidation (LOCOS) Oxide layer. In addition, the word line spans the base and the island, and the contact window is located on the word line above the island, where the island is similar in size to the contact window. In addition, the metal line is located on the substrate and is electrically connected to the character line through a contact window. In the layout structure of the intersection of word lines of the present invention, since the island is as small as the contact window, when defining the photoresist pattern of the bit line, the critical size near the edge of the memory area will not be affected by the island. influences. That is to say, the bit line located at the edge of the memory area can be used as a functional bit line instead of a dummy bit line, and the accumulation degree of the memory array can be improved as a result. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: [Embodiment] FIGS. 3 to 3 FIG. 5 illustrates a layout structure of word line junctions according to a preferred embodiment of the present invention. Among them, FIG. 3 is a simplified top view of the layout structure of the character line junctions, and FIG. 4 is an enlarged view of a partial area 3 1 0 of the layout structure of the character line junctions of FIG. 3, and FIG. Section IV-IV 'of the partial structure shown in Figure 4. Please refer to FIG. 3, FIG. 4, and FIG. 5 at the same time. The layout of the word line junctions is arranged on the base 300 between the two memory regions 30. This layout structure includes several isolated islands 3 0 2, several character lines 3 0 4, several contacts
10881twf.prd 第7頁 584937 五、發明說明（4) 窗306以及數條金屬線308。其中，這些隔離島302形成於 二個記憶體區域3 〇間的基底3 0 〇上（如第3圖所示），這些記 憶體區域3 0例如是快閃式記憶體（f 1 a s h in e m 〇 r y )區域或是 動悲隨機存取記憶體（d y n a m i c r a n d o m a c c e s s m e m o r y， DRAM)區域，且隔離島3〇2可為藉由區域氧化法所產生之場 氧化層。 &另外，字元線3 0 4橫跨過基底30 0，其中每一條字元線 304 ^跨過至少一個隔離島302，而這些字元線304之材質 例如=多晶矽或是多晶矽化金屬。此外，接觸窗3 0 6係配 置於字tl線3 〇 4上，其中每一個接觸窗3 〇 6都位於一個絕緣 ，3 〇 2上方的字元線3 〇 4上，且接觸窗3 〇 6之材質例如是多 曰曰石夕之類的導電材質。另外，金屬線3〇8位於基底3〇〇上 1屬線3 〇 8的材質例如是铭或銅，其中，每一條金 由線3^8藉由至少一個接觸窗3〇6與字元線3〇4電性連接。 、於化屬材質之阻值遠低於多晶矽或是多晶矽化金屬，所 以°己思體元件的R C遲滯效應可以減小。 -侗^外’如第3〜4圖所示’位於相鄰二字元線3 0 4下方之 : 隔離島3 0 2彼此並未對齊，亦即位於鄰近二字元線3 0 4 -加，—個接觸窗3 0 6 ’以及位於^玄二接觸窗3 1 2周圍之該 未對t 70線的二個寬廣區312(broadened portion)也 愔鲈& °因此’字元線3 0 4之間的間距可以減小以增加記 二廿=件的積集度。除此之外’這些隔離島302的配置方 ^ ，限於第3圖所示之「之字形（zigzag f0rm)」配置 工 ”要任兩相鄰字元線3 0 4下之二個隔離島3 0 2彼此之10881twf.prd Page 7 584937 V. Description of the invention (4) Window 306 and several metal wires 308. The isolated islands 302 are formed on a base 300 between two memory regions 30 (as shown in FIG. 3). These memory regions 30 are, for example, flash memory (f 1 ash in em). (0ry) area or dynamic random access memory (DRAM) area, and the isolated island 302 may be a field oxide layer generated by the area oxidation method. & In addition, the character lines 3 0 4 cross the substrate 300, where each character line 304 ^ crosses at least one isolated island 302, and the material of these character lines 304 is, for example, polycrystalline silicon or polycrystalline silicon silicide metal. In addition, the contact windows 3 0 6 are arranged on the word t1 line 3 04. Each of the contact windows 3 06 is located on an insulation, the word line 3 04 above the 3 2, and the contact window 3 0 6. The material is, for example, a conductive material such as Shi Xi. In addition, the metal wire 300 is located on the substrate 300, and the material of the metal wire 300 is, for example, inscription or copper. Among them, each gold is made of wire 3 ^ 8 through at least one contact window 300 and word line. 3〇4 Electrically connected. The resistance value of Yuhua is much lower than that of polycrystalline silicon or polycrystalline silicon silicide. Therefore, the R C hysteresis effect of the body component can be reduced. -侗 ^ 外 'as shown in Figures 3 to 4' below the adjacent two-character line 3 0 4: The isolated islands 3 0 2 are not aligned with each other, that is, adjacent to the two-character line 3 0 4 -Plus A contact window 3 0 6 ′ and two broadened portions 312 (broadened portions) that are not aligned with the t 70 line around the contact window 3 1 2 are also 愔 & ° Therefore, the character line 3 0 The distance between 4 can be reduced to increase the degree of accumulation of the number of pieces. In addition, the arrangement of these isolated islands 302 is limited to the "zigzag f0rm" configuration worker shown in Figure 3, and two isolated islands 3 under two adjacent character lines 3 0 4 are required. 0 2 of each other
584937 五、發明說明（5) 間未對齊即可。此外，在二個記憶體區域之間，每一條字 元線上下亦可配置複數對的接觸窗以及隔離島，以降低字 元線與相對應之金屬線間的阻值。 在本發明之字元線交接點佈局結構中，由於隔離島與 接觸窗一樣小，因此在定義位元線的光阻圖案時，靠近記 憶體區域邊緣的關鍵尺寸將不會受到隔離島的影響。換言 之，靠近記憶體區域邊緣的位元線可作為具有功用的位元 線，不再是假位元線，且記憶體陣列的積集度亦可因此提 升。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。584937 Fifth, the invention description (5) can be misaligned. In addition, between the two memory regions, each character line can be provided with a plurality of pairs of contact windows and islands to reduce the resistance between the character line and the corresponding metal line. In the layout structure of the zigzag line intersections of the present invention, since the isolation island is as small as the contact window, when defining the photoresist pattern of the bit line, the critical size near the edge of the memory area will not be affected by the isolation island. . In other words, the bit lines near the edge of the memory area can be used as functional bit lines, which are no longer false bit lines, and the accumulation degree of the memory array can be improved as a result. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.
10881twf.ptd 第9頁 584937 圖式簡單說明 第1 A圖是習知字元線交接點佈局結構的上視簡圖，且 第1 B圖是該結構的I - Γ剖面圖； 第2圖繪示在記憶體元件中，採用習知字元線交接點 佈局結構時所產生的缺點； 第3圖是依照本發明較佳實施例之字元線交接點佈局 結構的上視簡圖； 第4圖是第3圖之字元線交接點佈局結構的局部區域 3 1 0的放大圖； 第5圖是第4圖所示之局部結構的I V - I V ’剖面圖。 [圖式標記說明]: 100 102 104 106 108 110 302 310 312 1 0、3 0 :記憶體區域 300 :基底 場氧化層 304 306 308 字元線 接觸窗 金屬線 光阻圖形 隔離島 局部區域 寬廣區 IH1 10881twf.ptd 第10頁10881twf.ptd Page 9 584937 Brief description of the diagram Figure 1 A is a simplified top view of the layout structure of a conventional word line junction, and Figure 1 B is an I-Γ section view of the structure; Figure 2 is a drawing It shows the shortcomings that occur when the conventional word line junction layout structure is adopted in the memory element; FIG. 3 is a schematic top view of the word line junction layout structure according to a preferred embodiment of the present invention; The figure is an enlarged view of a partial area 3 1 0 of the layout structure of the intersection of the zigzag lines in FIG. 3; FIG. 5 is a cross-sectional view taken along line IV-IV ′ of the partial structure shown in FIG. 4. [Illustration of Graphical Symbols]: 100 102 104 106 108 110 302 310 312 1 0, 3 0: Memory area 300: Basal field oxide layer 304 306 308 IH1 10881twf.ptd Page 10