TW582093B - Method for forming a damascene structure - Google Patents

Abstract

A method for forming a damascene structure. An insulating layer is deposited on a substrate. A capping layer and a hard mask layer are successively formed on the insulating layer. Subsequently, the hard mask layer is etched to form at least one opening using the capping layer as an etching stop layer. A conformable metal layer is formed over the hard mask layer and the surface of the opening, and the metal layer is then anisotropically etched to form a metal spacer over the sidewall of the opening. Next, the capping layer and the underlying insulating layer under the opening are etched to form a trench therein. Next, the hard mask layer and the metal spacer are removed. Finally, the trench is filled with the conductive layer to complete the structure after the substrate is cleaned.

Description

582093

Field of the Invention: The present invention relates to an integrated circuit and a manufacturing method for forming a separate structure by using a damascene process, particularly a method for interconnecting. Prior technology: In the manufacture of integrated circuits, each area of the integrated circuit or each of the integrated circuits: a two-conductor structure to connect and mount the mosaic technology to form the above-mentioned wire junction device. As of today, it has been widely used in the semiconductor industry. This is a very useful way. # The inlay process is a method of forming grooves in the edge of the manufacturing process of the interconnect. Then the whole sequence is sequenced. Before understanding the background of the present invention, the following steps are used to form a wire layer In order to enter a M # ^ μ ^ ^ .X, the following figures 1 a to 1 d illustrate the conventional formation of two: such as a Λ. First, please refer to FIG. 13 ^ Bo / Qi Japanese Yen, which has a metal wire layer 102 formed therein. A capping layer 104, such as a silicon nitride layer, is then formed to cover the wiring layer 102. Thereafter, one gold is sequentially deposited on the capping layer 104: two Fs' | electric layers (lntermetal dielectric, imd) 106 and-the capping layer 108. The interlayer dielectric layer 106 may be composed of a low dielectric constant (iowk) layer, such as spin-on-glass (SOG), fluorine-doped dioxide (FSG), and hydrogen-containing silicate (HSQ). , Fluorine-doped polyarylene ether jFLARE), and aromatic hydrocarbons (siLK). In addition, the upper cap layer 108 is used to protect the metal interlayer dielectric layer 106, which may be composed of silicon oxide.] Then, a hard mask layer 110 is formed over the upper cap layer 108, such as a nitrided layer. 'And a photoresist layer 1 having a groove pattern is formed thereon

582093 V. Description of the invention (2) 112 The photoresist layer 112 is used as a mask to anisotropically etch the hard mask layer 1 1 0, and an opening 1 1 4 pattern is formed therein. Next, please refer to section 丨 b. In the figure, after the photoresist layer 2 is stripped, the upper cap layer 108 exposed under the opening 114 is removed by reactive ion etching (reactive ion), to expose the surface of the insulating layer 106. Into the ground, due to the poor choice of etching between the hard cover curtain layer 110 and the upper cover layer 108 and the μ-electric layer 10 between the metal layers, the hard cover curtain layer 110 (= iHa! Ted), as shown in Figure 1b . When using progressive refinement, it forms a sloped proflle. That is, the critical pattern dimension (critlcal dimension (CD) f) of the trench U6 of H1 does not change the electrical characteristics of all parts. The outline of the hard mask layer 110 can be seen in the area enclosed by the dotted line in the figure. < Inappropriateness Next, referring to FIG. 1C, after removing the gradually thinned hard layer no, the top cover layer 108 is also lost, especially in denser areas: the area π 7 between the grooves 11 6. / 、 Scoop / Finally, '§Refer to Figure 1dd' to implement a standard pre-cleaning step by inductively coupled plasma (Icp) process K (for example, ion sputtering etching) to remove $ Oxide or polymer residue (not shown). Next, a conductive layer, such as a copper metal layer, is formed over the cap layer / 08, and filled in the trench 6S. Generally speaking, before filling the conductive layer, a barrier layer (not shown in green) is formed on the top cap layer 008 and the surface of the trench 116 in compliance, such as titanium nitride (TJ) or nitride. Group (TaN)

582093 V. Description of the invention (3) Chemical mechanical polishing (CMP) removes the excess conductive layer and the early resistive layer above the upper cap layer 108 to form a mosaic structure 11 8. However, the part of the upper cap layer located between the trenches 116 is partially lost after the CMP process, and a metal bridging is formed to reduce the reliability of the device. In order to solve the above problems, it has been suggested to use a metal hard mask, for example, a barrier material such as titanium nitride or a nitride button, so as to increase the selection ratio between the top layer and the dielectric layer between the metal layers. It is indeed possible to obtain trenches with vertical contours. Unfortunately, during the pre-cleaning process, the chimium atoms or denier atoms in the hard mask are sputtered by argon ions and deposited on the inner wall of the j cp reaction chamber, causing the ICP reaction chamber to fail and become unusable. SUMMARY OF THE INVENTION In view of this, the object of the present invention is to provide a method of forming a damascene structure to prevent the low dielectric material layer from being etched improperly, so as to prevent the key pattern size (CD) from changing or metal bridging (bridgi and then improving Reliability of components. Another object of the present invention is to provide a method for forming a mosaic structure to avoid the failure of an inductively coupled plasma (icp) reaction chamber after a pre-cleaning process. According to the aforementioned object, the method of the present invention Firstly, a top cover layer and a hard cover curtain layer are deposited on a substrate to form an end stop layer. The hard cover curtain layer provides a square insulation layer forming a mosaic structure, and then sequentially on the insulation layer [Next, At least one opening is formed by using the cap layer as one. Then,

582093 V. Description of the invention (4) After the hard cover layer is etched metal, the opening grooves are etched, and then the induction coupling plasma is cleaned to clean the substrate. Nitrile barriers such as 1 denier. In order to make the present invention, the following special enumerations are preferred: A metal layer is formed on the upper surface and the surface of the opening in conformity, instead of being an equal layer, so that a metal gap is formed on the side wall of the mouth. The upper top layer and the lower insulating layer form a trench to remove the hard mask layer and the metal spacer. Finally, argon ion sputter etching is performed in the (I CP) reaction chamber to fill a trench with a conductive layer to form a damascene structure. The layer includes a layer of low dielectric constant (low k) material. The upper doped silicon glass (USG) -type mask layer may be composed of silicon nitride or silicon carbide. The metal partition wall may be composed of aluminum metal or titanium nitride or a material, and the thickness of the above-mentioned purpose, characteristics, and advantages of Fan Ming can be more clearly understood. Examples and With reference to the accompanying drawings, detailed descriptions are as follows: Embodiments: The f method of forming a mosaic structure according to an embodiment of the present invention is described below with reference to FIGS. 2a to 2e. First, please refer to the second figure to provide a substrate 200, such as a silicon wafer, in which a metal layer 202 is formed. The metal layer 2O2 serves as a lower conductor layer and may be composed of copper metal or metal. Next, a cover layer 204, such as a silicon nitride layer, is formed on the substrate 2000 to cover the metal layer 202. Solitary, then, by conventional deposition techniques such as chemical vapor deposition

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(chemical Vapor DepoSitiOn, CVD), a dielectric layer 206 is formed on the base capping layer 204. In the present invention, the dielectric layer 206 is used as an intermetal dielectric layer (IMD). The interlayer dielectric ^ 206 may be composed of a general low dielectric constant material such as SOG, HSQ, FSG, FLARE, SiLK, or black diamond (black

diamond). Moreover, the preferred metal interlayer dielectric layer is in the range of 206 to 1000 Angstroms. Yu Youmu 4UUU Next, by a conventional deposition technique, such as CVI, an overlying layer 208 and a hard cover layer are sequentially formed over the interlayer dielectric layer 206. In the present invention, the overlying layer 2 0 8 can be composed of silicon oxide, such as undoped silicon oxide (USG), which is used to protect the interlayer dielectric layer 206 and serve as a polishing stop layer for subsequent CMP processes. Its thickness is between 10 and 15 〇〇ange range. Furthermore, the 'hard mask layer 2 10' may be composed of silicon nitride or silicon carbide, and its thickness is in the range of 100 to 15 Angstroms. Subsequently, a photoresist layer 2 1 4 having a trench pattern is formed over the hard mask layer 210. In addition, an anti-reflection layer (ARC) 21 2 such as silicon oxynitride can be selectively formed between the photoresist layer 2 and 4 and the hard mask layer 210 to reduce standing waves. Effect and optical proximity effect (OPPE). Next, the anti-reflection layer 212 above the upper cap layer 2 08 and the hard mask layer 210 below it are anisotropically etched by reactive ion etching (RI EE) to form an opening 2 in the hard mask layer 21〇. 1 6. Next ', please refer to Figures 2b to 2d, which will explain the key steps of the present invention. In Figure 2b, the photoresist layer is removed by an oxygen plasma or a suitable solvent.

0702-8996twf (nl); 91P63; SPIN.ptd page 10 582093 V. Description of the invention (6) --- 2 1 4 The text is protected by the cover layer 208, and the dielectric layer 206 is not damaged :. Next, a conformable terrain layer 218 is formed over the anti-reflection layer 212 and on the surface of the opening 216. In the present invention, the thickness of the metal layer 218 is in the range of 1000 to 500 Å, and it may be composed of aluminum metal or a commonly used barrier 2, such as titanium nitride or a nitride button. Furthermore, the metal layer 2 1 8 can be formed by physical vapor deposition (PVD) or CVD. Preferably, the metal layer 218 is formed by ionized physical vapor deposition (ionized PVD, I-PVD). Next, referring to FIG. 2c, the metal layer 2 丨 8 is anisotropically etched, for example, using reactive ion etching to form a metal space on the side wall of each opening 21 6, which is 2 2 0. In addition, if the metal layer 2 1 8 is formed by using pb, the subsequent step of anisotropically etching to form a metal spacer can be performed by in-situ argon ion sputtering etching. As a result, process steps can be reduced and productivity can be increased. Next, referring to FIG. 2d, the upper cap layer 208 below the opening 2 1 6 and the dielectric layer 2 06 of the process are etched to form a trench 222 in the dielectric layer 2 06. After the etching process is performed, the anti-reflection layer 212 is completely removed and a part of the hard mask layer 2 1 0 and the metal spacer 2 2 0 are consumed. / Compared with the conventional technology, since the metal partition wall 2 2 0 in the present invention can protect the sidewall of the hard mask layer 2 2 during the etching, a groove 2 2 2 with a vertical profile can be obtained to prevent the key Graphic size (⑶) changes. In addition, the top cover layer 208 is also protected by the hard mask layer 2 and the metal spacer 220 during the etching, which is beneficial to the subsequent CMP process. Finally, please refer to Figure 2e, remove the hard cover curtain layer 21〇, and at the same time m · m 1 1 0702-8996twf (nl); 91P63; SPIN.ptd Z ---- 1 582093

V. Description of the invention (7) Remove the metal spacers 2 2 0 left on the side wall. Then, similarly, a standard pre-cleaning process is performed by an inductively coupled plasma (I CP) process (argon ion beam-spraying) to remove native oxide layers or polymer residues (not shown). Next, a conductive layer, such as a copper metal layer, is formed over the cap layer 208 and filled into the trench 222. Generally speaking, before filling the conductive layer, an early barrier layer (not shown), such as a titanium nitride layer or a nitride group layer, is formed on the surface of the upper cap layer 208 and on the surface of the trench 2 2 2 in compliance. . Thereafter, by using a conventional polishing technique, such as chemical mechanical polishing (CMP), the excess conductive layer and the barrier layer above the cap layer 208 are removed to form a damascene structure 224. According to the method of the present invention, before the pre-cleaning process is performed, the metal partition wall 22o composed of the barrier material or the metal can be removed together with the hard cover layer 21o. Therefore, no pollution source is deposited inside the cp etching reaction chamber = a problem that causes its failure. In addition, the cap layer 208 between the trenches 2 2 0 is protected from loss before CMP is performed. Therefore, the problem of metal bridges can be effectively prevented, and the reliability of the components can be improved. Although the present invention has better defined the present invention 'any familiarity with this god and scope', it can be changed and treated as the scope of the patent application attached The embodiment is disclosed as above, but it is not intended to be a craftsman, without departing from the refined decoration of the present invention, therefore, the scope of protection of the present invention shall prevail. %

582093 Brief description of the drawings Figures 1a to 1d are cross-sectional views of the conventional method for forming a mosaic structure. Figures 2a to 2e are schematic cross-sectional views illustrating a method of forming a mosaic structure according to an embodiment of the present invention. Explanation of symbols: Conventional 10 0 ~ substrate; 10 2 ~ metal wire layer; 104 ~ capping layer; 106 ~ metal interlayer dielectric layer; 108 ~ upper cap layer; 1 10 ~ hard cover Curtain layer; 11 2 ~ photoresist layer; 1 1 4 ~ opening; 11 6 ~ groove; 1 7 ~ area between dense groove; 118 ~ mosaic structure; 120 ~ metal bridge. 200 ~ substrate of the present invention; 202, 218 ~ metal layer; 204 ~ capping layer; 206 ~ metal interlayer dielectric layer; 208 ~ upper cover layer; 210 ~ hard mask layer; 212 ~ anti-reflective layer; 2 1 4 ~ light Barrier layer; 2 1 6 ~ opening; 2 2 0 ~ metal spacer; 2 2 2 ~ trench; 224 ~ mosaic structure.

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Claims (1)

View 093. The scope of patent application includes at least the following steps: a method of forming a mosaic structure, depositing an insulating layer on a substrate; # a · sequentially forming / covering a layer and a hard cover layer on the insulating layer, by The hard cover layer is etched by the upper cover layer as a residual layer to the final soil layer to form at least one opening; ", a person forms a metal partition wall on the side wall of the opening; and etches Xiangguang below the opening and the below Insulating layer to form a trench; Removing the hard mask layer and the metal spacer; and filling a conductive pad in the trench to form a mosaic structure. 2 · The method of forming a mosaic structure as described in item 丨 of the scope of patent application 'Before filling the trench with the conductive material, the method further includes cleaning the substrate. 3 · Forming the mosaic as described in item 2 of the scope of patent application Structural method 'wherein the cleaning step is argon ion sputtering etching performed in an inductively coupled plasma reaction chamber. 4. The method of forming a damascene structure as described in item 1 of the scope of the patent application, wherein the insulating layer comprises a layer of a low dielectric constant material. 5. The method of forming a mosaic structure as described in item 1 of the scope of the patent application, wherein the cap layer is an undoped stone glass. 6, 6. The method for forming a mosaic structure as described in item 5 of the scope of the patent application, wherein the thickness of the cap layer is in the range of 丨 00 to 5,000 Angstroms. 7. The method for forming a damascene structure as described in item 1 of the scope of the patent application, wherein the hard mask layer is a silicon nitride layer or a silicon carbide layer. 582093 6. Scope of patent application 8. The method for forming a mosaic structure as described in item 7 of the scope of patent application, wherein the thickness of the hard mask layer is in the range of 100 to 15 Angstroms. 9. According to the method for forming a mosaic structure described in item 1 of the scope of the patent application, before the engraving of the hard mask layer, the method further includes the step of forming an anti-reflection layer on the hard mask layer. 10. The method for forming a damascene structure as described in item 9 of the scope of the patent application, wherein the anti-reflection layer is a silicon oxynitride layer. 11. The method for forming a mosaic structure as described in item 1 of the scope of patent application, wherein forming the metal spacer comprises at least the following steps: forming a metal layer on the rigid mask layer and conforming to the opening surface; and The metal layer is engraved to form the metal spacer on the side wall of the opening. 1 2. The method for forming a damascene structure according to item 11 of the scope of the patent application, wherein the thickness of the metal layer is in the range of 100 to 500 angstroms. 1 3 · The method of forming a damascene structure as described in item 11 of the scope of patent application, wherein the metal layer is a barrier material layer such as titanium nitride or tantalum nitride. 14 · The method of forming a damascene structure as described in item 11 of the scope of the patent application, wherein the metal layer is formed by physical vapor deposition or chemical vapor deposition. 15 · The method of forming a damascene structure as described in item 11 of the scope of patent application, wherein the anisotropic etching is reactive ion etching. 16 · The method for forming a damascene structure as described in item 11 of the scope of patent application, wherein the metal layer is formed by ionized physical vapor deposition. 582093 6. Scope of patent application 1 7. The method of forming a mosaic structure as described in item 11 of the scope of patent application, wherein the anisotropic etching is in-situ argon ion sputtering etching. 1 8. The method for forming a mosaic structure according to item 1 of the scope of the patent application, wherein the metal spacer is an aluminum metal spacer and has a thickness in the range of 100 to 500 angstroms. 19. The method for forming a damascene structure as described in item 1 of the scope of the patent application, wherein the conductive layer is a copper metal layer. 0702-8996twf (nl); 91P63; SPIN.ptd page 16