TW579568B - Substrate with embedded passive components and method for fabricating the same - Google Patents

Abstract

A substrate with embedded passive components and a method for fabricating the substrate are proposed. A core layer is formed with a first and second circuit layers on upper and lower surfaces thereof. Then a resistor film and a third metal layer is formed above the first circuit layer with an isolating layer, and a forth circuit layer is formed above the second circuit layer. After a fifth metal layer with a capacitor film is formed above the forth circuit layer, a plurality of plated through holes are formed to penetrate the substrate, and a third and fifth circuit layers are formed by patterning the capacitor film, third circuit, and fifth circuit layers. Finally, at least an isolating layer and circuit layer are formed above the third and fifth circuit layers with a conductive via formed in the isolating layer to electrically connect the circuit layers to provide a semiconductor device with capacitors and resistors without affecting the routability of the substrate.

Description

579568 V. Description of the invention (l) '-[Technical field to which the invention belongs] The present invention relates to a semiconductor package substrate and a manufacturing method thereof, especially a film-like passive structure embedded in a layered circuit board structure. The device's semiconductor package substrate and its manufacturing method 'provide good electrical functions. 'Previous technology' Under the trend of high-function and high-speed electronics, it is increasingly necessary to integrate passive components such as resistors, capacitors, and inductors on semiconductor components. To enhance or stabilize the electrical functions of electronic products. As shown in Figure 1, most of the passive components 2 are placed on the surface of the substrate i. The substrate can be a general printed circuit board or a packaging substrate for a semiconductor wafer. However, in order to prevent these passive components 12 from obstructing the semiconductor wafer ^ ΐ% Two% frgers) are electrically connected. Traditionally, these passive elements are usually placed on the corner of the substrate 1 or outside the semiconductor chip 1 i connection area = the area outside the board collar. • Limited placement will reduce the flexibility of the circuit layout on the surface of substrate 1 (Rotablllty) = The temple needs to consider the location of the solder pads, and it will turn over from the house. The number of moving parts at Zhilang Temple is limited, and the development trend of highly integrated Fengtu device is unfavorable. The number of moving parts 12 is increasing with the high performance requirements of semiconductor packages. Conventional methods The surface of the substrate 1 must simultaneously accommodate a large number of notebooks, conductive wafers 11 and a large number of passive components 12, and the selection of the mounting volume is not in line with the development trend of lightness, thinness and shortness of semiconductor packages. That is, as shown in FIG. 2, based on the above problems, it is conceived to integrate the movable element into the area between the semiconductor wafer 21 and the soldering area on the substrate 2.

17048 Quan 懋 .ptd 579568 V. Description of the Invention (2) Domain. However, as the number of output / input connections per unit area in a semiconductor device increases by several dollars, the number of bonding wires 23 also increases; further, the general passive component 22 south (about 0-8 mm) is higher than The height of the semiconductor wafer 21 (approximately 0.55 mm). To prevent the bonding wire 23 from touching the passive element 22 to cause a short circuit, the bonding wire 23 needs to be pulled up and across the passive element 22 directly above the soldering element to increase soldering difficulty. , Which also increases the length of the wire loop. Moreover, the bonding wire 23 itself has a weight. If the bonding wire 23 lacks support, it is easy to cause a short circuit due to its own gravity collapse and touch the passive components. Moreover, the bonding wire 2 3 itself is made of gold and aluminum. Increasing the length of the wire arc will Significantly increased the cost of welding wire 2 3. Furthermore, 'the passive components 22 are fixed to a predetermined soldering position of the substrate 2 with a solder paste using a conventional surface-mounting technology (SMT), and then a semiconductor device gel package is implemented. During the manufacturing process, the molten sealing resin 2 4 is injected under a high temperature environment. At this time, the operating temperature (1 75 ° C) is close to the melting temperature (1 8 3 ° C) of the soldering adhesive used for the passive component 22. The cement is in a semi-melted and softened state, which easily causes the passive components 22 to be subjected to the stress of the molten encapsulation resin 2 4 mold flow (Mo 1 df 1 ow) after the injection, causing the passive components 22 to deviate from the pre-mold. Set the welding position to reduce the conductive quality and even cause a short circuit. [Summary of the Invention] In view of the shortcomings of the conventional technology described above, the main object of the present invention is to provide a semiconductor package substrate with embedded passive components and a manufacturing method thereof, to increase the number of passive components in the semiconductor device, and to increase the substrate layout. flexibility. Another object of the present invention is to provide a semiconductor with embedded passive components.

17048 Quan 懋 .ptd Page 8 579568 V. Description of the Invention (3) ____ 丨: f substrate and its manufacturing method 俾 Reduce the substrate to make it thinner and shorter. Destacking to reach + conductor mounting Another object of the present invention is to bump the I package substrate and its manufacturing method to avoid passive elements, semiconductor components of moving elements, and even short circuits. The influence of temperature and mold flow is another object of the present invention to provide a method for mounting a substrate and a manufacturing method thereof to reduce soldering by reading semiconductors to save soldering costs. The length of the solitary wire is short. In order to achieve the purpose of opening and other purposes, the package substrates of the present invention and the nickname body of the present invention are mainly semi-conductive resistors that can be passively opened in the package. At the same time, at least-film passive element (Fllm_type resistor) is embedded in the board, and the semiconductor element is provided with a right band at the same time. The shape of the capacitor will not affect the layout of the substrate surface. ^ Gu Fan The semiconductor package I embedded with passive components according to the present invention includes the following steps: A method for manufacturing a substrate for a farmer ’s package is provided in advance. A core board is provided, and the first surface of the core board is formed with a first layer. A conductive metal layer, a second conductive metal, and a first conductive metal layer and a second conductive layer are patterned, and an I-circuit layer and a second circuit layer are patterned. ... layer, forming a first step, and performing a build-up process to form a resistive film and a third conductive metal layer on the first circuit layer I insulating layer of the substrate, and arranging a Fourth conductive metal layer, and drawing: Electrically, the fourth conductive metal layer forms a fourth circuit layer. ,

17048 Quan 懋 .ptd $ 9 pages 579568 5. Description of the invention (4) Stack the layers on the fourth circuit layer. Then, the third conductive gold layer is plated through and patterned on the build-up substrate to form a third circuit layer and a fifth capacitor element are embedded in the build-up substrate at the edge of the third circuit layer. Layer and circuit layer, and through the majority (Conductive via) electrical connection through the embedded passive method of the present invention, the film-shaped resistance element and the passive element in the electrical semiconductor device layout circuit layout flexibility, and can The goal of light, thin and short carcass device, @ is offset by the influence of the mold flow, even & difficult, avoiding the direct contact of the welding wire and ^ the length of the welding wire solitary, to save the crocodiles ^ ^ 妾 The following examples are advanced — and not affected by These embodiments are limited. It is clear that the actual dimensions of each level in the drawings are not drawn according to actual dimensions. [Embodiment] Please refer to FIG. 31 for the application of a stack of a capacitor film and a fifth conductive metal to form multiple holes.) In the metal layer and the circuit layer, 0 and the fifth are formed when the number of capacitors connected to these components is reduced, and the cost of short-circuiting the components also arises. The steps are detailed and the hair is not described. Count the electrical resistance film running through the surface of the substrate, finish the circuit layer, and insulate the circuit layer. The semiconductor inlay is used to avoid the phenomenon that can be avoided with the use of the electrical board. The short description of this figure is reflected and the fifth conductive metal becomes the resistance element. Forming at least one insulated conductive hole. In the package substrate and its substrate, to improve the function and increase the base area, so that the semi-conductive passive components are exposed to high temperature 'to reduce soldering roads' is also shortened. The invention formula is just a simple description of a multilayer substrate structure.

17048 Quan 懋 .ptd Page 10 579568 V. Description of the Invention (5) --___ Sectional schematic diagram of the package substrate. The remote package substrate 100 includes a core board 3, at least one insulation 40, a circuit layer 36 staggered with the insulation layer 40, at least one resistance film ^ at least one capacitor film 42, most electrically conductive circuit layers, The plated through holes 43a of the resistive film 蛊 ~ and the conductive blind holes 44a of the valley layer circuit layer 36 penetrating through the insulating layers 40. The insulating layer 40 electrically connected to the substrate 100 may be made of an organic material, a fiber-reinf or organic material, or an organic material, such as an epoxy tree. Yueyue (epoxy resin), poiyimide, maleimide / bisamine (Bismaleimide triazine-based) resin, Cyanate ester, etc. The circuit layer 36 is, for example, a patterned copper layer, and it can be formed between the insulating layers 40 by electroplating, electroless plating, or sputtering. The conductive blind hole 44a is formed in the insulating layer 40. The blind hole 44a can be formed by mechanical drilling or laser drilling, etc., and the insulating layer 40 is formed by electrical keys, electroless plating or sputtering. At least one conductive metal layer is formed by plating or the like, and the conductive metal layer can be completely or partially covered to the blind hole 44, and the circuit layers 36 are electrically connected by forming the conductive blind hole 44 a. The resistive film 41 includes a thick film and a thin film (Thin fi 1 m) resistive passive element, and the thick film resistive material is, for example, silver powder or carbon particles (Carbon part i cl e). Scattered in resin, and ruthenium oxide (Ru〇2) and glass powder are spread and coated in a binder (Binder) and then solidified. Relative to the thin film resistance material are nickel chromium (N 丨 _ c Γ), nickel phosphorus 11

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17048 Full 懋 .ptd Page 11 579568

V. Description of the invention (6) (Ni-P), nickel-tin (Ni-Sn), chrome-aluminum (Cr_A1), and titanium nitride (TaN) alloys 1 "1: 1 '叩 1 & 1: 11 ^) or electroless plating (£: 16〇1: 1 * 〇1 at 31) 1 at 11 ^) and so on. The remote selection uses a thick film resistor or uses For thin film resistors, b depends on the manufacturing cost of the multilayer circuit board and the electrical properties of the passive components to be manufactured = accuracy. And the size of the resistance value required for the semiconductor package substrate can be determined by the material of the resistance film 41 used and The size of the resistive film spaced between the electrodes 3 3 b formed on the resistive film 41 is determined. The capacitive film 42 is selected from a high dielectric layer with a large dielectric constant. Ceramic powder filled polymers and similar materials are usually suitable for dielectric constants greater than 5. Of course, the more the dielectric constant value is, the better the material can be, for example, Bar1Uin-titanate, titanium Lead acid (Lead_zirc〇nate_ titanate), Fedandan and ^ carbon), or pot powder ^ Right reverse (Am〇rph〇US hydr〇genated glass powder, etc., also It is formed in a binder, such as resin (Roller eQatlns # I sputtering, printing, or roller spin coating), and the semiconductor package substrate requires a 42-phase capacitive film. Material surface: The material of the capacitor film 42 used and the size of the capacitor film are determined. For the size of the capacitor film sandwiched between the parallel plates 3 4 b and 3 5 b, please refer to Section 3A to Chu Xifeng. FIG. 'Is a schematic view of a method for manufacturing a passive substrate package substrate made of the present invention. As shown in Figure 3A + ^ The first # of board 3 /, Bai Xian, a core board 3 is provided to A first conductive metal is respectively formed on the core surface 3a and the second surface flap.

Page 12 579568 V. Description of the invention (7) The layer 31 and the second conductive metal layer 32, wherein the first and second conductive metal layers 3 1, 3 2 are separated by an electrically insulating layer 30, and the conductive metal layer doubles θ "Ma copper metal or other conductive metals can be formed by etching. Document the first and second conductive metal layers 31, 32 to form a first electrical and a second circuit layer 32a, as shown in FIG. 3B, where the second a layers 31a, 32a can be used as general electronic signals and power sources. Or ground conductive layer. Of course, the core board 3 can also be a multi-layer circuit board, and there are many related circuit technology. However, it is a well-known process technology in the industry, which is not a special feature, so it will not be described again. ^ As shown in FIG. 3C, a layer-increasing process is then performed to form a resistive film 2f conductive metal layer 33 ′ through the insulating layer 40 on the # 芦 3 第一 电路 层 3 1 a, and A fourth conductive metal layer 34 is arranged on the two circuit layers 32 a through the insulating reed 4 and the fourth conductive metal sound is patterned to form a fourth circuit layer 34 a. As shown in FIG. 3D, the flute 'a “34 3 4a has a number of circuit areas that can be used to form a capacitive element such as the following, the line plate 34b ° the material of the insulating layer 40 can be an insulating organic material or a ceramic material, such as epoxy resin (Ε ρ ο X yresi η), Polyethylenimide (P ο 1 yimide), bismaleimide / imine / triazine (based on Bismaleimide triazine — based) branch j. Month purpose, or — composite material of g 1 assfiber The method of forming the insulation sound includes roller spin coating (R 〇1 1 erc 〇ating), printing (pr 丨 nt 丨 卩), and a direct lamination method using an insulating paste 1 ay- up), etc., of course, the insulating layer 40 is not limited to being formed by a single organic material , Also the superimposed layers made from different insulating materials. Which

17048 Quan 懋 .ptd Page 13 579568 V. Description of the invention (8) The resistive film 41 includes a thick film (Thick film) and a thin film (Thin nim) passive passive element. The thick film resistor material is such as silver powder (Si 丨 ver p0wder) or carbon particles (Carbon particles) are dispersed in the resin, and ruthenium oxide (Ru〇2) and glass powder are dispersed and coated with a binder (Binder) and then cured; the thin film resistance material is nickel-chromium (Ni-Cr), nickel plate (Ni_p), nickel-tin (Ni-Sn), chromium-aluminum (Cr-Al), and titanium nitride (TaN) alloy, etc., which can be sputtered, electroplated ( (Electr. Plating) or electroless plating (Electroless P 1 ati ng). As shown in FIG. 3E, a capacitor film 42 and a fifth conductive metal layer 35 are stacked on the fourth circuit layer 34a, and the capacitor film 42 is selected from a dielectric layer with a large dielectric constant. It is made of polymers such as polymer materials, pottery materials, pottery powder, and the like, and the materials can be, for example, barium titanate, lead-zirconate-titanate , Amorphous hydrogenated carbon, or its powder is dispersed in the binder (such as resin, glass powder, etc.), can also use sputtering, printing (Roller coating), etc. Way to shape. As shown in FIG. 3F, a large number of through holes penetrating through the substrate are then formed in the substrate, and a layer of conductive metal 43 'is disposed on the wall of the through hole and the surface of the substrate to form a through hole. 43a. As shown in FIG. 3G, the third conductive metal layer 33, the resistance film 41, and the fifth conductive metal layer 35 are patterned to form a third circuit layer 33a, a resistance electrode 3 3b, and a fifth circuit layer 35. a and a parallel plate 3 5 b with one of the capacitor elements to match the other parallel plate 34 b of the capacitor in the previously patterned fourth circuit layer.

17048 Quan 懋 .ptd Page 14 579568 V. Description of the invention (9) The resistive element 4 1 a and the capacitive element 4 2 a are embedded in the build-up substrate, and in the second circuit layer 33 a and the fifth At least one insulating layer 4 0 'is formed on the circuit layer 3 5 a. A plurality of blind holes 4 4 are formed in the insulating layer 4 by mechanical drilling or laser drilling, as shown in FIG. Show. As shown in FIG. 31, at least one conductive metal layer 36 is formed on the insulating layer 40 by electroplating, electroless plating, or sputtering, and the conductive metal layer 36 can be completely or partially covered to the blind hole. 44. By forming at least one conductive blind hole 44a that can be electrically connected to the third circuit layer 33a with a resistive element 41a or the fifth circuit layer 35a with a capacitive element 42a, an embedded (membrane-like) passive film is completed. The manufacturing process of the multilayer packaging substrate q of the device. As shown in Fig. 3J, Foo can continue to use the build-up (Buui 1 d-up) process to continuously increase the insulation layer and the circuit layer on the 100 surface of the substrate, thereby forming a circuit with more circuit layers. Package substrate. The substrate 100 can be applied to a flip-chip (F 1 1 P Ch 1 p) package substrate, or a general wire bonding package substrate. Through the semiconductor package substrate with passive components embedded in the present invention and the manufacturing method thereof, the film-shaped resistance element and the capacitor element are embedded in the substrate, and a semi-body device is provided with both the resistor and the capacitor element to enhance the passiveness in the semiconductor device. The number of 7L components and electrical functions, and increase the flexibility of the circuit layout of the substrate, and can reduce the use area of the substrate to achieve the goal of thin, light and short semiconductor devices, at the same time, can also avoid the passive components from being affected by high temperature and mold flow 'Even short-circuits occur to reduce soldering difficulty and avoid short-circuits caused by direct contact with fresh wires and passive components. In the previous figure, only a resistive film and a capacitive film are used.

17048 全懋 .ptd Page 15 579568 V. Description of the Invention (ίο) The number and relative position of the resistance film, capacitor film and circuit layer are designed and distributed between the stacks of the substrate according to the actual process requirements, and the process It can be implemented on one or both sides of the core board. And the specific embodiments described above are only used to illustrate the features and effects of the present invention, but not to limit the scope of the invention that can be implemented, without departing from the spirit and technology disclosed by the present invention. Shufan® Shou In the following, any equivalent changes and modifications made by using the disclosure of the present invention shall still be covered by the scope of patent application described below.

17048 Quan 懋 .ptd Page 16 579568 Brief description of the drawings [Simplified description of the drawings] The first diagram is a schematic diagram of the additional layout area of a substrate on which a passive component is placed outside the semiconductor wafer receiving area, and the second diagram is For the sake of acquaintance, the passive components are integrated. The cross-sectional schematic diagrams between the semiconductor wafer and the soldering area, and Figures 3A to 3J are embedded in the present invention. 11,21 Semiconductor wafer 12, 22 Passive element 23 Welding wire 24 Encapsulation resin 3 Core board 30 Electrical insulation layer 3 a First surface 3b Second surface 31 First conductive metal layer 32 Second conductive metal layer 31a Circuit layer 3 2s second circuit layer 33 third conductive metal layer 33a first-^ * circuit layer 33b resistance electrode 34 fourth conductive metal layer 34a fourth circuit layer 35 fifth conductive metal layer 35a fifth circuit layer 34b, 3 5b Capacitance parallel plate 36, 43 Conductive metal layer 40 Insulation layer 41 Resistive film 41a Resistive element 42 Capacitive film 42a Capacitive element 43a Electroplated conductor L 44 Blind hole 44a Blind hole

17048 Full 懋 .ptd Page 17

Claims (1)

579568 6. Scope of patent application 1. A method for manufacturing a semiconductor package substrate with embedded passive components, comprising: providing a core board, and the first and second surfaces of the core board are respectively formed with a first circuit layer and a second circuit At least one resistive film and a conductive metal layer are formed at an insulating layer on the first circuit layer of the core board, and a fourth circuit layer is formed at an insulating layer on the second circuit layer; Forming at least a capacitor film and a conductive metal layer on the circuit layer; and forming a plurality of plated through holes penetrating the surface of the substrate, and patterning the conductive metal layer and the resistance film of the substrate with respect to the first surface of the core board, and A conductive metal layer on the surface of the second surface capacitor film of the core layer board to form a third circuit layer and a fifth circuit layer. 2. If the method of manufacturing a semiconductor package substrate according to item 1 of the patent application, wherein the third circuit layer on the surface of the resistor film can be formed as an electrode of a resistance element 3. If the method of manufacturing the semiconductor package substrate according to item 1 of the patent application, The fifth circuit layer on the surface of the capacitor film can be formed as a parallel plate of the capacitor element. 4. For the method of manufacturing a semiconductor package substrate according to item 2 of the patent application, wherein at least one insulating layer, a circuit layer, and a conductive blind hole are formed on the third circuit layer, and the conductive blind hole can be electrically connected to the electrode of the resistance element. 5. The method for manufacturing a semiconductor package substrate according to item 3 of the patent application, wherein at least one insulating layer, a circuit layer, and a conductive blind hole are formed on the fifth circuit layer, and the conductive blind hole can be electrically connected to the parallel plate of the capacitor element. 17048 Quan 懋 .ptd Page 18 579568 6. Scope of Patent Application 6 · If the scope of patent application is 1st, the main road is M Li @ & ί 丰 v 体 封 裴 substrate manufacturing method, in which the shai core laminate system is -Any of a double-layer circuit board and a multilayer circuit board. 7 · As for the first item of the scope of patent application: M 4 ^ 1 r · Xiangfeng conductor packaging substrate manufacturing method, in which :::, ", = film (Thlck f 1 lm) and thin film (Thin fi lm) resistive material The method of manufacturing a semiconductor package substrate with a profit range of $ 7, in which the film resistor material is silver powder, carbon part icle dispersed in a resin, and ruthenium oxide (Ru 〇2) It is formed by coating and curing with glass adhesive on any one of the adhesive (B inder). 9 · The method of manufacturing a semiconductor package substrate according to item 7 of the patent scope, wherein the thin film resistor material is Ni-Cr, Ni-P, Ni-Sn, Cr-A1, and Titanium Nitride (TaN) alloys It can be formed in any of the following ways: sputtering, electroplating, and electroless plating. I 0 · As in the method for manufacturing a semiconductor package substrate according to the scope of patent application No. 1, wherein the shaidian valley film system is made of polymer materials, Ceramic material, ceramic powder filled polymer and its mixture II · The method for manufacturing a semiconductor package substrate according to item 1 of the scope of patent application, wherein the capacitor film is a barium titanate (Barium -1 itanate), a titanate (Lead-zirconate-titanate), amorphous hydrogenation Carbon (Amorphous hydrogenated carbon) and any one of its powders are dispersed in a binder (B inder). ] 7048 全懋 .ptd Page 19 579568 VI. Application for Patent Scope 12. —Semiconductor package substrate with embedded passive components, which mainly includes: At least one core board with patterned circuit layers formed on its surface; multiple layer patterns Patterned circuit layers spaced apart from each other by an insulating layer to be stacked on the surface of the core board; at least one resistive film and at least one capacitive film formed on the patterned circuit layer; and a plurality of plated through holes formed on the substrate In the present invention, the related patterned circuit layer, resistor film and capacitor film are electrically connected. 13. The semiconductor package substrate according to item 12 of the scope of patent application, wherein the circuit layer on the surface of the resistive film can be formed as an electrode of a resistive element. 14. The semiconductor package substrate according to item 12 of the scope of patent application, wherein the circuit layer on the surface of the capacitor film can be formed as a parallel plate of a capacitor element. 15. The semiconductor package substrate according to item 13 of the scope of patent application, wherein at least one insulating layer, a circuit layer, and a conductive blind hole are formed on the circuit layer, and the conductive blind hole can be electrically connected to the electrode of the resistance element. 16. The semiconductor package substrate according to item 14 of the scope of patent application, wherein the circuit layer can be formed with at least one insulating layer, a circuit layer, and a conductive blind hole, and the conductive blind hole can be electrically connected to the parallel plate of the capacitor element. 17. The semiconductor package substrate according to item 12 of the patent application scope, wherein the core board is any one of a double-layer circuit board and a multilayer circuit board. 18. The semiconductor package substrate according to item 12 of the patent application scope, wherein the resistive film is any one of a thick film and a thin film resistive material. 19. The semiconductor package substrate according to item 18 of the scope of patent application, wherein the 17048 Quan 懋 .ptd Page 20 579568 6. The scope of patent application Thick film resistor material is silver powder (Carbon part icie) dispersed in resin, and ruthenium oxide (Ru〇2) and glass The powder is spread and formed by applying and curing any of a binder. 20 · = Semiconductor package substrate of the 18th in the scope of patent application, wherein the thin film resistance material is nickel-chromium (Ni-cr), nickel-phosphorus (Ni-P), nickel-tin (Ni-Sn), and chromium inscription (Cr Any one of the groups consisting of -Al) and titanium nitride (TaN) alloys is formed by any of the methods of sputtering, electroplating, and electroless plating. 2 1 · The semiconductor package substrate according to item 12 of the scope of patent application, wherein the capacitor film is composed of a polymer material, a ceramic material, a ceramic powder-filled polymer, and a mixture thereof. 22. The semiconductor package substrate according to item 12 of the application, wherein the capacitor film is barium arsenate (Barium -1 itanate), lead-zirconate-ti tanate, amorphous hydrogenated carbon (Amorphous hydrogenated carbon), and any one of the powders is dispersed in a binder (B inder). 17048 Full 懋 .ptd