TW577151B - Manufacturing method of read only memory - Google Patents

Abstract

A manufacturing method of read only memory includes forming a nitride-stacked layer on a substrate; performing an etch process to define the nitride-stacked layer to expose a bottom oxide layer; performing a clean process to remove the particles remaining on the patterned nitride-stacked layer sidewalls and the bottom oxide layer surface; performing an ion implant process to form a doped area in the substrate between the patterned nitride-stacked layer.

Description

577151 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a method for manufacturing a memory, and more particularly to a method for manufacturing a read only memory (ROM). In the prior art, in the read-only memory, the flash memory has the advantages of being programmable, erasable, and data can be saved after power-off, and has more ability to be used in the circuit than the erasable and programmable read-only memory. The internal (i η-circuit) has the advantages of electrical programming and electrical removal, so it has become a read-only memory element widely used in personal computers and electronic devices. In the conventional silicon nitride read-only memory (Nitride ROM) manufacturing process, after defining the silicon oxide / silicon nitride / silicon oxide stacked layer by etching, it is usually carried out by buried buried η (BD). Ion implantation process. However, in the previous process, particles or residual particles (partic 1 es) were formed on the bottom or sidewalls. These particles are equivalent to a hard cover during the implanted ion implantation process. As a result, the distribution of implanted ions is poor, and the integrity of the buried drain oxide formed later is not good, which leads to the reliability of the device. Moreover, for a read-only memory with a floating gate, since the source / drain implantation process is usually performed after the gate structure is defined by etching, the problem that the aforementioned particles become implanted into the hard cover is also It may occur, and the result will also affect the integrity of the implanted contour, which will cause the problem of reliability of the component. Summary of the Invention

9769twf.ptd Page 5 577151 V. Description of the invention (2) · Therefore, the object of the present invention is to provide a method for manufacturing a read-only memory, which can avoid the embedded drain or source / drain implantation process. Problems with poor implanted ion distribution. Another object of the present invention is to provide a method for manufacturing a read-only memory, which can improve the integrity of the buried drain oxide layer of the silicon nitride read-only memory. The invention provides a method for manufacturing a read-only memory, which is suitable for manufacturing a silicon nitride read-only memory. This method is to form a silicon nitride stacked layer on a substrate, and then form a patterned cover on the silicon nitride stacked layer. The curtain layer is patterned with a mask layer as a mask, and an etching process is performed to define a silicon nitride stack layer and retain an underlying oxide layer. Then, a cleaning process is performed to remove the etching process. · Residual particles on the sidewalls of the defined silicon nitride stack and the surface of the bottom oxide layer. Then, a patterned mask layer is used as a mask to perform an ion implantation process to form a doped region in the substrate between the defined silicon nitride stacked layers. The invention proposes another method for manufacturing a read-only memory, which is suitable for manufacturing a read-only memory with a floating gate. This method sequentially forms a patterned strip-shaped dielectric layer and a patterned strip on a substrate. A conductive layer, and then sequentially forming a dielectric layer and a gate conductor layer on the substrate, and then forming a patterned mask layer on the gate conductor layer, and then using the patterned mask layer as a mask, an etching process is performed. The gate conductor layer, the dielectric layer, the strip conductor layer, and the strip dielectric layer are defined to form a gate structure. Thereafter, a cleaning process is performed to remove particles remaining on the side wall of the gate structure and the surface of the substrate remaining in the etching process. Then, a source / drain region is formed in the substrate on both sides of the gate spring electrode structure. It can be known from the above that the present invention applies a cleaning process after the etching process.

9769twf.ptd Page 6 577151 V. Description of the invention (3) The process can completely remove the particles generated in the previous etching step, so that the doped region formed by the subsequent ion implantation process can have better Distribution and contour. Moreover, since the doped region formed by the ion implantation process of the present invention can have a better distribution and profile, the buried drain oxide layer formed will have a better invasive effect and completeness. In addition, since the mask layer is not removed during the cleaning process, the thickness of the silicon nitride stacked layer or the gate structure can be maintained and its integrity can be maintained. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: Embodiment: FIG. 1A Figures 1 to 1E are schematic cross-sectional views illustrating a manufacturing process of a read-only memory according to a preferred embodiment of the present invention, and are suitable for manufacturing silicon nitride read-only memory. First, referring to FIG. 1A, a silicon nitride stacked layer 108 is deposited on a substrate 100. The stacked structure is composed of a bottom oxide layer 102 and a gasified stone An oxide / nitride / silicon oxide (0 N 0) composite layer composed of a layer 104 and a top oxide layer 106. The bottom oxide layer 102 is formed by, for example, a thermal oxidation method, the silicon nitride layer 106 is formed by, for example, a chemical vapor deposition method, and the top oxide layer 106 is formed by using wet hydrogen / oxygen (H2 / 02 gas) is formed by deoxidizing a part of the silicon nitride layer 104.

9769twf.ptd Page 7 577151 V. Description of the invention (4) · Next, please refer to Figure 1B, define the top oxide layer 106 and the silicon nitride layer 104 to form several read-only memories as silicon nitride. The strip-shaped top oxide layer 106a of the cell dielectric layer and the strip-shaped nitrided layer 104a are exposed, and a part of the bottom oxide layer 102 is exposed. The method for forming the strip-shaped top oxide layer 1 0 6 a and the strip-shaped silicon nitride layer 1 0 4 a is, for example, forming a patterned mask layer 110 on the top oxide layer 106 and using the mask layer 1 10 is a mask, and a part of the top oxide layer 106 and the silicon nitride layer 104 are removed by anisotropic etching. Moreover, the above-mentioned process for defining the silicon nitride stacked layer 108 may also be defined by the etching process for the top oxide layer 106, the nitride nitride layer 104 and the bottom oxide layer 102 until the substrate 100 is exposed. As described above, after the top oxide layer 106 and the silicon nitride layer 104 are defined by anisotropic etching, the sidewalls and the bottom of the top oxide layer 106a and the silicon nitride layer 104a are defined. Particles 1 1 2 may be generated on the surface φ of the oxide layer 102, and these particles 1 1 2 are equivalent to a hard mask, which will affect the subsequent ion implantation process. Next, referring to FIG. 1C, a cleaning process 1 1 4 is performed on the substrate 100, so that the sidewalls of the top oxide layer 10 6 a and the silicon nitride layer 10 4 a and the surface of the bottom oxide layer 102 The particles 1 1 2 are removed. Wherein, the cleaning process 1 1 4 is, for example, the use of ammonia water peroxy 4 氢 hydrogen>, Kun He> night (Ammonia-Hydrogen perocide Mix, AP) for cleaning, because the present invention is defined in the top oxide layer 106 This cleaning process 1 1 4 is performed after the etching process with the silicon nitride layer 104, so that the fine particles generated on the etching process and attached to the wafer surface can be completely removed by the cleaning process 1 1 4. Moreover, during the cleaning process 1 1 4, the mask layer 1 1 0 on the top oxide layer 1 0 6 a remains, so the top oxide layer 1 6 a can be protected from being invaded by the cleaning solution. So as to be able to keep the nitride broken stack layer 108

9769twf.ptd Page 8 577151 V. Description of the Invention (5) · Keep the thickness unchanged and maintain its integrity. Next, referring to FIG. 1D, using the mask layer 1 10 as a mask, an ion implantation step 1 16 is performed to form a doped region 1 18 in the substrate 100. Since all the particles have been completely removed by the cleaning step 1 4, the implanted ions can form a doped region with a better distribution and profile in the substrate 100 ° 118 °, and if the bottom oxidation is retained in the above process Layer 102 is not removed (see Figure 1B), the exposed bottom oxide layer 102 can also be removed, and then the subsequent process can be performed. Next, referring to FIG. 1E, a buried electrodeless oxide layer 120 is formed on the surface of the doped region 1 18, and the bottom oxide layer 102 becomes the bottom oxide layer 102a. _ Where the buried drain oxide is formed The method of layer 1 2 0 is to use a wet oxidation method to form an oxide insulating layer on the surface of the doped region 1 1 8. In addition, since the doped region 1 1 8 formed has a better distribution and profile, the buried drain oxide layer 1 2 0 formed here will have a better penetration effect and completeness. . Subsequently, a conductor layer 1 2 2 such as polycrystalline silicon is formed on the substrate 100 as a word line of the silicon nitride read-only memory. In addition, since the subsequent process of forming a silicon nitride read-only memory device is well known to those skilled in the art, it will not be repeated here. In addition to the silicon nitride read-only memory, the present invention can also be applied to other types of read-only memory, such as a read-only memory with a floating gate. Please refer to Figs. 2A to 2D, and Figs. 2A to 2D are shown in the schematic diagram of the manufacturing process of a read-only memory according to another preferred embodiment of the present invention. In the manufacture of read-only memory with floating gates.

9769twf.ptd Page 9 577151 V. Description of the invention (6) First, please refer to FIG. 2A to sequentially form a plurality of parallel patterned strip-shaped dielectric layers 2 0 2 on the substrate 2 0 0 and The patterned strip-shaped conductor layer 204 is then sequentially formed on the substrate 200 with a dielectric layer 206 and a gate conductor layer 208. The method for forming the strip-shaped dielectric layer 202 and the strip-shaped conductor layer 204 is, for example, sequentially forming a thermal oxidation layer (not shown) and a conductive material layer (not shown) on the substrate, and then defining A conductive material layer and a thermal oxidation layer are formed. Next, please refer to FIG. 2B, define the gate conductor layer 208, the dielectric layer 206, the strip conductor layer 208, and the strip dielectric layer 2 02 to form a gate electrode 2 0 8 a. A gate structure 2 1 0 composed of a polycrystalline silicon interlayer dielectric layer 2 6 a, a floating gate 204 a and a tunneling oxide layer 2 02 a. The method for forming the gate structure 2 〇 is, for example, forming a patterned mask layer 2 1 2 on the gate conductor layer 208, and using the W mask layer 2 1 2 as a mask to anisotropic The etching method removes part of the gate conductor layer 208, the dielectric layer 206, the strip conductor layer 204, and the strip dielectric layer 202. Similarly, after the gate structure 2 is defined by anisotropic etching, particles 2 1 4 may be generated on the side walls of the gate structure 2 1 and the surface of the substrate 2 0, and these particles 2 1 The 4 series is equivalent to a hard mask and will affect the subsequent ion implantation process. Next, referring to FIG. 2C, a cleaning process 2 16 is performed on the substrate 200 to remove the particles 2 1 4 on the gate structure 2 10 sidewall and the surface of the substrate 2 00. The cleaning process 2 1 6 uses, for example, an Ammonia-Hydrogen perocide Mixture (APM) for cleaning. Since the present invention performs this cleaning process 2 1 6 after the anisotropic etching process that defines the gate structure 2 1 0, the microstructure attached to the surface of the substrate 2 0 0

9769twf.ptd Page 10 577151 V. Description of the invention (7) Particles 2 1 4 can be completely removed. Similarly, during the cleaning process 2 1 6, the mask layer 2 1 2 on the control gate 2 8 a still remains, so the thickness of the gate structure 2 1 0 can be maintained and maintained. Completeness. Next, referring to FIG. 2D, with the mask layer 2 12 as a mask, an ion implantation step 2 1 8 is performed to form a source electrode in the substrate 2 0 on both sides of the gate structure 2 1 0. The non-polar region 2 2 0, since all the particles have been completely removed by the cleaning step 2 1 6, the implanted ions can form a doped region (source / drain) with a better distribution and contour in the substrate 2 0 Polar region 2 2 0). Since the subsequent process of forming a read-only memory device is well known to those skilled in the art, it will not be described again here. In summary, it can be known that: 1. For silicon nitride read-only memory, the present invention applies a cleaning process after defining the silicon nitride stacked layer process, so that it can generate the nitride in the previous etching step. The particles on the sidewall of the stacked layer and the surface of the bottom oxide layer (or the surface of the substrate) are completely removed, so that the doped region formed by the subsequent ion implantation process can have a better distribution and profile. 2. Since the doped region formed by the present invention can have a better distribution and profile, the buried drain oxide layer formed later will have a better intrusion effect and can 'promote the buried drain oxide' The integrity of the layer. 3. For a read-only memory with a floating gate, the present invention applies a cleaning process after the process of defining the gate structure, so that the microparticles generated on the gate sidewall and the substrate surface generated by the previous touching step can be used. Completely cleared, which can also make subsequent doped regions (source / drain regions) have better separation

9769twf.ptd Page 11 577151 V. Description of the invention (8) Cloth and outline. 4. Since the present invention still has a top oxide layer or a mask layer on the control gate during the cleaning process, the top oxide layer or the control gate can be protected from being attacked by the cleaning solution, so that silicon nitride can be maintained. The thickness of the stacked layer or gate structure remains unchanged and its integrity. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

9769twf.ptd Page 12 577151 Brief Description of Drawings Figures 1A to 1E are schematic cross-sectional views illustrating a manufacturing process of a read-only memory according to a preferred embodiment of the present invention. 2A to 2D are schematic cross-sectional views illustrating a manufacturing process of a read-only memory according to another preferred embodiment of the present invention. Description of the drawing: 1 00, 2 0 0: substrate 1 0 2, 1 0 2 a · bottom oxide layer 1 0 4, 1 0 4 a: silicon nitride layer 1 0 6, 1 0 6 a: top oxide Layer 1 0 8: Silicon nitride stack layer 1 1 0, 2 1 2: Mask layer 1 1 2, 2 1 4: Particle 1 1 4, 2 1 6: Cleaning process 1 1 6, 2 1 8: Ion implant Process 1 1 8: doped region 1 2 0: buried drain oxide layer 1 22: conductor layer 2 0 2: strip dielectric layer 202a: tunneling oxide layer 2 0 4: strip conductor layer 2 0 4 a: floating gate 2 06: dielectric layer, 2 06 a: polycrystalline silicon dielectric layer 2 8: gate conductor layer

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Claims (1)

577151 VI. Scope of patent application 1. The purchase memory is in the nitrogen which is entered by silicon nitride to define the area. 2. Method, which is carried out 3. Method, which includes 4. a body, a base, the nitrogen, the stack of the graph, a silicon silicon, the graph has been used in the application, the cleaning is used in the application as in the application method, where The top oxide layer proceeds from Luzhong to Lulushen 5. Method, which includes # 刻 6. The manufacturing method of read-only memory is suitable for manufacturing a silicon nitride. The method includes: forming a silicon nitride stacked layer on the bottom A patterned mask layer is formed on the siliconized stacked layer; the masked layer is a mask, and an etching process is performed to define the layer; a cleaning process is performed to remove the remaining of the etching process from the sidewalls of the defined stacked layer and the Particles on the surface of the bottom oxide layer; and the mask layer is a mask, and an ion implantation process is performed to form a doping in the substrate between the silicon nitride stacked layers. The manufacturing process of the read-only memory cleaning process includes the use of an aqueous ammonia-hydrogen peroxide mixed solution (APM). 〇Please refer to the manufacturer of the read-only memory described in item 1 of the patent scope. The doped region surface forms the buried drain oxidation. Layer method wet oxidation. Please refer to the manufacturing method of the read-only memory described in the first item of the patent scope. The nitride chip stack layer is formed by a bottom oxide layer, a nitride chip layer and a sequential stack. The fabrication of the read-only memory described in item 4 of the patent is required to perform the etching process to define the steps and steps of the silicon nitride stacked layer to envelop the bottom oxide layer surface. The manufacturer of the read-only memory described in item 4 of the patent 9769twf.ptd Page 15 577151 The definition of chemical gas should be based on the process of planting plants. The process should be applied by Fan Zhongli, and should be mixed in the area after six or six weeks. In the base form, the base should be Fan Ji Luli, and the special layer should be used to apply the oxygen of the layer, such as the bottom of the stack. 7. Stack the pile and read the item in the description of β. The body's memory and memory packs are stepped and stacked II. The definition is based on the process. The etch should be etched at the end, and the professional should go to Lu Shenzhong to make it as it is. Body hermit sale = σ Weizhi's item includes the enclosing process Fan system profit engraving and eclipse, please apply to the application as its 9 methods to etch the body memory made to equal parties sold = Kou Weizhi's item Column II below includes the meaning of Bao after it has been changed to the area, and the miscellaneous process is blended into the plant shape and separated from the bottom > Step and layered oxygen, extremely pumped into the ml · il; a layer of a curtain-shaped masking area map mixed with the addition and removal of the silicified II should be used as a layered conductive case Figure 1. The body of the elementary characters on the line is to remember oneself = oral reading The memory of the body. The reading of the layered conductance plan of Baowei's quality materials is described in detail. • In the 10th method, Fan Li specially requested to apply for Rujigukou-• Read τ-χ Λΐ 2 1 Weiji C.P11 kinds of memory gate buoys are manufactured in the body of the appropriate method, and the memory includes the case 9 and the layer ^ a of the mesobar one of the case plan forming sequence; The upper base guide is shaped like a strip; the polar gate curtain and the layered electric diagram are formed into a shape-shaped upper upper guide. The bottom base gate is a Haikou ancient priest 5 Yu Yu ^ 1 9769twf.ptd Page 16 577151 VI. The scope of the application for the patent uses the patterned mask layer as the gate gate conductor layer, the dielectric layer, and the gate structure; a cleaning process is performed to clear the structure sidewall and the substrate. The surface is slightly smaller than the two sides of the gate structure. 2. As in the first method of the scope of patent application, the cleaning process includes cleaning. 1 3. According to the first method of applying for a patent, wherein the step of forming a patterned conductive layer includes: sequentially forming on the substrate and defining the conductive material layer and the patterned strip dielectric layer and a pattern 14. The first method as claimed in the patent application, wherein the etching process includes 1 5. The first method as claimed in the patent application, wherein the method for the bipolar region of the gate structure includes a patterned ion implantation process. An etching process is performed to define the strip conductor layer and the strip dielectric layer to remove the gate particles remaining in the etching process; and a source / drain region is formed in the substrate. The manufacture of the read-only memory according to item 1 uses a mixture of ammonia and hydrogen peroxide to manufacture the read-only memory according to item 1. The strip-shaped dielectric layer and the patterned strip-shaped thermal oxide layer and a conductive material Layer; thermally oxidize the layer to form a strip-shaped conductor layer on the substrate. Manufacture of read-only memory as described in item 1. Anisotropic post-cut method. The source / drain is formed in the substrate of the manufacturing side of the read-only memory described in item 1. The mask layer is a mask, and the substrate is subjected to 9769twf.ptd Page 17