TW574756B - Method for enhancing retention time of memory module and memory cell structure thereof - Google Patents

Abstract

A method for enhancing the retention time of memory module and a memory cell structure thereof are disclosed, and are utilized in an embedded DRAM process. According to the present invention, a doped region with property concentration is doped and formed in the well region beneath an oxide layer of MOS capacitor of an embedded DRAM cell and the well region on where the storage node located, wherein the storage node is electrically connected with a MOS transistor and the MOS capacitor of the embedded DRAM cell. Therefore, the threshold voltage of the MOS capacitor is decreased, and meanwhile, the leakage current from the drain to the well is decreased, so as to enhance the retention time of embedded DRAM, wherein the property concentration of the doped region is between the concentration of the well region and that of storage node.

Description

574756 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Field of the invention: The present invention relates to a method for improving the memory time of a memory and the structure of a memory cell, and particularly to the application of embedded (Embedded) In the process of dynamic random access memory (DRAM), a method for improving the memory time of DRAM can effectively improve the retention time of embedded DRAM. BACKGROUND OF THE INVENTION: As semiconductor technology advances, the size of semiconductor elements becomes smaller and smaller, and integrated circuits become more and more precise. With the development of lithography imaging technology, the line size has entered the field of sub-micro and even deep sub-micro. Moreover, the application and development of 'supplied with the popularization of various electronic instruments and devices, especially handheld electronic δ', such as communication equipment and personal electronic products, or single-chip systems in integrated circuits, etc., all require application. Memory with small volume and volume, especially DRAM or embedded DRAM, so the process of DRAM or embedded DRAM will inevitably move towards the sub-micron field. At present, the composition of general DRAM is mainly based on memory cells (CeU) for recording. Each memory cell is usually formed by matching a transistor and a capacitor to each other. However, the DRAM process, especially the embedded DRam process, has encountered many problems related to the manufacture and operation of components in the deep sub-micron field. Please refer to FIG. 1, which is a cross-sectional view showing a connection structure of a memory cell component of a conventional embedded DRAM. As shown in Figure 1, the conventional embedded 3 paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) (Please read the precautions on the back before filling this page)

574756

In the memory cell 10 of the DRAM, a p-type metal oxide type and i female golden breast + (M0S) capacitor placed in the N-type well 12 is formed, wherein the crack well 12 has an isolation structure 32, such as, τ. Shallow 1. trench isolation

Isolation; STI) structure.厶 厶 厶 士 1 金 1 gold lice + transistor 14 is mainly used as a switch. The gate layer as the gate is called & person _ Ί electrode layer 18, gate dielectric layer 20 (such as the oxide layer) ), A p-type doped i-doped region & 22 as a non-polar doped region, and a p-doped region 24 as a source. The metal oxide semi-capacitor is also implemented with p-type metal oxide semi-transistor 16 in which the gate layer% is used as the gate of the metal oxide semi-transistor (that is, as the metal oxide semiconductor): current state Upper electrode), the gate dielectric layer 28 (such as a monoxide layer) serves as the dielectric layer in the 51 φ a emulsion dry coupling 15 and the N-type well 12 under the gate dielectric layer 28 Is the lower electrode of the metal-oxide half-capacitor. Furthermore, in the first figure, the P-type doped region 22 is electrically connected to the bit line, and the P-type doped region 24 serves as the storage contact 34 of the memory cell, so that p The metal-oxide semiconductor transistor 14 is electrically connected to the p-type metal oxide semiconductor transistor 16 used as the metal-oxide semiconductor capacitor. The material of the p-type doped region 22 and the p-type doped region 24 may be a p-type stone. In the process of 0.18 micron or 0.3 micron, because the distance between the components has been greatly shortened, the channel between the source and the drain of the transistor is greatly shortened. This short channel effect will easily cause pMOS devices. The phenomenon of Hot Hole Effects occurs, or the phenomenon of Hot Electron Effects occurs in NMOS devices, P The gate of the MOS element loses the ability to control the switching of the PMOS element. In order to solve the hot hole effect or thermionic effect caused by the short-channel effect of the metal-oxygen half element, a slight paper size is often applied to the Chinese National Standard (CNS) A4 Specifications (210 × 297 mm) ..... · 1: Pack: (Please read the precautions on the back before writing this page) -Order ·% Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economy 574756 A7

Order

574756 V. Description of the invention (The voltage signal of vg is slightly oscillated by the metal-oxygen half-electricity, so that when Vg is equal to or greater than vt, the operation of P-type galactophore 1: crystal 6 loses the electrical characteristics of the capacitor. (In simplified iGn Mode) Electric second: The conventional improvement method shown in Figure 2 is based on the gate dielectric sound of the "Golden Oxygen Half Day Sun Body 16" ... ¥ g 28 N-type well 12 In the position, doping: the p-type semiconductor material with an appropriate degree of inertia is formed to form a ρ · type doped region 40, and the electrical envoy of the storage contact 34 and the P-type metal-oxide semiconductor transistor 16 The electric eel more easily flows through the storage contact 34 to the second-type metal-oxide-semiconductor 16 used as a capacitor, which improves the ability of the p-type metal-oxide-semiconductor 16 to store charge when it is used as a capacitor. However, the habits described above Knowing the improvement methods, both failed to reduce the starting voltage of the p-type metal-oxide semiconductor transistor 16 used as an electric valley device and reduce the leakage current of the custom storage contact 34 to the N-type well 30 by 30. Effectively improve the memory time of the embedded DRAM. Purpose and summary of the invention: In view of the above background of the invention, with the advancement of semiconductor technology, integrated circuits are becoming more and more precise. At the same time, with the popularity of various electronic equipment, the demand for DRAM or embedded DRAM is rapidly increasing. However, due to semiconductor components The size is getting smaller and smaller, making the embedded DRAM manufactured by the process of 0.10 microns or even less than 10 microns, the hot hole effect phenomenon or hot electron caused by the short channel effect of the gold-oxygen semi-transistor element in the memory cell. The effect phenomenon is very serious, which affects the operation of the transistor element. The solution is to use a slight doping to reduce the phenomenon of hot hole effect or thermionic electrons. This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm). Printed by the Intellectual Property Bureau Employee Consumer Cooperative 574756 A7

V. Description of the invention () Effect phenomenon. However, in the process of 0.10 micron or below, the lightly doped method will further shorten the channel between the source and the drain. Therefore, the lightly doped method has unavoidable disadvantages in implementation. On the other hand, because the embedded DRAM uses a very low operating voltage, the voltage applied to the capacitor in the memory cell is also very low and is close to the starting voltage, so that the power valley 1 of the metal-oxygen half capacitor is greatly reduced. Reduced memory, cell memory time. The main purpose of the present invention is to provide a method for improving the memory time of a memory and a memory cell structure, which are applied in an embedded DRaM process. After the N-type well is manufactured, an appropriate photomask is used as a mask, and doping or implantation methods are used to form N-doped regions in the N-type well with a lower concentration than the N-type well before forming the memory cell. The PMMOS transistor and the Mos capacitor used as a switch, and the storage contact for the electrical connection between the PMOS transistor and the MOS capacitor, and the lower electrode of the MOS capacitor are placed in a doped region to reduce the MOS capacitor. The initial voltage and the leakage current from the storage contact to the N-well achieve the purpose of improving the memory time of the embedded DRAM. In addition, the mask used when the N-doped region is formed by doping. The mask can be implemented by adjusting the initial voltage of the N-type metal-oxide semiconductor transistor, or other existing masks are used as masks according to different design layouts. Therefore, the cost of implementing the present invention is cheap and simple. According to the above-mentioned object, the present invention provides a method for improving the memory time of a memory, which at least includes: providing a substrate; forming an n-type well on the substrate; and forming at least one N-type doped region in the N-type well. ； Yu type 7 This paper size is applicable to China National Standard (CNS) A4 specification (21〇 × 297 mm) (Please read the precautions on the back before filling this page)

574756 A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the People ’s Republic of China, at least one isolation structure; forming a well on the substrate and this at least -... area; in: electricity :: part two gates Layer and gate dielectric layer, so that at least the N-type well and part of the exposed matter are combined with the ns-wake mountain doped region; and the N-type number 4 part and the exposed part of the N-doped region The formation of a complex = doped region 'wherein ... the doped region is placed in the N-type doped region, and "

Between the P-type well and the P-type doped region. The redness of the red-doped region is between N-type devices: the outer 1 can form h-type doped regions on both sides of the P-type doped region and the gate: b: step to reduce the leakage current from the p-type doped region to the N-type well The general material of the electrical layer is a dream dioxide, isolation structure trench isolation (STI) structure. The line also provides a memory cell which at least includes: a metal-oxygen half-capacitor II and a metal-oxygen half-capacitor's lower electrode system located in the n-doped region of the N material, where the semiconductor material concentration of the N-doped region is greater than that of the n-type The semiconductor of the well = low material concentration; and the P-type metal-oxide-semiconductor crystal, in which the drain and source of the p-type metal-oxide semiconductor are composed of the first P-type doped region and the second p-type in the N-type well, respectively. It is composed of a type doped region, and one of the p-type doped region and one of the two p-type doped regions serves as a storage contact electrically connected to the metal-oxide half-capacitor, and some of the storage contacts are located at N _ In the doped region. In addition, 'the first p-type doped region includes several first-type doping regions on both sides, and the second p-type doped region includes several second P-type doped regions on both sides = domain 0 This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) 574756 Printed by A7, Consumer Property Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs 5. Description of the invention (Detailed description of the invention: / The method provided by the present invention for improving the memory memory time is based on Before forming the gate dielectric layer (such as the dioxide layer and the dream layer) on the substrate, by using a suitable mask for blocking propagation, doping or implantation, etc., in some n-type wells: the concentration is higher than N The low N_ area of the model well, and then the subsequent embedded ^ DRAM process steps, and when the metal oxide half capacitor is formed and used as a switch = type metal oxide half transistor, the closed-electrode of the metal oxide half capacitor The lower electrode under the electrical layer is placed in the N- region, and the storage contact for the metal-oxide half-capacitor ^ type metal-oxide semi-transistor electrical connection is also placed in the N_ region. The following is a detailed step description. ^ Please refer to FIG. 3 to FIG. 1G are diagrams respectively showing a system to which an embodiment of the present invention is applied. A cross-sectional view of the element structure of the process. As shown in FIG. 3, firstly, a substrate 100 is provided, and then a vapor deposition method, such as a chemical Z-phase deposition method (Chemical Vapor DepOsitiOn; CVD) or other binary method is used, An N-type well 102 is deposited on the substrate 100. Next, as shown in FIG. 4, when doping or implanting a semiconductor material 104 having a lower concentration than the n-type well 102 to the N-type well 102 (such as doping an appropriate concentration) P-type semiconductor material), using a suitable mask 12 (such as a mask to adjust the initial voltage of the N-type metal-oxide semiconductor transistor as a mask) to block part of the half = bulk material 104, so that A plurality of ^ regions 106 are formed in the N-type well 102, and only one N-doped region 106 is shown in Fig. 5. Furthermore, the concentration of the N-type semiconductor material in the ^ -doped region 106 is determined by Mesowell = Concentration and p-type semiconductor material in the subsequent process steps (or p + "This paper size is applicable to Chinese National Standard (CNS) A4 specifications ⑽χ 聊 公 爱) (Please read the precautions on the back before filling this page}

574756 Printed by A7 B7, Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs, V. Description of the invention () V-body material) between the concentration of the doped region 118 (shown in Figure ι), such as the concentration of the N-doped region 106 It is between ι · 〇Ε12 and 5E13. Please refer to Fig. 6, forming N-type wells 102. After forming multiple N, hetero-theta regions 106, the N-type wells with N-doped regions 106 can be processed by lithography etching process and other methods. 10 is defined, and then a deposition and planarization process is used to form a plurality of isolation structures 10 in the N-well 102 (only one isolation structure is shown in FIG. 6). This isolation structure can also be called Shallow trench isolation an) structure. Then, as shown in FIG. 7, a gate dielectric layer 110 (such as a silicon dioxide layer) is formed by a chemical vapor deposition method to cover the isolation structure 108 and the N-type well 102 having a doped region 106. A gate layer 112 (such as an N-type polycrystalline silicon layer) is formed by using a method such as chemical vapor deposition to cover the gate dielectric layer 1 10. After the gate layer 112 is formed, for example, a photoresist material is formed on the gate layer 1 12 by a coating method, and a part of the photoresist material is removed by a lithography process and the like, and a part of the gate is exposed. The electrode layer 112 is used to form a photoresist layer 114 having a memory cell arrangement pattern on the gate layer 112, as shown in FIG. 8. Please refer to FIG. 8 and FIG. 9, and then use the etching method, and use the light following layer 1 14 as a mask to etch the gate layer 丨 2 and the gate dielectric; 1 1 0 'to form a plurality of The opening 116 is exposed, and a part of the n-type well 10 is exposed, and then the photoresist layer 1 1 4 is removed by an etching or planarization process.凊 Refer to Figure 10 ’and then use doping or implantation in N-type wells. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling in this page >

A7

574756 2 The exposed part forms a plurality of doped regions 118 of the semiconductor material M let r 1 cow conductor material (or P4: conductor material 枓), which is a concentration between 1E15 and 1 pka X i 1 8 … Between. In addition, these doped regions U8 use Babie as the source and sum of P-type metal-oxygen half-knife and P-type metal-oxygen half-ray 2 in the memory cell, with oxygen + electric sun body 124 and metal oxygen half capacitor 126 Connected eroded contacts ⑵. Moreover, as shown in FIG. 10, the storage contact == ^ doped region 1G6 in 102, and the metal-oxygen half capacitor 126 is also placed in the N-doped region 106 in the N-type well 102. . Because the concentration of the N-type semiconductor material in the doped region 1 () 6 is between the concentration of the N-type well 102 and the concentration of the doped region 118 having the p-type semiconductor material (or p + type bulk material), and the point! . Both the lower electrode of the metal-oxide half-capacitor 126 and the lower electrode of the metal-oxide half-capacitor 126 are placed in a small doped region ι. The reason is that the energy level of the material interface in the metal-oxide half-capacitor 126 changes when the memory cell operates, so that the metal-oxide half-capacitor H The starting voltage of 126 is reduced, and according to the experimental data, the starting voltage of the metal-oxygen half capacitor 126 can be decreased by 200 mV or more after applying the present invention. At the same time, the leakage current 128 from the storage contact 122 to the small doped region 106 to the N-type well 102 is also lower than the leakage current from the storage contact 122 to the N-type well 102. Therefore, via the storage contact 122 The current flowing to the metal-oxide half-capacitor 126 is increased. In summary, the memory time of each memory cell in the internal memory DRAM is increased. Especially when the memory of the memory cell is “0”, the memory cell ’s Memory time has been greatly improved. Furthermore, since the mask used to form the N-doped region 106 is not required, this paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page}

Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 574756 A7 V. Description of the invention () Specially made, you can use the existing photomask to adjust the N-type metal-oxygen semi-electrical starting voltage as a mask, or use a different design and Layout and other masks 'Therefore, the steps for implementing the present invention are simple and inexpensive, and the factory refers to FIG. 11' and FIG. 11 is a structural wearing view of a component manufactured by applying another embodiment of the present invention. In addition, it is also possible to: p + -type doped region 118 on both sides of the type + conductor material to form a p-type exchange binary-to reduce the doped region 1 ... type one: V :: the invention-the advantage is to provide _ a kind of improvement notes The dielectric of the memory time ... The lower electrode under the gate layer of the two metal-oxide half-capacitor is placed in the N • area, so the starting voltage of the metal-oxide half-capacitor test can be reduced, and it flows from the storage contact to the metal-oxide half-capacitor. Electricity &

The memory time of each memory cell is increased, and the memory time of the memory cell is “0,”. At the same time, another advantage of the present invention is that the electricity between the metal-oxide half-capacitor and the p-type semi-electric crystal is electrically charged. The storage contact of the sexual connection is placed in the ~ area, and the leakage current between the stored contact and the N-type well is greatly reduced, so the memory time of each memory cell is also improved, which makes the embedded dram Memory time increases. Another advantage of the present invention is that special equipment is needed when forming N-zones in N-type wells, which can be achieved only by using the appropriate light available as a mask when changing the hybrid semiconductor material to the n-type wells. The implementation method is simple and low cost, and can be easily produced with a long memory time and high reliability. 12 paper-size towels «frequency eNSM4g_2l () x297_

.......— :: ά: (Please read the notes on the back before filling this page) Order ·

I 574756 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Embedded ram. As understood by those familiar with this technology, 'The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the invention or the patent application for the invention; all others completed without departing from the spirit disclosed by the present invention Equivalent changes or modifications should be included in the scope of patent application described below. Brief description of the drawings: The preferred embodiment of the present invention has been described in more detail in the preceding explanatory text with the following figures, where: Figure 1 is a diagram showing a connection structure of a memory cell component of a conventional embedded DRAM Fig. 2 is a cross-sectional view showing a connection structure of a memory cell element of a conventional embedded DRAM; Figs. 3 to 10 are parts showing a manufacturing process to which an embodiment of the present invention is applied; Structural cross-sectional view; and FIG. 11 is a structural cross-sectional view of an element manufactured without applying another embodiment of the present invention. Description of drawing numbers: 10 memory cells, 12 N-type wells, 14 P-type metal-oxide semiconductors 16 P-type metal-oxide semiconductors 18 Gate layer 20 Gate dielectric layer 22 P-type doped regions 24 P-type doped regions 26 Gate layer 28 Gate dielectric layer 30 Leakage current 32 Isolation structure 13 This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page)

574756 A7 B7 V. Description of the invention (34) Storage contact 36 Channel 38 P-type doped region 40 P-type doped region 100 Substrate 102 N-well 104 Semiconductor material 106 N-doped region 108 Isolation structure 110 Gate Dielectric layer 112 Gate layer 114 Photoresist layer 116 Opening 118 Doped region 120 Mask 122 Storage contact 124 P-type metal-oxide semiconductor 126 Metal-oxide semiconductor capacitor 128 Leakage current 130 P-type doped region Ministry of Economic Affairs Printed by the Intellectual Property Bureau Staff Consumer Cooperatives 14 (Please read the notes on the back before filling out this page)

This paper size applies to China National Standard (CNS) A4 (210X297 mm)

Claims (1)

The scope of 574756 A8 B8 C8 D8 and Shenyan patent includes a method for improving the memory time of the memory. The method at least provides a method of forming a first conductive space in the electrical type doped region and a first conductive space. And at least one first substrate;-a first conductivity type well in the substrate; at least one first conductivity type doping region is patterned in the _ conductivity type well-gate dielectric layer and _ gate electrode Layer at the-# electric type well and part of the at least one type of doping area in the exposed part A of the substrate; and at least the first conductive area and the exposed part of the conductive type well The concentration of the at least one first conductivity type doped region in the plurality of second conductivity type dopings is between the concentration of the type well and the concentration of the second conductivity type doped regions. At least one of the conductive type doped regions is disposed in the conductive type doped region. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2. The method for improving memory memory time as described in item 1 of the scope of patent application, wherein the first conductive well is an N-type well, and the at least one first conductive well The type-doped regions are at least one N-type doped region, and the second conductivity-type doped regions are a plurality of P-type doped regions. 15 This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page) 574756 Patent application scope • The method for improving memory memory time as described in item 2 of the patent application scope, which further includes forming a plurality of P + type dopings on both sides of each of the second conductivity type doped regions. region. 4 · The method for improving the memory time of a memory as described in item 1 of the scope of the patent application, wherein the first conductivity type well is an N type well, and the at least one conductivity type doped region is an N-type dopant. Regions, the second conductivity type doping regions are a plurality of P + type doped regions. 5. The method of improving the memory time of a memory as described in item 1 of the scope of the patent application, wherein the step of forming the at least one first conductivity type doped region is a doping step. 6 · The method for improving the memory of a memory as described in item 5 of the scope of the patent application, wherein a step of applying a mask to block the semiconductor doped to a portion of the first conductivity type well is performed when the push-in step is performed. material. 7. The method for improving the memory time of a memory as described in item 6 of the scope of the patent application, wherein the mask is a photomask, and the photomask is used to adjust the starting voltage of the N-type metal-oxide semiconductor transistor. A method to improve the memory time of the memory. This method includes at least 16 paper sizes that are applicable to the Chinese National Standard (CNS) A4 specification (210X297 public love).-Binding (please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 574756 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 ____D8 The scope of the patent application provides a substrate; an N-type well is formed on the substrate; at least one N-type is formed The doped region is in the N-type well; a patterned gate dielectric layer and a gate layer are sequentially formed on the substrate, in which a portion of the N-type well and a portion of the at least one N are exposed. _-Type doping regions; and forming a plurality of p-type doped regions on the exposed portion of the N-type well and the exposed portion of the at least one N-type doped region, wherein the at least one N-type The concentration of the doped region is between the concentration of the n-type well and the concentration of the p-type doped regions, and at least one of the P-type doped regions is placed in the at least one N · type Within the doped region. 9. The method for improving the memory time of a memory as described in item 8 of the scope of patent application ', which further includes forming a plurality of P + -type doped regions on both sides of each of the P-type doped regions. 10. The method for improving the memory time of a memory according to item 8 of the scope of the patent application, wherein the step of forming the at least one type doped region is a doping step. 11. The method for improving the memory time of a memory as described in item 10 of the scope of the patent application, wherein the doping step is performed by applying a mask to block the semiconductor material doped to the portion of the N-type well. 17 This paper is oriented toward Chinese National Standard (CNS) A4 (21 () χ 297 public love) (Please read the precautions on the back before filling in this page) 574756 A8 B8 C8 D8, patent application scope 12 · A kind of memory cell, the memory cell includes at least:-metal-oxygen semi-capacitor, the lower electrode of the metal-oxygen semi-capacitor is located in one of the N-doped regions in the well, where The half body of the N-doped region = the material concentration is lower than that of the semiconductor material of the N-type well; and, a p-type metal-oxide-semiconductor, wherein a drain and a p-type metal-oxide-semiconductor are The source electrode is composed of a first p-type doped region and a first-type doped region respectively located in the N-type well, and the first p-type doped region 2 and the second p-type doped region One of them serves as a storage contact that is electrically connected to the metal-oxide half-capacitor, and part of the storage contact is located in the & doped region. ! 3. The memory cell described in item 12 of the scope of patent application, where the first? Both sides of the type P doped region further include a plurality of first p + type doped regions. The sides of the second P type doped region further include a plurality of second p + type doped regions. 0 (Please read the notes on the back first Write this page again} Loading, ·, τ Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs This paper is printed in accordance with China National Standard (CNS) A4 (210 × 297 mm)