TW566021B - Method of and structure for transferring stored digital parallel data of multiple bits of data stored in a first data register - Google Patents

Abstract

A global architecture for a serial link connection between two cards which must transmit data across wired media is provided. The architecture comprises a transmitter portion and a receiver portion. The transmitter portion includes a structure and circuitry to take digital bits from a first bit register, such as for example, an eight-bit register or a ten-bit register, and convert these bits into serial analog transmission to the receiver portion. The receiver portion includes a structure and circuitry to sample the analog transmission of the original digital bits and reconvert the analog serial signal of the digital bits corresponding to the original digital bits and store them in a second bit register comparable to the data stored in the original register from which they were selected.

Description

566021 A7 B7 V. Description of the Invention (!) Related Inventions This application has a provisional patent application serial number 6 0/2 62,3 5 8 as filed on January 26, 2001 "Global Architecture" for

The advantages of Advanced Serial Link "(Case No. RAL920010004US1). This application is about the following patent applications under review ... _ The serial number of the filed application No. 1" Unified Digital Architecture (Uniform Digital Structure) "(pending case number RAL920010003US2); _The serial number of the application filed-___" Analog Unidirectional Serial Link Architecture (analog unidirectional serial link structure), "(pending case number RAL920010005US2) ; And _ the number of the application filed _

Apparatus And Method For Oversampling With Evenly Spaced Samples "(pending case number RAL92001001 1US2) is hereby incorporated by reference. FIELD OF THE INVENTION The present invention relates generally to a card The registers in the ASIC (Special Application Integrated Circuit) chip on the serial transfer data to the registers in the ASIC chip on another card. More specifically, for serial transfer of this data, The data is converted from a parallel digital form to a serial analogue = formula to transfer data from one ASIC to a second ASIC, and then convert it to parallel digital form in the first ASIC. When the data is transferred, BACKGROUND OF THE INVENTION Sequence data must be transmitted via a wire as a transmission medium. The transmission and reception area is based on paper standards (CNS).

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-4- 566021 V. Description of the Invention (2) The domain includes chip circuits interspersed with each other as an interactive connection between the cards. The transmission medium may be a printed circuit board, a connector, a fixed planar circuit, an optical fiber, or a set of sigma wires. Its parent interconnection includes its own power, data sources, or these functions that can be driven by the host core group. This data is typically transmitted via a parallel data bus such as ISA PCI 'PC-IX. This parallel connection, σ disadvantage t & slows the data transfer rate to improve the performance of the microprocessor, causing the data conversion bandwidth to typically exceed the input / output conversion rate. Similarly, the number of ASIC inputs / outputs is also High, in addition to this, the system: the number of parallel data buses used in the integration of input / output is also high. After taking out, the entire system tends to high costs with the use of parallel data buses. Relevant skills show that trying to use pain ^ L 扪 扪 多样化 序列 序列 设计 序列 多样化 多样化 多样化 多样化 多样化 多样化 多样化 多样化 多样化 多样化 多样化 多样化 多样化 难题 难题 难题 难题 = Difficulties and disadvantages ^. For example ... Some use a low-carrier oscillator Γ / produce AP) # of the group, and quot; others use linear compression / decompression and digital Zhao: Erli technology in the frequency module. Others use linear (analog) phase-to-phase benefits to recover subsequent carrier signals. It is better to limit the passband of the frequency bandwidth than to use its 4 "box searcher to enjoy the frequency μ and the frequency is not restricted .... The signal is not divided during the way of the invention Summary of the invention The invention includes a sequence between two cards Link communication uses a line as a medium to transmit data. This 仏 ·. Structure requires a receiver. The transmitter includes a circuit and; = includes the use of a transmitter and a device to obtain digital bits, for example, such as; From the bit register 'and convert these bits to serial analog transfer: =:? = -5- This paper size is applicable to China Standards (CNS) M specifications (plus> <297 public shame) 3 5 The invention description device includes a structure and a circuit, | V &amp; ψ ^. Pass the analogy of the original digital bits to the margin of Pei, and then convert 誃 赵 办 # — G 得 轮 位 位 亓, 'l &gt; The analog sequence signal of / bit is the original number. # '亚 &quot; The data selected by the father is stored in the original register and the data is stored in a register. 1 is the intersection of the lines between a high-order graphics receiver; Figure 2 is a block diagram; and 'It is used to display sequence links. The transmitter part is connected to the connection; ^ It is used to show the operation of the transmitter circuit of the structure Figure 3 is a block diagram to show the operation of the receiver circuit of the structure. The diagram of the present invention shows the south-order graphic of the interactive connection between ASICs. One side of the connection is a transmitter and the other is a receiver, and there are different transmitters and receivers for transmitting information. The invention is as above. As shown, it can be implemented in many different appearances, such as a combination of printed circuit boards, connectors, fixed plane circuits, optical fibers or cables. As shown in the figure, this implementation places a hard line on a fixed plane on the transmitter part Between the receiver and the receiver. As can be seen in Figure 1, a pair of printed circuit (pc) cards 12a and 12b are installed on the fixed plane 10. Each circuit card 12a and 12b provides an ASIC chip 1 and 14b, respectively. The present invention is interactively connected. Each asic 14a and 14b has at least one transmitter 16, and as shown in the figure, 'has two or more transmitters. Similarly, each ASIC 14a and 14b has at least one receiver.18, and as in Example 8 Shu has two receivers, as shown above or as shown -6 - This applies China National Standard Paper Scale (CNS) A4 size (210 X 297 mm) 566 021

Depending on the number of transmitters 16, more than two receivers are provided. Generally speaking, because the flow of data is two-way, and the communication here is single::, so the transmitter 16 and the receiver 18 need to be provided in a pair-wise manner. Each transmitter 16 on 14 "14b contains a unidirectional hardware circuit serial sink * The row 20 is connected to another ASIC 14a or the transmitter 18 of the ASIC. = For this, two-way communication is required by each ASCU4a and The pairing with the receiver is done on 14b. In short, each transmitter 16 stores its parallel digital data 24 (Figure 2), and the transmitter 16 is stored in an ASIC register, such as 1 to convert this parallel digital The data is stored in the sequence analog form, and the data is transmitted to the opposite a register 18 through the serial bus 20 in the sequence analog form, such as 14b. The register 18 converts the analog asynchronous sequence = step parallel digital data. The digital register is used to store the register 68 (Figure 3) of the library. Therefore, the sequence link function here is to obtain parallel data in the temporary piano in an efficient way, and use the asynchronous sequence analogy 0π U. Xihai tribute material is synchronous and parallel digital data. 了 Inch Dan conversion is now shown in Figure 2 'as a transmitter i 6 circuit function diagram, it can be seen that the transmitter 16 contains a., L ^ ^ Fan Zhicun Zhai 24, although the size of the temporary register can be used However, this temporary ', ..., bucket, 丄 a-丄 飞仔 are typically eight-bit special register 24 is a ten-bit temporary register. Under the synchronous control of counter 38, One device 26 sequentially selects the person k from the register 24 at one time, and the -bit 70 selects one person k, so that the two-bit data can be read from the register 24 overnight. However, in temporarily

566021

"The number of bits in 24 must be an evenly divisible number, because in the register with ten digits, this number can be one, two, or five, and in the two-bit register This number can be two or four, and two bits are preferred. Each of them is selected by the selector 26 · Crying Strong 4 Su Yi "The two bits of the intelligent storage k are provided to the position P-ι The lock 2-8a or 28b is also selected and transported under the synchronous control of the counter 38 to 70%. Under the synchronous control of the counter 38, these bits then ask for the lock ... and the bird is transported to the multiplexer 30, and then to Flash of One Yuan. 32. The bit data is transported to the driver equalizer 1 by the one-bit latch 32, where the digital bits converted from the latch 32 and including the converted digital bits are transmitted to the sequence analog signal output 3 5 in. A single-phase full-rate phase lock circuit 36 provides the action of the clock (Cl0ck) latch 32 and drives the equalizer 34, and actuates the counter 38 and turns to the multiplexer 30, the latch 28a, and 28b. Select 26 and ten-bit register 24. The phase locked loop 36 has an input of a clock signal generated by the internal or external clock 40 as shown in the figure. The function provided by the counter 38 is to synchronously execute the extraction of bits from the register 24 via the selector 26 for transport to the latches 28a & 28b. The counter also forms the synchronous transport of the bits from 28a, 28b to the multiplexer 30. To flash lock 32. The digital bits received synchronously in the driving equalizer 34 are converted into a sequence analog signal 35. Functions of many parts of the transmitter 16 such as the register 24, the selector 26, the latches 28a and 28b, the multiplexer 30, the latch 32, the single-phase full-rate phase lock loop 36, and the counter 38, and a more detailed description The serial number of the application filed under __ "Unified Digital Architecture (Unified Digital Architecture)" (pending case number RAL920010003US2) and mention -8- This paper size applies to China National Standard (CNS) A4 specifications ( 210X 297 mm)

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Yuan 566021 A7 B7 V. Serial No. _ "Analog Unidirectional Serial

Link Architecture (analog unidirectional sequence link structure) "(pending case number RAL 92000015005uS2), which is hereby incorporated by reference. Analog output 35 is placed on the serial bus 20. , Which is transmitted in asynchronous form to receiver 18 at the end of another serial bus 20. As shown above, receiver 18 receives the asynchronous analog signal and converts it into a synchronous digital parallel signal, corresponding to a digital bit The register 24 is stored in the receiver. 8. Now referring to Figure 3, it is shown to convert the non-synchronous analog sequence. The number 35 is the synchronous digital parallel digits to store these bits in the receiver. Block diagram of the structure and circuit function of 18. The sequence analog asynchronous signal 3 is received by the signal receiving member (member) 50 and the analog signal is sent to the single sample latch 52. In the sampling interlock 52, in a data Under the control of a marginal debt and electricity = 58 and a multi-phase half-rate phase-locked loop 60, the analog signal is converted into a digital signal through the tool of the phase inverter 54. Under this sampling, the multiple Sampling, the f material The two ends are: Asia converts the lean material from analog signals to parallel data bits. It is better to use 'multi-sampling' to measure the approximate two points of the data bits for each result It is to convert the non-synchronous analog sequence signal to select "2 to digital output 63" and transport it to displacement 64 in two-bit increments. Actuated by the phase inverter 54 °-Operates in the shift register with the two digits it rotates. The digits are stored in the L register, such as the ten-digit sync signal to the ten-digit buffer. The operation details of this receiver 18 are described in detail in the sequence number of L out, I Γ Ϊ,-^ UAnal〇g Unidirectiona ^ ia! (Referred to as the structure of analog unidirectional sequence connection) ,, (pending trial)

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566021

Case number RAL920010005US2) and _ number of the application filed "Apparatus and Meth〇d f〇r 〇versampHng ～ 池

Spaced Samples (apparatus and method for oversampling of uniform space samples), (pending case number RAL9200100liUS2), the ones mentioned here are included in the spring test. 'So' if parallel data is stored in the ten-bit register 24, the storage of the ten-digit digit 7L is converted by the transmitter i 6 into an asynchronous analog sequence signal 35 and is transported asynchronously to the bus 2 〇, the asynchronous analog signal h

Ik is then reassembled by the receiver 18 into the original ten-bit parallel digits in the register 68. This patent specification has incorporated its embodiments in detail to describe the present invention. Those skilled in the art can make many alternatives, modifications and changes from the foregoing experience. Accordingly, within the spirit and scope of the patent scope of this application and the scope of the subsequent patent application scope ', the present invention also intends to include many alternatives, queries, and changes attached thereto. -10- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 public love)

Claims (1)

5 ^ € Q2l ------- _ &amp; Miscellaneous 3 strong patent applications petition + + ^^ ## Replacement (July 1992) 1. A method of transferring parallel data stored in a first storage digit, = multi-bit data in the device The stored data is transmitted from one transmitter to the receiver of a kind of hardware circuit, including: ° Passed to a receiver, and the step-by-step ratio of the stored data in the library is converted into sequence data in the library. It is not necessary to receive m steps of ground material ratio signals through the hardware line conductor to = the data stored in the first data register in the transmitter, = the same v-sequence analog signal as the synchronous digital parallel data on the connection Reduce and detect the two edges of the data in the asynchronous sequence analog signal to convert to parallel data bits. 2 ·!: = The method of item 1 of the patent scope, in which digital parallel data is temporarily stored as the middle item from the-data to at least one single-bit flash lock. Yuan Jiang 3. Rushen: Special? The method of the second item, wherein the data output from the first register of the transmitter is two bits at a time, and each data bit goes to the first and second single data bit registers respectively. 1 from each of the first and second single-bit data registers to the third single-bit data register, and the clocks of the two additional data bits written subsequently are added to the first and second single-bit data registers. The register and the third single-bit data register until the data bits in the first register are read out. 4. The method according to item 3 of the scope of patent application, wherein the bits from the third single-bit register are converted into a single analog sequence signal of the data. 5. The method according to item 1 of the scope of patent application, in which the paper size in the first register is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) Supplement Λ8 Β8 C8 The data consists of eight or ten digits. 6 · If the scope of patent application is the first! Term method, wherein the clock signal is used to convert the analog sequence signal into a digital signal. 7. The method of claim 3, wherein the analog signal is converted into two-bit signals in the receiver and transmitted to a shift register and then stored in a second data register. Memory. &amp; A method such as item D of the M patent scope ', wherein the bit in the shift register is synchronously transmitted from the service register to the second data register. 9. The method according to claim M, wherein the edge is obtained in the same manner. 10. The method of claim 9 in the scope of patent application, wherein the multiple sampling is used to determine the approximate center of the generated data bit. U · A structure for transferring the stored digital parallel data of the multi-bit data stored in the -data register, which includes a transmitter and a receiver connected via a hardware line conductor; A circuit for synchronously converting the surviving digital data into a serial analog data signal; a circuit for transmitting the serial analog signal to the receiver asynchronously over the hardware line conductor; and a circuit corresponding to the transmitter The data stored in the first data register 'restores the asynchronous sequence analog signal as synchronous digital parallel data in the receiving II', where the two edges of the data in the asynchronous sequence analog data signal are measured for conversion to parallel Data bits. -2- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 public directors) GT21 A8 B8 12. The structure of the 11th item of the ΓΓΓ range, which includes at least one single-bit π latch and a circuit for self-m times, ± cautious B to read the digits from the first shell register Parallel to the at least one single bit interlock. 13 · :: Please ::: The structure of item 12 of the range, which includes the-, the second, and the ;;: Γ bit register ', and the-register from the transmitter is two at a time After each data bit reaches the first bit register, the first and second single registers are stored in the third single-bit data register: The clock of each data bit is added to the-and the second one is in the 70th period, and the third single-bit data register is read until all the data bits in the first register are read out . 14 .: Application: The structure of item 13 of the scope of interest, which includes a single-analog sequence signal that converts the bit into the data in a register, which is stored in the first register. The structure of item 1 is composed of eight or ten digits. 16. The structure of item &quot; in the scope of patent application, which includes a clock signal to convert the analog sequence signal into a digital signal. 17. The structure of item 11 in the scope of patent application 疋 Register and circuit are sent in the receiver to the two one-bit bits of a shift register in the second data register. , Which contains a second data bit in order to convert the analog signal into a bit signal and store the conversion in which the transfer in the shift register is transferred to the second data buffer 18. If the scope of patent application is 17 Structure, the bit is synchronously fed from the shift register 566Θ24 to ya '' λ. Η η, ~ a AB c D 々, patent application scope. 19. The structure according to item 11 of the scope of patent application, which includes a circuit for obtaining the edge from multiple sampling. 20. The structure of item 19 in the scope of patent application, in which the circuit of the edge obtained from the multi-sampling can determine the approximate center of the data bit of the result. -4- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)