TW565882B - Gate structure and its manufacturing method, and MOS device having the gate structure - Google Patents

Abstract

The present invention provides a kind of gate structure that includes the followings: the first part of polysilicon layer for the bottom layer; and the second part of polysilicon layer for the top layer. In addition, the invention also includes the manufacturing method of gate structure and the transistor device containing the invented gate structure.

Description

565882 V. Description of the Invention (1)-Metal Oxide Semiconductor Transistor (Metal-0xide_Semic〇nduct〇r

Transistor (MOS) is a very important basic electronic component in VLSI technology. It is mainly composed of three basic materials, namely a metal conductor layer, an oxide layer and a semiconductor layer. It also includes two semiconductor regions located on both sides of the gate transistor and electrically opposite to the semiconductor substrate, which are called source and drain. At present, when the gate transistor is manufactured, the metal conductive layer is mostly composed of doped polycrystalline silicon (p〇lysiHcOn) and metal. This structure is also called polycrystalline silicon (p〇lycide). The la-lc diagram and the ia-ic diagram are flowcharts showing the conventional steps for manufacturing the gate. Referring to FIG. 1a, first, a semiconductor substrate 101 is provided. An isolation region 102 is formed on the semiconductor substrate 101. The isolation region 102 is used to isolate an active region on the semiconductor substrate 101. An active area on the semiconductor substrate 101 is sequentially formed with an oxide layer 103 and a polycrystalline silicon layer 104, and the polycrystalline silicon layer 104 is ion-implanted to form a P-type or N Type of conductive layer. Wherein, the isolation region 102 is, for example, a shallow trench isolation layer; the oxide layer is, for example, a dioxide, which is used as a gate oxide layer; the ion implantation is, for example, arsenic (As) ions or boron (B ) Ions for implantation. / Please refer to FIG. 1 b. After ion implantation of the polycrystalline silicon layer 104, a patterned photoresist 105 is formed on the conductive layer 104. The patterned photoresist 105 will cover the active area of the semiconductor substrate 101. On the part that wants to form the gate. Refer to Figure lc, “Receiver”, using a patterned photoresist as a mask, and anisotropically etch the polycrystalline silicon layer 104 and the oxide layer 103 to form the gate electrode 10 ″ and close it.

0503-7898TWF (N); TSMC200M494; claire.ptd page 4 565882 V. Description of the invention (2) — ------- Advance, = layer 103a. If the semiconductor substrate on both sides of the gate is 10 mils in the future, a source-drain region (not shown) will be formed, and the inclusion of the gate region becomes a so-called transistor structure. Polycrystalline is a kind of multi-crystal The phenomenon of co-construction of crystals is composed of a variety of: silicon crystal grains with different directions. The polycrystalline material commonly used in the semiconductor industry for gates is a kind of polycrystalline silicon, which is arranged in a columnar structure. Because :: [Said: The relationship of the layer structure, when the polycrystalline silicon layer is formed on the semiconductor substrate ", the gate, the surface of the polycrystalline silicon layer in contact with the semiconductor substrate will be rough :: smooth. Subsequent voltage is applied to the gate 104a to allow electrons to pass through the source: When the channel below the gate 104a reaches the drain, the uneven electric field caused by the uneven interface between the gate 10 "and the semiconductor substrate 101 will cause The electrons in the channel are affected, 'resulting in a change in the travel path of the electrons and reducing the electrical characteristics of the electricity. At the same time, in order to increase the density of the components, the size of the components will be minimized to increase the number of components; however, when the component size When being shrunk, the poly gate depletion effect (PED) will become severe. The so-called poly gate depletion effect is that when the device size is reduced, the proportion of empty regions between the metal layer and the oxide layer will be reduced. Increasing the speed at which the electrons move forward will reduce the operating speed of the pieces. In view of this, the object of the present invention is to provide a gate and a method for manufacturing the gate, by A gate having a relatively smooth surface in contact with a semiconductor substrate is manufactured to reduce the influence on the electron path in the channel. Another object of the present invention is to provide a gate including the above gate. Polar structure gold 565882

Oxyde semiconductor (metal oxlde semiconductor) device, this device has low polycrystalline silicon gate depletion effect and high carrier activity characteristics. 8. According to the foregoing object, the present invention provides a gate structure formed on a semiconductor substrate, including: a first part of a polycrystalline silicon layer, which serves as a bottom layer; a polycrystalline silicon layer formed on the first part of the polycrystalline silicon layer; and a first A two-part polycrystalline silicon layer is formed on the polycrystalline silicon layer and serves as a top layer. According to the above object, the present invention further provides a metal-oxide semiconductor including: a semiconductor substrate; a gate oxide layer formed on the semiconductor substrate; and a multilayer structure gate including a portion of a polycrystalline silicon underlayer, a polycrystalline silicon intermediate layer, and Partial polycrystalline silicon top layer.

According to the above object, the present invention further provides a method for manufacturing a gate structure, including the following steps: providing a semiconductor substrate, a semiconductor layer is formed on the semiconductor substrate; and depositing the semiconductor substrate in an environment having hydrogen to form a first part A polycrystalline silicon layer; depositing a semiconductor substrate to form a polycrystalline silicon layer on the first partial polycrystalline silicon layer; and depositing a semiconductor substrate in an environment having hydrogen to form a second partial polycrystalline silicon layer on the polycrystalline silicon layer.

According to the above object, the present invention further provides a method for manufacturing a gate structure, comprising the following steps: providing a semiconductor substrate, forming a W layer on the semiconductor substrate, wherein the semiconductor substrate has a source drain; Depositing a semiconductor substrate to form a first portion of a polycrystalline silicon layer; depositing a semiconductor substrate to form a layer, f layer on a first portion of a polycrystalline silicon layer; depositing a semiconductor substrate in an environment having hydrogen to Layered > into a second part polycrystalline silicon layer; for the first part polycrystalline

565882

V. Description of the invention (4) The silicon layer, the polycrystalline silicon layer and the second part are formed as a mask on the second part of the polycrystalline silicon layer, and the first part of the polycrystalline silicon layer is engraved to form a gate; The Shi Xi layer is subjected to an ion implantation step; the patterned photoresist is used to pattern the photo resist Shi Xi layer, the polycrystalline Shi Xi layer and the second part to remove the patterned photo resist. Figure 2a 2f shows the manufacturing gate of the present invention. Please refer to the schematic diagram of the steps in Figures 2a-2f. C Consider Figure 2a. 'First', a semiconductor substrate 201 is provided. The semiconductor has an isolation region 202 and an isolation region 202. It is used to isolate an active region on the semiconductor substrate 2-10. The active region on the semiconductor substrate 201 is formed &# 11 层 2 () 3 'and in a processing chamber with hydrogen: the conductor substrate 201. Hit the deposition step. The isolation region 202 is, for example, a shallow trench isolation layer; the oxide layer 203 is, for example, silicon dioxide, and is used as a gate oxide layer. Referring to FIG. 2b, after the semiconductor substrate 201 is subjected to a deposition step in a process with hydrogen (η2) and silane (SiH4), a first portion of a polycrystalline silicon layer 204 will be formed on the oxide layer 203; A part of the polycrystalline silicon layer 204 is composed of polycrystalline silicon and amorphous silicon. Because the first part of the polycrystalline silicon layer 204 is recrystallized, the interface between the first part of the polycrystalline silicon layer 204 and the semiconductor substrate 201 will have a network structure to smooth the surface, so it can be tightly combined with the semiconductor substrate 201 Among them, the deposition method is chemical vapor deposition (vapor deposition), such as LPCVD or PECVD; and the flow rate of hydrogen is greater than that of silicon burning. Please refer to Figure 2c, only silane (SiH4) is provided in the processing chamber without mentioning

565882 V. Description of the invention (5) Supply hydrogen (H2), and then perform a deposition step on the semiconductor substrate 2 0 1 formed with the first part of the polycrystalline silicon layer 204 to form a polycrystalline silicon layer 2 0 5 on the first part of the polycrystalline silicon layer 2 0 4 . The deposition method is, for example, plasma-assisted chemical vapor deposition (PECVD); the crystals of the polycrystalline silicon layer 205 are arranged in a columnar shape, and the thickness is greater than that of the first polycrystalline silicon layer 204. Next, hydrogen (h2) is supplied to the silane-only (SiHJ) processing chamber, and the semiconductor substrate 021 is subjected to a deposition step. Referring to FIG. 2d, in a processing chamber having hydrogen (H2) and pethexane (SiH4) After the semiconductor substrate 201 is subjected to a deposition step, a second portion of the polycrystalline silicon layer 206 is formed on the polycrystalline silicon layer 205. The deposition step is, for example, plasma-assisted chemical vapor deposition (PECVD); Thicker than the second portion of the polycrystalline silicon layer 206. Because the second portion of the polycrystalline silicon layer 206 undergoes recrystallization, the exposed portion of the second portion of the polycrystalline silicon layer 206 will have a network structure to smooth the surface. Then, The second part of the polycrystalline silicon layer 206, the polycrystalline silicon layer 205, and the first part is a polycrystalline silicon layer 204 for ion implantation to form a p-type or n-type conductive layer. Among them, the ions for ion implantation are, for example, Arsenic ions (As) or boron (B) ions. Please refer to Figure 2e, and then, a patterned photoresist 207 is formed on the surface of the first polycrystalline silicon layer 206 on the surface of the first polycrystalline silicon layer 206. Patterned photoresist 207 will make Banfu 201 The part on the moving area where the gate is to be formed is covered. Please refer to Figure 2f for soil one, and then etch the second part of the polycrystalline silicon layer 206 with _chemical_2, and the silicon layer is more than enough. Part of the polycrystalline silicon layer 204 and the oxide layer 203 to form a gate electrode?

0503-7898TWF (N) · TSMC200M494; claire.ptd 5. Description of the invention (6): Dagger ::? 2 to 08 is composed of two parts of the polycrystalline crystalline layer 206a and the polycrystalline crystalline layer _ 4 blade crystalline hard layer 2 0 4 a. Subsequent steps may be followed by a shallow doping step, a spacer formation step, an ionization = source / depolarization step, etc. to form a -complete metal-oxygen half-to-be-deposited polycrystalline stone layer, usually required Applying high; = make Shi Xi deposition; and the formation of part of the recrystallized Shi Xi layer is not η :: lower; ® this, if you want to form a different Xi Jing hair layer in the same-processing chamber, a boat is abundant ff ^ ^ X P1 ^ ^; the slaves all need to adjust the temperature of the processing chamber to achieve the pole plate, only two: the purpose of the crystalline silicon layer. In the reaction formula of the gate silane provided by the present invention, which can be decomposed at high temperature, 邛: polysilicon: wind or hydrogen is provided as a deposition polysilicon layer or the reason, as long as it is at the same temperature. = Can be performed without adding chlorine gas or a part of the polycrystalline layer has high carrier activity (smooth surface roughness), smooth surface roughness (smo〇th surface roughness), and average resistance distribution "Petification" and so on. "Day 2", "Borrow (less Boron) controls you. If you use a part of the polycrystalline silicon layer for the whole leisure pole! The work will reduce the gate activity (i〇w actlvatl 〇)), and will make py thicker during the oxidation process. However, the thickness and bottom μ of the batch and wm emulsified layer prepared by the present invention, so a part of the polycrystalline silicon layer is used as the top: = edge =: using polycrystalline Shi Xilai's structure as a closed electrode ', the gate provided by the present invention, whether it is in contact with the semiconductor 565882, or the surface roughness of the substrate (7), also has the ability to use part of polycrystalline activity to make the plant The present invention has many advantages Electrical properties of high-poly silicon broken gate electrode empty body. With the introduction of hydrogen, it has the ability to form part of polycrystalline silicon to achieve increased production. Although the present invention is limited to the scope of the present invention, it can be seen in the attached application profile or if The ions in the low butterfly layer can provide the gate activation effect in time, and only share the gate polarity and partial load with the penetrating high carriers exposed by the adjustment layer or the shape quality. The processing chamber must be polycrystalline and the output can be optimized. This technique has the advantages of refining the gate surface; it has the advantages of active and polycrystalline cloth. The manufacturing method has the advantages of polycrystalline crushing and the same temperature in the processing chamber. The silicon layer is the purpose of the method. For example, if the person is not detached, the author shall prevail. After the ion implantation with a smooth surface, a better silicon layer with a better silicon gate can produce a smooth surface at the same time, and Low 'effectively improves the effect of the transistor with or without the effect of selection, which is simple and low-cost to control, but it is not intended to depart from the scope of protection of the spirit of the present invention.

565882 Brief description of the drawings In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Section 1 a- Figure 1c is a schematic flow chart showing the conventional steps of manufacturing a gate electrode. Figures 2a-2f are schematic diagrams showing the steps of manufacturing the gate electrode according to the present invention. Explanation of symbols: 1 01 ~ semiconductor substrate; 102 ~ isolated area; 103 ~ oxide layer; 104 ~ polycrystalline silicon layer; 105 ~ patterned photoresist; 201 ~ semiconductor substrate; 202 ~ isolated area; 203 ~ oxide layer; 204 ~ first polycrystalline silicon layer; 205 ~ polycrystalline silicon layer; 206 ~ second polycrystalline silicon layer; 207 ~ patterned photoresistor; 208 ~ gate.

0503-7898TW (N): TSMC2001-1494; claire.ptd Page 11

Claims (1)

565882 6. Scope of patent application 1. A gate structure formed on a semiconductor substrate, including: at least a first part of a polycrystalline silicon layer for use as a bottom layer; at least one polycrystalline silicon layer formed on the first part of the polycrystalline silicon layer; and at least A second portion of the polycrystalline silicon layer is formed on the polycrystalline silicon layer and serves as a top layer. —Z • The gate structure described in item 1 of the scope of patent application, wherein the part of the polycrystalline silicon layer is formed in a processing chamber having hydrogen. _ 3. The gate structure described in item 1 of the scope of the patent application, wherein the second part of the polycrystalline silicon layer is formed in a processing chamber having hydrogen. 4. The gate structure according to item 1 of the scope of the patent application, wherein the thickness of the polysilicon layer is greater than that of the first polycrystalline silicon layer and the second polycrystalline fragment layer. 5. A metal-oxide semiconductor comprising: a semiconductor substrate; a gate oxide layer formed on the semiconductor substrate; and a multilayer structure gate including a portion of a polycrystalline silicon bottom layer, a polycrystalline silicon intermediate layer, and a portion of a polycrystalline silicon top layer. 6. The gold-oxygen semiconductor according to item 5 of the scope of patent application, wherein the part of the polycrystalline silicon bottom layer is formed in a processing chamber having hydrogen. 7. The gold-oxygen semiconductor according to item 5 of the scope of the patent application, wherein the top portion of the polycrystalline silicon is formed in a processing chamber having hydrogen. 8. The gold-oxygen semiconductor according to item 5 of the scope of patent application, wherein the thickness of the polycrystalline silicon layer is greater than that of the polycrystalline silicon bottom layer and the polycrystalline silicon top layer. 0503-7898 ^ (N) »TSMC2001-I494; claire.ptd 565882 ^ A method for manufacturing a gate structure, comprising the following steps: providing a semiconductor substrate with a via layer formed on the semiconductor substrate; performing a plutonium-partial polycrystalline silicon layer on the semiconductor substrate in an environment having hydrogen gas; The substrate is deposited to deposit the semiconductor substrate on the first portion of the polycrystalline silicon drawer in an environment with hydrogen to form a second portion of the polycrystalline silicon layer on the crystalline silicon layer. ^ I 〇 • The manufacturer of the gate structure as described in item 9 of the scope of the patent application, wherein the interlayer is a gate oxide layer. 〆II. The method for manufacturing a gate structure as described in item 9 of the scope of the patent application, wherein the thickness of the polycrystalline silicon layer is greater than the first part of the polycrystalline silicon layer and the twelfth type of method for manufacturing a gate structure, including the following steps: k for a semiconductor substrate, forming a interlayer on the semiconductor substrate; depositing the semiconductor substrate to form a first part of a polycrystalline silicon layer in an environment with hydrogen; depositing the semiconductor substrate to form the first part of the polycrystalline silicon A polycrystalline silicon layer is formed on the layer; the semiconductor substrate is deposited in an environment with hydrogen to form a second polycrystalline silicon layer on the polycrystalline silicon layer; ™ the first polycrystalline silicon layer and the polycrystalline silicon Layer and the second part of the crystalline silicon layer to perform an ion implantation step; forming a patterned photoresist on the second part of the polycrystalline silicon layer, and 565882 The scope of the patent application for the application of the photoresist is a mask, which etches the first and second portions of the polycrystalline silicon layer to form and remove the patterned photoresist. Part of the polycrystalline silicon layer, the polycrystalline silicon layer / gate, and the method of manufacturing a gate structure as described in the item 2 of the patent application ', wherein the interlayer is a gate oxide layer. 1 4 · The method for manufacturing a gate structure according to item 2 of the scope of the patent application, wherein the thickness of the polycrystalline silicon layer is greater than that of the first polycrystalline silicon layer and the second polycrystalline silicon layer. 15 · The method for manufacturing a gate structure according to item 12 of the scope of the patent application, wherein the ion in the ion implantation step is arsenic or boron. 0503-7898TW (N); TSMC2001-1494; claire.ptd page 14